coreboot November 2007

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[LinuxBIOS] [PATCH] K8T890 V-link fine-tune
by Rudolf Marek 15 Nov '07

15 Nov '07

Hello, Attached patch fine-tunes the V-link bus between K8T890 and VT8237R and set it to 8X transfer rate (up to 1066 MB/s) similar code placed here would be needed for VT8237A/S etc. Using VIA recommended values despite they are for K8T890CF, this is K8T890CE (still dont know what is exactly different). This patch enables the parity error reporting on V-Link, so it enables NMI generation for the SERR# errors. The NMI may not be generated, maybe port 61h needs some tuning too. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Btw there is FID/VID patch pending too. Rudolf

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[LinuxBIOS] r2974 - in trunk/LinuxBIOSv2/src/southbridge/via: k8t890 vt8237r
by svn＠openbios.org 15 Nov '07

15 Nov '07

Author: uwe Date: 2007-11-15 16:52:42 +0100 (Thu, 15 Nov 2007) New Revision: 2974 Modified: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_ctrl.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_dram.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_error.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host_ctrl.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c Log: Various cosmetic fixes and improvements (trivial). - Use 'static' where appropriate. - Use 'const' where appropriate. - Indentation fixes. - Add comment wrt init code which is only valid for VT8237R. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_ctrl.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_ctrl.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_ctrl.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -41,12 +41,17 @@ * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 */ -static void ctrl_init(struct device *dev) +static void ctrl_init_vt8237r(struct device *dev) { u8 reg; + + /* + * This init code is valid only for the VT8237R! For different + * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R) + * and VT8251) a different init code is required. + */ device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - if (!devsb) return; @@ -132,17 +137,17 @@ pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); } -static struct device_operations ctrl_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = ctrl_enable, - .init = ctrl_init, - .ops_pci = 0, +static const struct device_operations ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = ctrl_enable, + .init = ctrl_init_vt8237r, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_7, + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_7, }; Modified: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_dram.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_dram.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_dram.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -63,16 +62,16 @@ pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); } -static struct device_operations dram_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = dram_enable, - .ops_pci = 0, +static const struct device_operations dram_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = dram_enable, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &dram_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_3, + .ops = &dram_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_3, }; Modified: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_error.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_error.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_error.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -33,15 +33,15 @@ } static const struct device_operations error_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = error_enable, - .ops_pci = 0, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = error_enable, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_1, + .ops = &error_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_1, }; Modified: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -30,16 +30,16 @@ pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); } -static struct device_operations host_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = host_enable, - .ops_pci = 0, +static const struct device_operations host_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_enable, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &host_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_0, + .ops = &host_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_0, }; Modified: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host_ctrl.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host_ctrl.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_host_ctrl.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -78,16 +78,16 @@ dump_south(dev); } -static struct device_operations host_ctrl_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = host_ctrl_enable, - .ops_pci = 0, +static const struct device_operations host_ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_ctrl_enable, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &host_ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_2, + .ops = &host_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_2, }; Modified: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -21,10 +21,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> -void peg_init(struct device *dev) +static void peg_init(struct device *dev) { u8 reg; @@ -78,7 +77,7 @@ dump_south(dev); } -void pcie_init(struct device *dev) +static void pcie_init(struct device *dev) { u8 reg; @@ -113,52 +112,52 @@ dump_south(dev); } -static struct device_operations peg_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .enable = peg_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, +static const struct device_operations peg_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = peg_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, }; -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .enable = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, +static const struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &peg_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEG, + .ops = &peg_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEG, }; static const struct pci_driver pcie_drvd3f0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX0, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX0, }; static const struct pci_driver pcie_drvd3f1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX1, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX1, }; static const struct pci_driver pcie_drvd3f2 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX2, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX2, }; static const struct pci_driver pcie_drvd3f3 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX3, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX3, }; Modified: trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -19,13 +19,11 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> - #include "k8t890.h" -void mmconfig_set_resources(device_t dev) +static void mmconfig_set_resources(device_t dev) { struct resource *resource; u8 reg; @@ -106,16 +104,16 @@ apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24); } -static struct device_operations traf_ctrl_ops = { - .read_resources = apic_mmconfig_read_resources, - .set_resources = mmconfig_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = traf_ctrl_enable, - .ops_pci = 0, +static const struct device_operations traf_ctrl_ops = { + .read_resources = apic_mmconfig_read_resources, + .set_resources = mmconfig_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = traf_ctrl_enable, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &traf_ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_5, + .ops = &traf_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_5, }; Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> #include <pc80/keyboard.h> #include "chip.h" Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -21,7 +21,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> #include "vt8237r.h" Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -23,7 +23,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> @@ -48,7 +47,7 @@ extern void dump_south(device_t dev); -struct ioapicreg { +static struct ioapicreg { u32 reg; u32 value_low; u32 value_high; @@ -146,7 +145,7 @@ * Set up the power management capabilities directly into ACPI mode. * This avoids having to handle any System Management Interrupts (SMIs). */ -void setup_pm(device_t dev) +static void setup_pm(device_t dev) { /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -299,7 +298,7 @@ rtc_init(0); } -void vt8237r_read_resources(device_t dev) +static void vt8237r_read_resources(device_t dev) { struct resource *res; @@ -320,7 +319,7 @@ * than standard PC I/O addresses), however it does control the ISA bus * and so we need to manually call enable childrens resources on that bus. */ -void vt8237r_enable_resources(device_t dev) +static void vt8237r_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c 2007-11-14 17:57:04 UTC (rev 2973) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c 2007-11-15 15:52:42 UTC (rev 2974) @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pci_ids.h> #define SATA_MISC_CTRL 0x45

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[LinuxBIOS] IRQ question
by Feng, Libo 15 Nov '07

15 Nov '07

Hi, all, A simple question: when talking about IRQ, you mean one of the 256 interrupt vectors within x86, or one of the pins of APIC, or one of the pins of 8259? I always got confused by it. Best Regards 丰立波 Feng Libo @ AMD Ext: 20906 Mobile Phone: 13683249071 Office Phone: 0086-010-62801406

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[LinuxBIOS] quote heard today at SC 07
by ron minnich 15 Nov '07

15 Nov '07

"EFI is a really bad OS in search of a boot loader" ron

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[LinuxBIOS] v3: status on real hardware
by Carl-Daniel Hailfinger 15 Nov '07

15 Nov '07

Hi, while taking a look at stage0 and stage1 code in v3, I was surprised to see no coherent structure in the code for Geode LX boards. While some of this may be due to dead code, I'd like to know: * which board can serve as structural reference * which board is working best. Once I know that, I can send cleanup patches and maybe even kill a few functions and files. Regards, Carl-Daniel

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[LinuxBIOS] r2973 build service
by LinuxBIOS information 14 Nov '07

14 Nov '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 2973 to the LinuxBIOS source repository and caused the following changes: Change Log: Gigabyte M57SLI: Fix watchdog clocksource to be external, not internal. Reason: The existing code does not tell us why it sets the watchdog clock at all, but since it appears in cache_as_ram_auto.c instead of the usual place (Config.lb) there has to be some meaning to it. Simply do what the proprietary bios does: Use the external clock source. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2973&device=serengeti_che… Compilation of asus:a8v-e_se is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2973&device=a8v-e_se&vend… Compilation of iwill:dk8_htx is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2973&device=dk8_htx&vendo… Compilation of msi:ms9185 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2973&device=ms9185&vendor… Compilation of msi:ms9282 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2973&device=ms9282&vendor… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2973&device=h8dmr&vendor=… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] [PATCH] v2: Fix GA-M57SLI watchdog clocksource
by Carl-Daniel Hailfinger 14 Nov '07

14 Nov '07

Gigabyte M57SLI: Fix watchdog clocksource to be external, not internal. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2007-11-14 16:47:50.000000000 +0100 +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2007-11-14 16:47:50.000000000 +0100 @@ -273,8 +273,8 @@ } pnp_enter_ext_func_mode(SERIAL_DEV); - /* The following line will set CLKIN to 24 MHz */ - pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 1); + /* The following line will set CLKIN to 24 MHz, external */ + pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP); /* Is serial flash enabled? Then enable writing to serial flash. */ if (tmp & 0x0e) {

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[LinuxBIOS] r2973 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
by svn＠openbios.org 14 Nov '07

14 Nov '07

Author: hailfinger Date: 2007-11-14 18:57:04 +0100 (Wed, 14 Nov 2007) New Revision: 2973 Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c Log: Gigabyte M57SLI: Fix watchdog clocksource to be external, not internal. Reason: The existing code does not tell us why it sets the watchdog clock at all, but since it appears in cache_as_ram_auto.c instead of the usual place (Config.lb) there has to be some meaning to it. Simply do what the proprietary bios does: Use the external clock source. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2007-11-14 15:09:30 UTC (rev 2972) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2007-11-14 17:57:04 UTC (rev 2973) @@ -273,8 +273,8 @@ } pnp_enter_ext_func_mode(SERIAL_DEV); - /* The following line will set CLKIN to 24 MHz */ - pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 1); + /* The following line will set CLKIN to 24 MHz, external */ + pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP); /* Is serial flash enabled? Then enable writing to serial flash. */ if (tmp & 0x0e) {

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[LinuxBIOS] r2972 build service
by LinuxBIOS information 14 Nov '07

14 Nov '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 2972 to the LinuxBIOS source repository and caused the following changes: Change Log: Autodetect presence of serial flash and set up the board accordingly. This enables us to have only one configuration and one set of code for all revisions of the Gigabyte GA-M57SLI-S4. Flash is now setup correctly for both SPI and LPC flash. Detection of SPI flash in flashrom on rev. 2.x boards now hangs instead of failing. However, that is just an effect of the combination of incomplete initialization of the SPI controller and paranoid checks in the flashrom SPI code. If anyone wants to work on that, he needs a logic analyzer or creative imagination. Hint: LPC-to-SPI read passthrough, clock signal. Remaining issues for the M57SLI: Fan/environment control. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Harald Gutmann <harald.gutmann(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2972&device=serengeti_che… Compilation of asus:a8v-e_se is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2972&device=a8v-e_se&vend… Compilation of iwill:dk8_htx is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2972&device=dk8_htx&vendo… Compilation of msi:ms9185 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2972&device=ms9185&vendor… Compilation of msi:ms9282 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2972&device=ms9282&vendor… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2972&device=h8dmr&vendor=… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] #87: flashrom issues on m57sli-s4
by LinuxBIOS 14 Nov '07

14 Nov '07

#87: flashrom issues on m57sli-s4 ---------------------------------+------------------------------------------ Reporter: ward | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ There is a problem with flashrom; it won't work reliably when the machine is booted under LinuxBIOS on the m57sli-s4. This is what I used to see: It works maybe 1 out of 10 times - it always works when booted with the proprietary BIOS. I can tell while it's flashing if it is good or not good: the speed of the flashing is moderately fast for a good flash. For a bad flash, it is either too fast, too slow, or it varies a lot during the flash. This is what I'm seeing today (with the latest rev of flashrom, 2744): Flashrom jumps from page 15 to page 224 while flashing, and then fails to verify. I've tried with several different chis (all of the same type though). {{{ # ./flashrom -vvvv -w /home/ward/Desktop/buildrom/buildrom-devel/deploy /gigabyte-m57sli.rom -V Calibrating delay loop... 537M loops per second. ok Found canidate at: 00000530-00000e2c Found LinuxBIOS table at: 00000530 lb_table found at address 0xb7e40530 LinuxBIOS header(24) checksum: e2db table(2300) checksum: 826c entries: 14 vendor id: GIGABYTE part id: m57sli Found chipset "NVIDIA MCP55": Enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for At29C040A, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for At29C020, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for Mx29f002, 256 KB probe_29f002: id1 0xbf, id2 0x5b Probing for SST29EE020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST28SF040A, 512 KB probe_28sf040: id1 0xff, id2 0xff Probing for SST39SF010A, 128 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39SF020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39SF040, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39VF020, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF040B, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF040, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xbf, id2 0x5b SST49LF080A found at physical address: 0xfff00000 Flash part is SST49LF080A (1024 KB) LinuxBIOS last image size (not rom size) is 1048576 bytes. MANUFACTURER: GIGABYTE MAINBOARD ID: m57sli This firmware image matches this motherboard. Programming Page: 0255 at address: 0x000ff000 Verifying flash address: 0x00000000 - FAILED }}} I should note that I'm using a bios savior to swap flash chips, and that the socket has been soldered onto the board manually. But under the proprietary bios there is never a problem, so... -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87> LinuxBIOS <http://www.linuxbios.org/>

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coreboot November 2007