coreboot August 2006

coreboot@coreboot.org

39 participants
110 discussions

[LinuxBIOS] r2372 - trunk/LinuxBIOSv2/targets/olpc/rev_a
by svn＠openbios.org 11 Aug '06

11 Aug '06

Author: rminnich Date: 2006-08-11 02:08:37 +0200 (Fri, 11 Aug 2006) New Revision: 2372 Modified: trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb Log: build 1024-128k binary as per requests. Modified: trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb =================================================================== --- trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb 2006-08-10 09:38:39 UTC (rev 2371) +++ trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb 2006-08-11 00:08:37 UTC (rev … [View More]

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[LinuxBIOS] boot windows, BSD and solaris on x86
by Lu, Yinghai 10 Aug '06

10 Aug '06

Eric, Anyone try to use kexec to boot windows, BSD and solaris on x86? YH

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[LinuxBIOS] AMD Turion - AGESA
by jf simon 10 Aug '06

10 Aug '06

Hi, The company i worked for has designed a card that uses the AMD Turion. It uses the PHOENIX Bios. I am trying to port linuxbios to it. But among other issues, one hardware engineer told me to make sure that linuxbios was using the latest AGESA code from AMD (from what i understand that code changes the CPU processor state, frequency,...)as it seems we had trouble in the past getting the right BIOS with the latest AGESA code. How does linuxbios manage to do the same thing as the agesa … [View More]

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[LinuxBIOS] LinuxBIOS r2371 build changes
by LinuxBIOS information 10 Aug '06

10 Aug '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2371 to the LinuxBIOS source repository and caused the following changes: Change Log: fix serial initialization (from Uwe Hermann) Build Log: Compilation of artecgroup:dbe61 is still broken. If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. … [View More]

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[LinuxBIOS] r2371 - trunk/LinuxBIOSv2/src/superio/ite/it8671f
by svn＠openbios.org 10 Aug '06

10 Aug '06

Author: stepan Date: 2006-08-10 11:38:39 +0200 (Thu, 10 Aug 2006) New Revision: 2371 Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/chip.h trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c Log: fix serial initialization (from Uwe Hermann) Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/chip.h ===============================================================… [View More]==== --- trunk/LinuxBIOSv2/src/superio/ite/it8671f/chip.h 2006-08-10 03:23:48 UTC (rev 2370) +++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/chip.h 2006-08-10 09:38:39 UTC (rev 2371) @@ -19,14 +19,6 @@ #ifndef _SUPERIO_ITE_IT8671F #define _SUPERIO_ITE_IT8671F -// TODO: Unused? -// #ifndef SIO_COM1 -// #define SIO_COM1_BASE 0x3F8 -// #endif -// #ifndef SIO_COM2 -// #define SIO_COM2_BASE 0x2F8 -// #endif - #include <pc80/keyboard.h> #include <uart8250.h> Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h 2006-08-10 03:23:48 UTC (rev 2370) +++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h 2006-08-10 09:38:39 UTC (rev 2371) @@ -16,20 +16,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// TODO: Untested, cut'n'pasted from some other file so it's probably wrong. -// #define IT8671F_FDC 0x00 /* Floppy */ -// #define IT8671F_PP 0x01 /* Parallel port */ +/* TODO: Find datasheet and check for correct values. */ +#define IT8671F_FDC 0x00 /* Floppy */ +/* #define IT8671F_PP 0x01 */ /* Parallel port */ #define IT8671F_SP2 0x02 /* Com2 */ #define IT8671F_SP1 0x03 /* Com1 */ -// #define IT8671F_SWC 0x04 -// #define IT8671F_KBCM 0x05 /* Mouse */ #define IT8671F_KBCK 0x06 /* Keyboard */ -// #define IT8671F_GPIO 0x07 -// #define IT8671F_ACB 0x08 -// #define IT8671F_FSCM 0x09 -// #define IT8671F_WDT 0x0A -// #define IT8671F_GMP 0x0B -// #define IT8671F_MIDI 0x0C -// #define IT8671F_VLM 0x0D -// #define IT8671F_TMS 0x0E +/* #define IT8671F_FAN 0x09 */ Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c 2006-08-10 03:23:48 UTC (rev 2370) +++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c 2006-08-10 09:38:39 UTC (rev 2371) @@ -19,11 +19,73 @@ #include <arch/romcc_io.h> #include "it8671f.h" +/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA SIO_BASE+1 + +/* TODO: These values are actually from the IT8673F datasheet; check if + they're also valid for the IT8671F. */ +#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control. */ +#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8671F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ + +#define IT8671F_ADDRESS_PORT 0x279 + +/* Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. */ +static const uint8_t init_values[] = { + 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, + 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, + 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, + 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, +}; + +/* The content of IT8671F_CONFIG_REG_LDN (index 07h) must be set to the + * LDN the register belongs to, before you can access the register. */ +static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +{ + outb(IT8671F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +/* Enable the peripheral devices on the IT8671F Super IO chip. */ static void it8671f_enable_serial(device_t dev, unsigned iobase) { - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); + uint8_t i; + + /* (1) Enter the configuration state (MB PnP mode). */ + + /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ + /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ + /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ + /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ + outb(0x86, IT8671F_ADDRESS_PORT); + outb(0x80, IT8671F_ADDRESS_PORT); + outb(0x55, IT8671F_ADDRESS_PORT); + outb(0x55, IT8671F_ADDRESS_PORT); + + /* Sequentially write the 32 special values. */ + for (i = 0; i < 32; i++) { + outb(init_values[i], SIO_BASE); + } + + /* (2) Modify the data of configuration registers. */ + + /* Enable parallel port, serial port 1, serial port 2, floppy. */ + it8671f_sio_write(0x00, 0x23, 0x0f); + + /* Activate serial port 1 and 2. */ + it8671f_sio_write(0x01, 0x30, 0x1); + it8671f_sio_write(0x02, 0x30, 0x1); + + /* Select 24MHz CLKIN and clear software suspend mode. */ + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00); + + /* (3) Exit the configuration state (MB PnP mode). */ + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); } Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c 2006-08-10 03:23:48 UTC (rev 2370) +++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c 2006-08-10 09:38:39 UTC (rev 2371) @@ -16,12 +16,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// #include <arch/io.h> -// #include <device/device.h> -// #include <device/pnp.h> -// #include <console/console.h> -// #include <string.h> -// #include <bitops.h> #include <uart8250.h> #include <pc80/keyboard.h> #include "chip.h" @@ -38,7 +32,10 @@ conf = dev->chip_info; - switch(dev->path.u.pnp.device) { + switch (dev->path.u.pnp.device) { + case IT8671F_FDC: + /* TODO. */ + break; case IT8671F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); @@ -63,18 +60,13 @@ .init = init, }; -// TODO. +/* TODO: Find and check datasheet. */ static struct pnp_info pnp_dev_info[] = { -// { &ops, IT8671F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, -// { &ops, IT8671F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, + { &ops, IT8671F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, + /* { &ops, IT8671F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, */ { &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, { &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, -// { &ops, IT8671F_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, -// { &ops, IT8671F_KBCM, PNP_IRQ0 }, -{ &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, -// { &ops, IT8671F_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, -// { &ops, IT8671F_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, -// { &ops, IT8671F_RTC, PNP_IO0 | PNP_IO1, { 0xfffe, 0 }, {0xfffe, 0x4} }, + { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, }; static void enable_dev(struct device *dev) [View Less]

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[LinuxBIOS] LinuxBIOS r2370 build changes
by LinuxBIOS information 10 Aug '06

10 Aug '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "rminnich" checked in revision 2370 to the LinuxBIOS source repository and caused the following changes: Change Log: change from AMD for the IRQ10 problem. Build Log: Compilation of artecgroup:dbe61 is still broken. If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. … [View More]

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[LinuxBIOS] r2370 - in trunk/LinuxBIOSv2/src: mainboard/olpc/rev_a northbridge/amd/gx2
by svn＠openbios.org 10 Aug '06

10 Aug '06

Author: rminnich Date: 2006-08-10 05:23:48 +0200 (Thu, 10 Aug 2006) New Revision: 2370 Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c Log: change from AMD for the IRQ10 problem. Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c 2006-08-09 02:21:49 UTC (rev 2369) +++ trunk/LinuxBIOSv2/src/… [View More]

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[LinuxBIOS] RD1-PL on EPIA-M10000 problem
by lists＠actweb.info 09 Aug '06

09 Aug '06

hi can someone confirm that i have the following correct? i have an EPIA-M m/board with an SST39SF020A bios chip, along with an RD1-PL 2Mbit bios savour, are these both 2Mb chips? i have tried writing the RD1 with a image file, but it always fails :( anyone any pointers? have so far tried to write image aprox 8 times, still with no luck :( this is the output from flashrom :- Original BIOS # ./flashrom Calibrating delay loop... ok No LinuxBIOS table found. Enabling flash write on VT8235...… [View More]

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[LinuxBIOS] Linux & memory regions
by Indrek Kruusa 09 Aug '06

09 Aug '06

Hi! I am looking for clarification about what and how (Linux)BIOS should provide to kernel about memory size/memory regions. I'm wondering about linuxbios table: there are lot of different variation with new_resource/ram_resource, where those calls are placed, what regions they are setting up, are those regions 0-TopOfSysRAM, or 0-640/768-TopOfSysRAM etc. And reportedly it all works with linux kernel. I'm not sure how to properly control linuxbios table content - and is this table … [View More]

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[LinuxBIOS] LinuxBIOS r2369 build changes
by LinuxBIOS information 09 Aug '06

09 Aug '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "rminnich" checked in revision 2369 to the LinuxBIOS source repository and caused the following changes: Change Log: mods for the ultra40 bringup. This now builds.amd gx2 north -- don't set anything in the north, it conflicts with vsasettings. So we have our own pci_set_resources that is essentially ano-op -- just calls the kids.olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD … [View More]

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coreboot August 2006