coreboot August 2006

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[LinuxBIOS] r2369 - in trunk/LinuxBIOSv2: src/mainboard/sunw/ultra40 src/northbridge/amd/gx2 targets/olpc/rev_a targets/sunw/ultra40
by svn＠openbios.org 09 Aug '06

09 Aug '06

Author: rminnich Date: 2006-08-09 04:21:49 +0200 (Wed, 09 Aug 2006) New Revision: 2369 Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/chip.h trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/mptable.c trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb Log: mods for the ultra40 bringup. This now builds. amd gx2 north -- don't set anything in the north, it conflicts with vsa settings. So we have our own pci_set_resources that is essentially a no-op -- just calls the kids. olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD NOT have been set -- it is untested and caused real trouble. Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb 2006-08-08 21:42:18 UTC (rev 2368) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb 2006-08-09 02:21:49 UTC (rev 2369) @@ -176,11 +176,12 @@ ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2895" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895 +default MAINBOARD_PART_NUMBER="ultra40" +default MAINBOARD_VENDOR="sunw" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40 + ### ### LinuxBIOS layout values ### Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c 2006-08-08 21:42:18 UTC (rev 2368) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c 2006-08-09 02:21:49 UTC (rev 2369) @@ -174,7 +174,7 @@ sio_gpio_setup(); - setup_s2895_resource_map(); + setup_ultra40_resource_map(); needs_reset = setup_coherent_ht_domain(); Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2006-08-08 21:42:18 UTC (rev 2368) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2006-08-09 02:21:49 UTC (rev 2369) @@ -236,7 +236,7 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - setup_s2895_resource_map(); + setup_ultra40_resource_map(); needs_reset = setup_coherent_ht_domain(); Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/chip.h 2006-08-08 21:42:18 UTC (rev 2368) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/chip.h 2006-08-09 02:21:49 UTC (rev 2369) @@ -1,6 +1,6 @@ -extern struct chip_operations mainboard_tyan_s2895_ops; +extern struct chip_operations mainboard_sunw_ultra40_ops; -struct mainboard_tyan_s2895_config { +struct mainboard_sunw_ultra40_config { // int fixup_scsi; // int fixup_vga; }; Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/mptable.c 2006-08-08 21:42:18 UTC (rev 2368) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/mptable.c 2006-08-09 02:21:49 UTC (rev 2369) @@ -35,8 +35,8 @@ void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; - static const char productid[12] = "S2895 "; + static const char oem[8] = "SUNW "; + static const char productid[12] = "ultra40 "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c 2006-08-08 21:42:18 UTC (rev 2368) +++ trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c 2006-08-09 02:21:49 UTC (rev 2369) @@ -283,9 +283,56 @@ irq_init_steering(dev, nb->irqmap); } +/* due to vsa interactions, we need not not touch the nb settings ... */ +/* this is a test -- we are not sure it will work -- but it ought to */ +static void set_resources(struct device *dev) +{ + struct resource *resource, *last; + unsigned link; + uint8_t line; + +#if 0 + last = &dev->resource[dev->resources]; + + for(resource = &dev->resource[0]; resource < last; resource++) { + pci_set_resource(dev, resource); + } +#endif + for(link = 0; link < dev->links; link++) { + struct bus *bus; + bus = &dev->link[link]; + if (bus->children) { + assign_resources(bus); + } + } + +#if 0 + /* set a default latency timer */ + pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); + + /* set a default secondary latency timer */ + if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { + pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); + } + + /* zero the irq settings */ + line = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if (line) { + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); + } + /* set the cache line size, so far 64 bytes is good for everyone */ + pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); +#endif +} + + + static struct device_operations northbridge_operations = { .read_resources = pci_dev_read_resources, +#if 0 .set_resources = pci_dev_set_resources, +#endif + .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .enable = 0, Modified: trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb =================================================================== --- trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb 2006-08-08 21:42:18 UTC (rev 2368) +++ trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb 2006-08-09 02:21:49 UTC (rev 2369) @@ -5,7 +5,7 @@ # Don't let LinuxBIOS compress the payload # option CONFIG_COMPRESSED_ROM_STREAM=0 -option CONFIG_PRECOMPRESSED_ROM_STREAM=1 +#option CONFIG_PRECOMPRESSED_ROM_STREAM=1 # leave 64k for vsa option ROM_SIZE=1024*1024-64*1024 Modified: trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb 2006-08-08 21:42:18 UTC (rev 2368) +++ trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb 2006-08-09 02:21:49 UTC (rev 2369) @@ -29,7 +29,7 @@ # payload ../../../payloads/filo.zelf # payload ../../../payloads/tg3.zelf # payload ../../../payloads/tg3--filo_hda2_vga.zelf - payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf + payload /etc/hosts # payload ../../../payloads/forcedeth_vga.zelf # payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf # payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf @@ -58,7 +58,7 @@ # payload ../../../payloads/filo.zelf # payload ../../../payloads/tg3.zelf # payload ../../../payloads/tg3--filo_hda2_vga.zelf - payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf + payload /etc/hosts # payload ../../../payloads/forcedeth_vga.zelf # payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf # payload ../../../payloads/tg3_vga.zelf

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[LinuxBIOS] LinuxBIOS r2368 build changes
by LinuxBIOS information 08 Aug '06

08 Aug '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "rminnich" checked in revision 2368 to the LinuxBIOS source repository and caused the following changes: Change Log: fix up the links for the ultra 40 -- i/o on ht 1 on each cpu Build Log: Compilation of artecgroup:dbe61 is still broken. Compilation of sunw:ultra40 is still broken. If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] r2368 - trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40
by svn＠openbios.org 08 Aug '06

08 Aug '06

Author: rminnich Date: 2006-08-08 23:42:18 +0200 (Tue, 08 Aug 2006) New Revision: 2368 Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb Log: fix up the links for the ultra 40 -- i/o on ht 1 on each cpu Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb 2006-08-08 18:02:12 UTC (rev 2367) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb 2006-08-08 21:42:18 UTC (rev 2368) @@ -201,7 +201,8 @@ end device pci_domain 0 on chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on + device pci 18.0 on end # link 0 + device pci 18.0 on # link1 # devices on link 0, link 0 == LDT 0 chip southbridge/nvidia/ck804 device pci 0.0 on end # HT @@ -318,30 +319,16 @@ register "mac_eeprom_addr" = "0x51" end end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - chip drivers/pci/onboard - device pci 6.0 on end # lsi scsi - device pci 6.1 on end - end - end - device pci 1.1 on end - end - end # device pci 18.0 + device pci 18.0 on end # link 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 chip northbridge/amd/amdk8 - device pci 19.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 19.0 on end # link 0 + device pci 19.0 on + # devices on link 1, link 1 == LDT 1 chip southbridge/nvidia/ck804 device pci 0.0 on end # HT device pci 1.0 on end # LPC @@ -366,21 +353,10 @@ end # device pci 19.0 device pci 19.0 on end - device pci 19.0 on end device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end end end # PCI domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 off end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end end #root_complex

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[LinuxBIOS] LinuxBIOS r2367 build changes
by LinuxBIOS information 08 Aug '06

08 Aug '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "rminnich" checked in revision 2367 to the LinuxBIOS source repository and caused the following changes: Change Log: fix up config space. Build Log: Compilation of artecgroup:dbe61 is still broken. Compilation of sunw:ultra40 has been broken If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] r2367 - trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40
by svn＠openbios.org 08 Aug '06

08 Aug '06

Author: rminnich Date: 2006-08-08 20:02:12 +0200 (Tue, 08 Aug 2006) New Revision: 2367 Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/resourcemap.c Log: fix up config space. Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/resourcemap.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/resourcemap.c 2006-08-07 20:02:02 UTC (rev 2366) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/resourcemap.c 2006-08-08 18:02:12 UTC (rev 2367) @@ -3,7 +3,7 @@ * */ -static void setup_s2895_resource_map(void) +static void setup_ultra40_resource_map(void) { static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ @@ -253,11 +253,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - + PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103, + PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113, + PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xec), 0x0000, 0x00000000, }; int max;

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[LinuxBIOS] Tyan s2865
by Richard Smith 08 Aug '06

08 Aug '06

I've got someone asking about the Tyan s2865 which is an nVidia based board. Whats the status on these parts? The board is not listed in the Tyan dir. 0000:00:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) Subsystem: Tyan Computer: Unknown device 2865 Flags: bus master, 66Mhz, fast devsel, latency 0 Capabilities: [44] #08 [01e0] Capabilities: [e0] #08 [a801] 0000:00:01.0 ISA bridge: nVidia Corporation: Unknown device 0050 (rev a3) Subsystem: Tyan Computer: Unknown device 2865 Flags: bus master, 66Mhz, fast devsel, latency 0 0000:00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2) Subsystem: Tyan Computer: Unknown device 2865 Flags: 66Mhz, fast devsel, IRQ 12 I/O ports at fc00 [size=32] I/O ports at 1c00 [size=64] I/O ports at 1c40 [size=64] Capabilities: [44] Power Management version 2 0000:00:02.0 USB Controller: nVidia Corporation CK804 USB Controller (rev a2) (prog-if 10 [OHCI]) Subsystem: Tyan Computer: Unknown device 2865 Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 10 Memory at febff000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 0000:00:02.1 USB Controller: nVidia Corporation CK804 USB Controller (rev a3) (prog-if 20 [EHCI]) Subsystem: Tyan Computer: Unknown device 2865 Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 11 Memory at febfe000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] #0a [2098] Capabilities: [80] Power Management version 2 0000:00:04.0 Multimedia audio controller: nVidia Corporation CK804 AC'97 Audio Controller (rev a2) Subsystem: Tyan Computer: Unknown device 2865 Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 12 I/O ports at f000 [size=256] I/O ports at ec00 [size=256] Memory at febfd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 0000:00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev a2) (prog-if 8a [Master SecP PriP]) Subsystem: Tyan Computer: Unknown device 2865 Flags: bus master, 66Mhz, fast devsel, latency 0 I/O ports at e000 [size=16] Capabilities: [44] Power Management version 2 0000:00:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Tyan Computer: Unknown device 2865 Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 11 I/O ports at 09f0 [size=8] I/O ports at 0bf0 [size=4] I/O ports at 0970 [size=8] I/O ports at 0b70 [size=4] I/O ports at cc00 [size=16] Memory at febfb000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 0000:00:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: nVidia Corporation: Unknown device cb84 Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 10 I/O ports at 09e0 [size=8] I/O ports at 0be0 [size=4] I/O ports at 0960 [size=8] I/O ports at 0b60 [size=4] I/O ports at b800 [size=16] Memory at febfa000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 0000:00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev a2) (prog-if 01 [Subtractive decode]) Flags: bus master, 66Mhz, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=02, sec-latency=32 I/O behind bridge: 00009000-0000afff Memory behind bridge: f8000000-fdffffff Prefetchable memory behind bridge: fea00000-feafffff 0000:00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3) Subsystem: Tyan Computer: Unknown device 2865 Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 5 Memory at febf9000 (32-bit, non-prefetchable) [size=4K] I/O ports at b400 [size=8] Capabilities: [44] Power Management version 2 0000:00:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00008000-00008fff Memory behind bridge: fe900000-fe9fffff Prefetchable memory behind bridge: 00000000fe800000-00000000fe800000 Capabilities: [40] Power Management version 2 Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [58] #08 [a800] Capabilities: [80] #10 [0141] 0000:00:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 00007000-00007fff Memory behind bridge: fe700000-fe7fffff Prefetchable memory behind bridge: 00000000fe600000-00000000fe600000 Capabilities: [40] Power Management version 2 Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [58] #08 [a800] Capabilities: [80] #10 [0141] 0000:00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 00006000-00006fff Memory behind bridge: fe500000-fe5fffff Prefetchable memory behind bridge: 00000000fe400000-00000000fe400000 Capabilities: [40] Power Management version 2 Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [58] #08 [a800] Capabilities: [80] #10 [0141] 0000:00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 00005000-00005fff Memory behind bridge: fe300000-fe3fffff Prefetchable memory behind bridge: 00000000fe200000-00000000fe200000 Capabilities: [40] Power Management version 2 Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [58] #08 [a800] Capabilities: [80] #10 [0141] 0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Flags: fast devsel Capabilities: [80] #08 [2101] 0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map Flags: fast devsel 0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller Flags: fast devsel 0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control Flags: fast devsel 0000:01:05.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 27) (prog-if 00 [VGA]) Subsystem: ATI Technologies Inc Rage XL Flags: bus master, stepping, medium devsel, latency 32, IRQ 12 Memory at f8000000 (32-bit, non-prefetchable) [size=16M] I/O ports at ac00 [size=256] Memory at fdfff000 (32-bit, non-prefetchable) [size=4K] Expansion ROM at fd000000 [disabled] [size=128K] Capabilities: [5c] Power Management version 2 0000:01:06.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80) (prog-if 10 [OHCI]) Subsystem: VIA Technologies, Inc. IEEE 1394 Host Controller Flags: bus master, stepping, medium devsel, latency 32, IRQ 10 Memory at fdffe000 (32-bit, non-prefetchable) [size=2K] I/O ports at a800 [size=128] Capabilities: [50] Power Management version 2 0000:05:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5721 Gigabit Ethernet PCI Express (rev 11) Subsystem: Broadcom Corporation NetXtreme BCM5721 Gigabit Ethernet PCI Express Flags: bus master, fast devsel, latency 0, IRQ 12 Memory at fe500000 (64-bit, non-prefetchable) [size=64K] Capabilities: [48] Power Management version 2 Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Capabilities: [d0] #10 [0001] -- Richard A. Smith

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[LinuxBIOS] something new ... buildrom
by Ronald G Minnich 07 Aug '06

07 Aug '06

we're all sick of having to do all the steps to build a flash image, right? Well, thanks to OLPC, there is a new tool: buildrom. This tool is designed to build a 1M flash image including linuxbios, kernel, and an initrd with busybox tools. Right now, it only works for OLPC, but that should not hold you back. To get it, just svn co svn://linuxbios.org/buildrom/buildrom-devel cd buildrom-devel/buildrom look at: packages/linuxbios/linuxbios.mk and see how you can set vendor, board, and config file in the top-level Config.mk. This is a work in progress. What I want to do over time is have a config directory such that you can pull down buildrom, set a few variables for mainboard etc., and in short time have a rom image automagically. take a look ron

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[LinuxBIOS] LinuxBIOS r2366 build changes
by LinuxBIOS information 07 Aug '06

07 Aug '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "rminnich" checked in revision 2366 to the LinuxBIOS source repository and caused the following changes: Change Log: initial work on sunw ultra40. It's wrong :-) Build Log: Compilation of artecgroup:dbe61 is still broken. Configuration of sunw:ultra40 has been fixed. Compilation of sunw:ultra40 has been fixed. If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] Uniflash.
by Uwe Hermann 07 Aug '06

07 Aug '06

Hi, I've stumbled over Uniflash recently (http://uniflash.org/) which is a flashing program similar to flashrom. I was lucky to find that I can use that to flash my W49F002U with that, so I can now finally flash LinuxBIOS (and other) images. The program is quite old, but supports lots of flash chips and motherboards (http://uniflash.org/hardware.htm). As it has recently been GPL'd I figure it might be interesting for LinuxBIOS in order to add support for more chips (even though it's written in Pascal and is compiled to a DOS *.exe file ;) I'll try to figure out what it does that flashrom does not, in order to be able to use flashrom; I'll post a patch for flashrom when I'm done. Cheers, Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org

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[LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
by Sam Brightman 07 Aug '06

07 Aug '06

Hello, I was wondering if someone could tell me whether LinuxBIOS will work with my setup (details below). At the moment I'm only hoping that flashrom works, as I have an updated BIOS from Asus but I'd also like to play with LinuxBIOS later. I've compiled and run flashrom -V from the "latest snapshot" link with nothing being detected. Details: Asus P2B - Intel i440BX (Pentium II 400MHz) Award BIOS Winbond W83977TF-AW (SuperIO/Flash Chip?? Nearest to BIOS) Below is the lcpci output. 0000:00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) 0000:00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) 0000:00:04.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) 0000:00:04.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) 0000:00:04.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01) 0000:00:04.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) 0000:00:0b.0 Ethernet controller: 3Com Corporation 3c900 10Mbps Combo [Boomerang] 0000:01:00.0 VGA compatible controller: ATI Technologies Inc Radeon RV100 QY [Radeon 7000/VE] Any help appreciated, -- sam brightman

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coreboot August 2006