coreboot July 2006

coreboot@coreboot.org

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89 discussions

Re: [LinuxBIOS] some more tyan/s2881 questions
by Lu, Yinghai 06 Jul '06

06 Jul '06

I have inited the hw sensors in LinuxBIOS for s2881. So you could use lmsensor to check the FAN speed. The config file is on Tyan web. For the Fan control, there should more some reg setting...to reduce the FAN speed winbond and adm1027... YH

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[LinuxBIOS] LinuxBIOS Support for motherboard from GIGABYTE
by rum vodka 05 Jul '06

05 Jul '06

Hi Everyone, Just stumbled upon www.linuxbios.org while "digg"ing for news. I would like to know if there is LinuxBIOS support for the following config: CPU : AMD Athlon 6400 MOTHERBOARD : GA-K8N51GMF-9 from GIGABYTE I/O Control : Winbond W83627 Chipset : NorthBridge : nVIDIA GeForce 6100 SouthBridge : nVIDIA nForce 430 output of lspci -vvv follows : ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 00:00.0 RAM memory: nVidia Corporation C51 Host Bridge (rev a2) … [View More]Subsystem: Giga-byte Technology Unknown device 5000 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn+ LSEn+ ExtCTL- 64b- Link Config 1: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 800MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping 00:00.1 RAM memory: nVidia Corporation C51 Memory Controller 0 (rev a2) Subsystem: Giga-byte Technology Unknown device 5000 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- 00:00.2 RAM memory: nVidia Corporation C51 Memory Controller 1 (rev a2) Subsystem: Giga-byte Technology Unknown device 5000 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:00.3 RAM memory: nVidia Corporation C51 Memory Controller 5 (rev a2) Subsystem: Giga-byte Technology Unknown device 5000 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:00.4 RAM memory: nVidia Corporation C51 Memory Controller 4 (rev a2) Subsystem: Giga-byte Technology Unknown device 5000 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00:00.5 RAM memory: nVidia Corporation C51 Host Bridge (rev a2) Subsystem: Giga-byte Technology Unknown device 5000 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] #00 [00fe] Capabilities: [fc] #00 [0000] 00:00.6 RAM memory: nVidia Corporation C51 Memory Controller 3 (rev a2) Subsystem: Giga-byte Technology Unknown device 5000 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:00.7 RAM memory: nVidia Corporation C51 Memory Controller 2 (rev a2) Subsystem: Giga-byte Technology Unknown device 5000 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:05.0 VGA compatible controller: nVidia Corporation C51 PCI Express Bridge (rev a2) (prog-if 00 [VGA]) Subsystem: Giga-byte Technology Unknown device d000 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 11 Region 0: Memory at f2000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at e0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at f3000000 (64-bit, non-prefetchable) [size=16M] [virtual] Expansion ROM at 30000000 [disabled] [size=128K] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 00:09.0 RAM memory: nVidia Corporation MCP51 Host Bridge (rev a2) Subsystem: Giga-byte Technology Unknown device 5001 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=9 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn+ LSEn+ ExtCTL- 64b- Link Config 0: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 800MHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping 00:0a.0 ISA bridge: nVidia Corporation MCP51 LPC Bridge (rev a2) Subsystem: Giga-byte Technology Unknown device 5001 Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00:0a.1 SMBus: nVidia Corporation MCP51 SMBus (rev a2) Subsystem: Giga-byte Technology Unknown device 0264 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 5 Region 4: I/O ports at 1c00 [size=64] Region 5: I/O ports at 1c80 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:0a.2 RAM memory: nVidia Corporation MCP51 Memory Controller 0 (rev a2) Subsystem: Giga-byte Technology Unknown device 0264 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:0b.0 USB Controller: nVidia Corporation MCP51 USB Controller (rev a2) (prog-if 10 [OHCI]) Subsystem: Giga-byte Technology Unknown device 5004 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 16 Region 0: Memory at f5108000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:0b.1 USB Controller: nVidia Corporation MCP51 USB Controller (rev a2) (prog-if 20 [EHCI]) Subsystem: Giga-byte Technology Unknown device 5004 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 17 Region 0: Memory at f5104000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:0d.0 IDE interface: nVidia Corporation MCP51 IDE (rev a1) (prog-if 8a [Master SecP PriP]) Subsystem: Giga-byte Technology Unknown device b000 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Region 4: I/O ports at f000 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:0e.0 IDE interface: nVidia Corporation MCP51 Serial ATA Controller (rev a1) (prog-if 85 [Master SecO PriO]) Subsystem: Giga-byte Technology Unknown device b002 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 16 Region 0: I/O ports at 09f0 [size=8] Region 1: I/O ports at 0bf0 [size=4] Region 2: I/O ports at 0970 [size=8] Region 3: I/O ports at 0b70 [size=4] Region 4: I/O ports at d800 [size=16] Region 5: Memory at f5107000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00:0f.0 IDE interface: nVidia Corporation MCP51 Serial ATA Controller (rev a1) (prog-if 85 [Master SecO PriO]) Subsystem: Giga-byte Technology Unknown device b002 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 17 Region 0: I/O ports at 09e0 [size=8] Region 1: I/O ports at 0be0 [size=4] Region 2: I/O ports at 0960 [size=8] Region 3: I/O ports at 0b60 [size=4] Region 4: I/O ports at c400 [size=16] Region 5: Memory at f5106000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping 00:10.0 PCI bridge: nVidia Corporation MCP51 PCI Bridge (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000a000-0000afff Memory behind bridge: f5000000-f50fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [b8] #0d [0000] Capabilities: [8c] HyperTransport: MSI Mapping 00:10.1 Audio device: nVidia Corporation MCP51 High Definition Audio (rev a2) Subsystem: Giga-byte Technology Unknown device a102 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (500ns min, 1250ns max) Interrupt: pin B routed to IRQ 19 Region 0: Memory at f5100000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [6c] HyperTransport: MSI Mapping 00:14.0 Bridge: nVidia Corporation MCP51 Ethernet Controller (rev a1) Subsystem: Giga-byte Technology Unknown device e000 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 18 Region 0: Memory at f5105000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b000 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 01:0e.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80) (prog-if 10 [OHCI]) Subsystem: Giga-byte Technology GA-7VT600-1394 Motherboard Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (8000ns max), Cache Line Size 08 Interrupt: pin A routed to IRQ 20 Region 0: Memory at f5000000 (32-bit, non-prefetchable) [size=2K] Region 1: I/O ports at a000 [size=128] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- regards Ram [View Less]

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[LinuxBIOS] Accessibility of LinuxBios
by Samuel Thibault 05 Jul '06

05 Jul '06

Hi, BIOSes is an area where accessibility is approximately non-existent. Asking vendors to support hardware speech syntheses and braille devices is quite dreamwork. I tried to convince accessibility people to release basic drivers with BSD licenses so that vendors might integrate them, but they just refused that, arguing that vendors will not make any effort to integrate them, and there will always be bugs (which are hard to debug/fix/integrate/... with vendor BIOSes). LinuxBios, however, can … [View More]

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[LinuxBIOS] OLPC Developers
by Bari Ari 05 Jul '06

05 Jul '06

We just got two developer OLPC mainboards in. Who else is here working on LinuxBIOS for OLPC besides Ollie and Ron? We are willing to help on testing/developing BIOS, but will probably do most of our work on mesh networking and codec's. -Bari

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[LinuxBIOS] Tyan S2892
by Arturo Mann 04 Jul '06

04 Jul '06

Hallo there, I used my Pentium4 to build a LinuxBIOS image based on the jun30th snapshot, using FILO to boot directly into GRUB. Now, my problem is, that the Tyan is currently bricked, and yes, even a replacement bios from BIOSMAN did not do the trick I do not want to send the Mainboard into warranty just yet. I have my linuxbios.rom, and a brand new, shiny SST49LF080A chip to put the image into. However, since the Tyan is bricked, I cannot program with it's own flashing mechanism using the … [View More]

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Re: [LinuxBIOS] lb on pd10000
by bios＠lists.actweb.info 03 Jul '06

03 Jul '06

Hi folks, Ok, ive had a play around with the code for LB to see if i can find where its failing and have found the following :- in file : src/northbridge/via/vt8623/raminit.c I added a couple of line to show were in the file its crashing :- /* setup cpu */ pci_write_config8(north,0x50,0xc8); pci_write_config8(north,0x51,0xde); pci_write_config8(north,0x52,0xcf); pci_write_config8(north,0x53,0x88); pci_write_config8(north,0x55,0x04); … [View More]print_debug("vt8623 init step 2\r\n"); /* DRAM MA Map Type Device 0 Offset 58 Determine memory addressing based on the module's memory technology and arrangement. See Table 4-9 of Intel's 82443GX datasheet for details. Bank 1/0 MA map type 58[7-5] Bank 1/0 command rate 58[4] Bank 3/2 MA map type 58[3-1] Bank 3/2 command rate 58[0] Read SPD byte 17, Number of banks on SDRAM device. */ print_debug("vt8623 init step 3\r\n"); c = 0; b = smbus_read_byte(0xa0,17); print_debug("vt8623 init step 4\r\n"); print_val("Detecting Memory\r\nNumber of Banks ",b); print_debug("vt8623 init step 5\r\n"); if( b != 2 ){ // not 16 Mb type /* Read SPD byte 3, Number of row addresses. */ At line 103 (aprox, as ive added some lines for debug as u can see) the print_debug("vt8623 init step 3\r\n"); statment works ok BUT I NEVER GET THE 'step 4' debug statments outputting so i can assume (and PLEASE correct me if im wrong, or if u recon the lines ive added are the cause) the the bad line is : b = smbus_read_byte(0xa0,17); Ok, after finding this line, i hunted for the source for smbus_read_byte which i belive is in : src/southbridge/via/vt8231/vt8231_early_smbus.c (am i corect in thinking this??????) Im not sure because i edited the file starting at line 151 and added in my debug lines as follows :- static int smbus_read_byte(unsigned device, unsigned address) { print_debug("smbus_read_byte start\r\n"); unsigned char global_control_register; unsigned char global_status_register; unsigned char byte; print_debug("smbus_read_byte step 2\r\n"); if (smbus_wait_until_ready() < 0) { outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTA$ if (smbus_wait_until_ready() < 0) { return -2; } } print_debug("smbus_read_byte step 3\r\n"); /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); print_debug("smbus_read_byte step 4\r\n"); /* set the device I'm talking too */ outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); print_debug("smbus_read_byte step 5\r\n"); /* set the command/address... */ outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); print_debug("smbus_read_byte step 6\r\n"); /* set up for a byte data read */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BAS$ print_debug("smbus_read_byte step 7\r\n"); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); print_debug("smbus_read_byte step 8\r\n"); /* clear the data byte... */ outb(0, SMBUS_IO_BASE + SMBHSTDAT0); print_debug("smbus_read_byte step 9\r\n"); /* start a byte read, with interrupts disabled */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL$ print_debug("smbus_read_byte step 10\r\n"); /* poll for it to start */ if (smbus_wait_until_active() < 0) { return -4; } print_debug("smbus_read_byte step 11\r\n"); /* poll for transaction completion */ if (smbus_wait_until_done() < 0) { return -3; } print_debug("smbus_read_byte step 12\r\n"); /* Ignore the Host Busy & Command Complete ? */ global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) |$ print_debug("smbus_read_byte step 13\r\n"); /* read results of transaction */ byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); print_debug("smbus_read_byte step 14\r\n"); if (global_status_register != 0) { return -1; } print_debug("smbus_read_byte step 15\r\n"); return byte; } Unfortunatly NOTHING EXTRA was displayed via the serial port :( So, first, is this the write file that im editing to find were the problem is occuring? second, if so, why didnt i get at leaste the first print_debug before anything else was run in the routine? if its not the correct file, which file should i edit? Is this all necisarry, or has someone else already done all this, and got a solution :) One last thing, am i correct in thinking that simply going into src/targets/via/epia-m/epia-m/ and running 'make clean', 'make' is enough to recompile all the routines (including the southbridge stuff)? Matt [View Less]

3 6

[LinuxBIOS] LB on PD10000
by bios＠lists.actweb.info 03 Jul '06

03 Jul '06

Ok, found a serial cable :) Booting up the EPIA-PD1000 I get the following via serial terminal :- 0 LinuxBIOS-1.1.8.0Fallback Sat Jul 1 01:02:23 BST 2006 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting and thats as far as it gets :( Is there a setting to get a more verbose output? or can anyone give me any pointers just from this? (LOL) As i understand it the vt8623 is the video chip, does this meen that my via video bios grab didnt work properly? Is … [View More]

2 1

[LinuxBIOS] cant detect bios with flash software
by bios＠lists.actweb.info 03 Jul '06

03 Jul '06

Hi, I have just got my RD1, and installed it into my EPIA-PD10000 m/board (same chipset as the EPIA-M), all works fine :) I ran the flashrom util fom the linuxbios source code, (downloaded via svn) when i run the flashrom util i get the following :- with bios savour switched in, but nothing written :- :~/bios/LinuxBIOSv2/util/flashrom# ./flashrom Calibrating delay loop... ok No LinuxBIOS table found. Enabling flash write on VT8235...OK W49F002U found at physical address: 0xfffc0000 Flash … [View More]

5 18

[LinuxBIOS] Kernel will not boot
by Philipp Degler 03 Jul '06

03 Jul '06

Hi, I tried various payloads to boot the system. Filo could not find my hda saying floating bus. Etherboot loads OK and gets a kernel elf image via tftp but kernel is not loading. Do you have an idea what could be the problem? Maybe some PCI-Devices not initialized correctly? VGA-Support is turned off, no pci cards in the slots, 2GB RAM, Using 2.6 static kernel with vga and fb options turned completely off. LinuxBIOS was compiled with gcc (GCC) 3.3.3 (SuSE Linux) and binutils-2.15.90.0.1.… [View More]1-30 (binutils-32bit-9.1-200404070910) I appended the trace of LinuxBIOS with loglevel 9. thx phil --------- LinuxBIOS-1.1.8_Fallback Mon Mar 27 15:51:01 CEST 2006 starting... i386 console_init report_bist_failure setup_default_resource_map setting up resource map.... 0000c144 <-00000000 0000c14c <-00000001 0000c154 <-00000002 0000c15c <-00000003 0000c164 <-00000004 0000c16c <-00000005 0000c174 <-00000006 0000c17c <-00000007 0000c140 <-00000000 0000c148 <-00000000 0000c150 <-00000000 0000c158 <-00000000 0000c160 <-00000000 0000c168 <-00000000 0000c170 <-00000000 0000c178 <-00000000 0000c184 <-00000000 0000c18c <-00000000 0000c194 <-00000000 0000c19c <-00000000 0000c1a4 <-00000000 0000c1ac <-00000000 0000c1b4 <-00000000 0000c180 <-00000000 0000c188 <-00000000 0000c190 <-00000000 0000c198 <-00000000 0000c1a0 <-00000000 0000c1a8 <-00000000 0000c1b0 <-00000000 0000c1cc <-00000000 0000c1d4 <-00000000 0000c1dc <-00000000 0000c1c8 <-00000000 0000c1d0 <-00000000 0000c1d8 <-00000000 0000c1e4 <-00000000 0000c1e8 <-00000000 0000c1ec <-00000000 done. setup_coherent_ht_domain Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done needs_reset ht reset - enable_smbus SMBus controller enabled memreset_setup sdram_initialize Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 Enabling dual channel memory 200Mhz Interleaved RAM: 0x00100000 KB Ram2.01 Enabling dual channel memory 200Mhz Interleaved RAM: 0x00200000 KB Ram3 ECC enabled ECC enabled Initializing memory: done Initializing memory: done Clearing initial memory region: done Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. test LinuxBIOS-1.1.8_Fallback Mon Mar 27 15:51:01 CEST 2006 booting... Enumerating buses... scan_static_bus for Root Device PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: devfn 0xc4, bad id 0xffffffff PCI: devfn 0xc5, bad id 0xffffffff PCI: devfn 0xc6, bad id 0xffffffff PCI: devfn 0xc7, bad id 0xffffffff PCI: 00:19.0 [1022/1100] bus ops PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled PCI: devfn 0xcc, bad id 0xffffffff PCI: devfn 0xcd, bad id 0xffffffff PCI: devfn 0xce, bad id 0xffffffff PCI: devfn 0xcf, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 00040000 malloc 0x00040000 PCI: 01:00.0 [1022/7450] bus ops PCI: 01:00.0 [1022/7450] enabled Capability: 0x08 @ 0xa0 Capability: 0x08 @ 0xb8 flags: 0x8000 Capability: 0x08 @ 0xa0 Capability: 0x08 @ 0xb8 Capability: 0x08 @ 0xc0 flags: 0x0040 PCI: 01:01.0 count: 0002 static_count: 0001 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 malloc Enter, size 668, free_mem_ptr 0004029c malloc 0x0004029c PCI: 01:00.0 [1022/7460] bus ops PCI: 01:00.0 [1022/7460] enabled Capability: 0x08 @ 0xc0 flags: 0x0080 PCI: 01:03.0 count: 0004 static_count: 0001 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 1 PCI: devfn 0x0, bad id 0xffffffff PCI: 01:01.0 [1022/7450] enabled malloc Enter, size 668, free_mem_ptr 00040538 malloc 0x00040538 PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: devfn 0xa, bad id 0xffffffff PCI: devfn 0xb, bad id 0xffffffff PCI: devfn 0xc, bad id 0xffffffff PCI: devfn 0xd, bad id 0xffffffff PCI: devfn 0xe, bad id 0xffffffff PCI: devfn 0xf, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 000407d4 malloc 0x000407d4 PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled malloc Enter, size 668, free_mem_ptr 00040a70 malloc 0x00040a70 PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: devfn 0x12, bad id 0xffffffff PCI: devfn 0x13, bad id 0xffffffff PCI: devfn 0x14, bad id 0xffffffff PCI: devfn 0x15, bad id 0xffffffff PCI: devfn 0x16, bad id 0xffffffff PCI: devfn 0x17, bad id 0xffffffff PCI: 01:03.0 [1022/7460] enabled malloc Enter, size 668, free_mem_ptr 00040d0c malloc 0x00040d0c PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled malloc Enter, size 668, free_mem_ptr 00040fa8 malloc 0x00040fa8 PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled malloc Enter, size 668, free_mem_ptr 00041244 malloc 0x00041244 PCI: 01:04.2 [1022/746a] bus ops PCI: 01:04.2 [1022/746a] enabled malloc Enter, size 668, free_mem_ptr 000414e0 malloc 0x000414e0 PCI: 01:04.3 [1022/746b] bus ops PCI: 01:04.3 [1022/746b] enabled PCI: devfn 0x24, bad id 0x0 malloc Enter, size 668, free_mem_ptr 0004177c malloc 0x0004177c PCI: 01:04.5 [1022/746d] ops PCI: 01:04.5 [1022/746d] enabled malloc Enter, size 668, free_mem_ptr 00041a18 malloc 0x00041a18 PCI: 01:04.6 [1022/746e] ops PCI: 01:04.6 [1022/746e] enabled PCI: devfn 0x27, bad id 0x0 PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff do_pci_scan_bridge for PCI: 01:01.0 PCI: pci_scan_bus for bus 2 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 00041cb4 malloc 0x00041cb4 PCI: 02:03.0 [8086/1076] enabled malloc Enter, size 668, free_mem_ptr 00041f50 malloc 0x00041f50 PCI: 02:04.0 [8086/1076] enabled malloc Enter, size 668, free_mem_ptr 000421ec malloc 0x000421ec PCI: 02:05.0 [1095/3114] enabled PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=02 Capability: 0x07 @ 0xa0 PCI: 02: Conventional PCI do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 01:02.0 PCI: pci_scan_bus for bus 3 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=03 Capability: 0x07 @ 0xa0 PCI: 03: 133MHz PCI-X do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 01:03.0 PCI: pci_scan_bus for bus 4 malloc Enter, size 668, free_mem_ptr 00042488 malloc 0x00042488 PCI: 04:00.0 [1022/7464] bus ops PCI: 04:00.0 [1022/7464] enabled malloc Enter, size 668, free_mem_ptr 00042724 malloc 0x00042724 PCI: 04:00.1 [1022/7464] bus ops PCI: 04:00.1 [1022/7464] enabled malloc Enter, size 668, free_mem_ptr 000429c0 malloc 0x000429c0 PCI: 04:00.2 [1022/7463] ops USB2 disabled. PCI: 04:00.2 [1022/7463] disabled PCI: devfn 0x3, bad id 0xffffffff PCI: devfn 0x4, bad id 0xffffffff PCI: devfn 0x5, bad id 0xffffffff PCI: devfn 0x6, bad id 0xffffffff PCI: devfn 0x7, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 00042c5c malloc 0x00042c5c PCI: 04:01.0 [1022/7462] ops PCI: 04:01.0 [1022/7462] enabled PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 00042ef8 malloc 0x00042ef8 PCI: 04:06.0 [1002/4752] enabled PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff scan_static_bus for PCI: 04:00.0 scan_static_bus for PCI: 04:00.0 done scan_static_bus for PCI: 04:00.1 scan_static_bus for PCI: 04:00.1 done PCI: pci_scan_bus returning with max=04 do_pci_scan_bridge returns max 4 scan_static_bus for PCI: 01:04.0 scan_static_bus for PCI: 01:04.0 done scan_static_bus for PCI: 01:04.2 scan_static_bus for PCI: 01:04.2 done scan_static_bus for PCI: 01:04.3 scan_static_bus for PCI: 01:04.3 done PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 PCI_DOMAIN: 0000 passpw: enabled PCI_DOMAIN: 0000 passpw: enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI: 00:19.3 siblings=0 CPU: APIC: 01 enabled scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.0 missing read_resources PCI: 00:00.1 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:00.0 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:01.2 missing read_resources PCI: 00:01.3 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:18.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.0 missing read_resources PCI: 00:00.1 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:00.0 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:01.2 missing read_resources PCI: 00:01.3 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:18.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.0 missing read_resources PCI: 00:00.1 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:00.0 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:01.2 missing read_resources PCI: 00:01.3 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:18.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:18.0 read_resources bus 1 link: 2 PCI: 01:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 01:01.0 read_resources bus 2 link: 0 PCI: 01:01.0 read_resources bus 2 link: 0 done PCI: 02:03.0 18 * [0x00000000 - 0x0000003f] io PCI: 02:04.0 18 * [0x00000040 - 0x0000007f] io PCI: 02:05.0 20 * [0x00000080 - 0x0000008f] io PCI: 02:05.0 10 * [0x00000090 - 0x00000097] io PCI: 02:05.0 18 * [0x000000a0 - 0x000000a7] io PCI: 02:05.0 14 * [0x000000b0 - 0x000000b3] io PCI: 02:05.0 1c * [0x000000c0 - 0x000000c3] io PCI: 01:01.0 compute_allocate_io: base: 000000c4 size: 00001000 align: 12 gran: 12 done PCI: 01:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 01:01.0 read_resources bus 2 link: 0 PCI: 01:01.0 read_resources bus 2 link: 0 done PCI: 01:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 01:01.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 PCI: 01:01.0 read_resources bus 2 link: 0 PCI: 01:01.0 read_resources bus 2 link: 0 done PCI: 01:01.0 compute_allocate_prefmem: base: fffffffffff00000 size: 00000000 align: 20 gran: 20 done PCI: 01:01.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 2 prefmem PCI: 01:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 01:01.0 read_resources bus 2 link: 0 PCI: 01:01.0 read_resources bus 2 link: 0 done PCI: 02:05.0 30 * [0x00000000 - 0x0007ffff] mem PCI: 02:03.0 10 * [0x00080000 - 0x0009ffff] mem PCI: 02:04.0 10 * [0x000a0000 - 0x000bffff] mem PCI: 02:04.0 14 * [0x000c0000 - 0x000dffff] mem PCI: 02:04.0 30 * [0x000e0000 - 0x000fffff] mem PCI: 02:05.0 24 * [0x00100000 - 0x001003ff] mem PCI: 01:01.0 compute_allocate_mem: base: 00100400 size: 00200000 align: 20 gran: 20 done PCI: 01:03.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 01:03.0 read_resources bus 4 link: 0 PCI: 01:03.0 read_resources bus 4 link: 0 done PCI: 04:06.0 14 * [0x00000000 - 0x000000ff] io PCI: 01:03.0 compute_allocate_io: base: 00000100 size: 00001000 align: 12 gran: 12 done PCI: 01:03.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 01:03.0 read_resources bus 4 link: 0 PCI: 01:03.0 read_resources bus 4 link: 0 done PCI: 01:03.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 01:03.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 01:03.0 read_resources bus 4 link: 0 PCI: 01:03.0 read_resources bus 4 link: 0 done PCI: 01:03.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 01:03.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 4 prefmem PCI: 01:03.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 01:03.0 read_resources bus 4 link: 0 PCI: 01:03.0 read_resources bus 4 link: 0 done PCI: 04:06.0 10 * [0x00000000 - 0x00ffffff] mem PCI: 04:06.0 30 * [0x01000000 - 0x0101ffff] mem PCI: 04:01.0 30 * [0x01020000 - 0x0102ffff] mem PCI: 04:00.0 10 * [0x01030000 - 0x01030fff] mem PCI: 04:00.1 10 * [0x01031000 - 0x01031fff] mem PCI: 04:01.0 10 * [0x01032000 - 0x01032fff] mem PCI: 04:06.0 18 * [0x01033000 - 0x01033fff] mem PCI: 01:03.0 compute_allocate_mem: base: 01034000 size: 01100000 align: 24 gran: 20 done PCI: 01:04.0 read_resources bus 0 link: 0 PCI: 01:04.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 1 link: 2 done PCI: 01:01.0 1c * [0x00000000 - 0x00000fff] io PCI: 01:03.0 1c * [0x00001000 - 0x00001fff] io PCI: 01:04.3 58 * [0x00002000 - 0x000020ff] io PCI: 01:04.5 10 * [0x00002400 - 0x000024ff] io PCI: 01:04.6 10 * [0x00002800 - 0x000028ff] io PCI: 01:04.6 14 * [0x00002c00 - 0x00002c7f] io PCI: 01:04.5 14 * [0x00002c80 - 0x00002cbf] io PCI: 01:04.2 10 * [0x00002cc0 - 0x00002cdf] io PCI: 01:04.1 20 * [0x00002ce0 - 0x00002cef] io PCI: 00:18.0 compute_allocate_io: base: 00002cf0 size: 00003000 align: 12 gran: 12 done PCI: 00:18.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 1 link: 2 PCI: 00:18.0 read_resources bus 1 link: 2 done PCI: 00:18.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:18.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 1 link: 2 PCI: 00:18.0 read_resources bus 1 link: 2 done PCI: 01:03.0 20 * [0x00000000 - 0x010fffff] mem PCI: 01:01.0 20 * [0x01100000 - 0x012fffff] mem PCI: 01:01.1 10 * [0x01300000 - 0x01300fff] mem PCI: 01:02.1 10 * [0x01301000 - 0x01301fff] mem PCI: 00:18.0 compute_allocate_mem: base: 01302000 size: 01400000 align: 24 gran: 20 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:18.0 1d2 * [0x00001000 - 0x00003fff] io PCI: 00:18.0 1d8 * [0x00004000 - 0x00003fff] io Root Device compute_allocate_io: base: 00004000 size: 00003c00 align: 12 gran: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:18.3 94 * [0x00000000 - 0x03ffffff] mem PCI: 00:18.0 1a2 * [0x04000000 - 0x053fffff] mem PCI: 00:18.0 1b8 * [0x05400000 - 0x053fffff] prefmem PCI: 00:18.0 1b0 * [0x05400000 - 0x053fffff] mem PCI: 00:18.0 1aa * [0x05400000 - 0x053fffff] prefmem Root Device compute_allocate_mem: base: 05400000 size: 05400000 align: 26 gran: 0 done Done reading resources. Setting resources... Root Device compute_allocate_io: base: 00001000 size: 00003c00 align: 12 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:18.0 1d2 * [0x00001000 - 0x00003fff] io PCI: 00:18.0 1d8 * [0x00004000 - 0x00003fff] io Root Device compute_allocate_io: base: 00004000 size: 00003000 align: 12 gran: 0 done Root Device compute_allocate_mem: base: f8000000 size: 05400000 align: 26 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem PCI: 00:18.0 1a2 * [0xfc000000 - 0xfd3fffff] mem PCI: 00:18.0 1b8 * [0xfd400000 - 0xfd3fffff] prefmem PCI: 00:18.0 1b0 * [0xfd400000 - 0xfd3fffff] mem PCI: 00:18.0 1aa * [0xfd400000 - 0xfd3fffff] prefmem Root Device compute_allocate_mem: base: fd400000 size: 05400000 align: 26 gran: 0 done Root Device assign_resources, bus 0 link: 0 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 compute_allocate_io: base: 00004000 size: 00000000 align: 12 gran: 12 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.0 missing read_resources PCI: 00:00.1 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:00.0 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:01.2 missing read_resources PCI: 00:01.3 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 compute_allocate_io: base: 00004000 size: 00000000 align: 12 gran: 12 done PCI: 00:18.0 1d8 <- [0x0000004000 - 0x0000003fff] io <node 0 link 0> PCI: 00:18.0 compute_allocate_prefmem: base: fd400000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.0 missing read_resources PCI: 00:00.1 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:00.0 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:01.2 missing read_resources PCI: 00:01.3 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 compute_allocate_prefmem: base: fd400000 size: 00000000 align: 20 gran: 20 done PCI: 00:18.0 1b8 <- [0x00fd400000 - 0x00fd3fffff] prefmem <node 0 link 0> PCI: 00:18.0 compute_allocate_mem: base: fd400000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.0 missing read_resources PCI: 00:00.1 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:00.0 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:01.2 missing read_resources PCI: 00:01.3 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 compute_allocate_mem: base: fd400000 size: 00000000 align: 20 gran: 20 done PCI: 00:18.0 1b0 <- [0x00fd400000 - 0x00fd3fffff] mem <node 0 link 0> PCI: 00:18.0 compute_allocate_io: base: 00001000 size: 00003000 align: 12 gran: 12 PCI: 00:18.0 read_resources bus 1 link: 2 PCI: 00:18.0 read_resources bus 1 link: 2 done PCI: 01:01.0 1c * [0x00001000 - 0x00001fff] io PCI: 01:03.0 1c * [0x00002000 - 0x00002fff] io PCI: 01:04.3 58 * [0x00003000 - 0x000030ff] io PCI: 01:04.5 10 * [0x00003400 - 0x000034ff] io PCI: 01:04.6 10 * [0x00003800 - 0x000038ff] io PCI: 01:04.6 14 * [0x00003c00 - 0x00003c7f] io PCI: 01:04.5 14 * [0x00003c80 - 0x00003cbf] io PCI: 01:04.2 10 * [0x00003cc0 - 0x00003cdf] io PCI: 01:04.1 20 * [0x00003ce0 - 0x00003cef] io PCI: 00:18.0 compute_allocate_io: base: 00003cf0 size: 00003000 align: 12 gran: 12 done PCI: 00:18.0 1d2 <- [0x0000001000 - 0x0000003fff] io <node 0 link 2> PCI: 00:18.0 compute_allocate_prefmem: base: fd400000 size: 00000000 align: 20 gran: 20 PCI: 00:18.0 read_resources bus 1 link: 2 PCI: 00:18.0 read_resources bus 1 link: 2 done PCI: 00:18.0 compute_allocate_prefmem: base: fd400000 size: 00000000 align: 20 gran: 20 done PCI: 00:18.0 1aa <- [0x00fd400000 - 0x00fd3fffff] prefmem <node 0 link 2> PCI: 00:18.0 compute_allocate_mem: base: fc000000 size: 01400000 align: 24 gran: 20 PCI: 00:18.0 read_resources bus 1 link: 2 PCI: 00:18.0 read_resources bus 1 link: 2 done PCI: 01:03.0 20 * [0xfc000000 - 0xfd0fffff] mem PCI: 01:01.0 20 * [0xfd100000 - 0xfd2fffff] mem PCI: 01:01.1 10 * [0xfd300000 - 0xfd300fff] mem PCI: 01:02.1 10 * [0xfd301000 - 0xfd301fff] mem PCI: 00:18.0 compute_allocate_mem: base: fd302000 size: 01400000 align: 24 gran: 20 done PCI: 00:18.0 1a2 <- [0x00fc000000 - 0x00fd3fffff] mem <node 0 link 2> PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 1 link: 2 PCI: 01:01.0 compute_allocate_io: base: 00001000 size: 00001000 align: 12 gran: 12 PCI: 01:01.0 read_resources bus 2 link: 0 PCI: 01:01.0 read_resources bus 2 link: 0 done PCI: 02:03.0 18 * [0x00001000 - 0x0000103f] io PCI: 02:04.0 18 * [0x00001040 - 0x0000107f] io PCI: 02:05.0 20 * [0x00001080 - 0x0000108f] io PCI: 02:05.0 10 * [0x00001090 - 0x00001097] io PCI: 02:05.0 18 * [0x000010a0 - 0x000010a7] io PCI: 02:05.0 14 * [0x000010b0 - 0x000010b3] io PCI: 02:05.0 1c * [0x000010c0 - 0x000010c3] io PCI: 01:01.0 compute_allocate_io: base: 000010c4 size: 00001000 align: 12 gran: 12 done PCI: 01:01.0 1c <- [0x0000001000 - 0x0000001fff] bus 2 io PCI: 01:01.0 compute_allocate_mem: base: fd100000 size: 00200000 align: 20 gran: 20 PCI: 01:01.0 read_resources bus 2 link: 0 PCI: 01:01.0 read_resources bus 2 link: 0 done PCI: 02:05.0 30 * [0xfd100000 - 0xfd17ffff] mem PCI: 02:03.0 10 * [0xfd180000 - 0xfd19ffff] mem PCI: 02:04.0 10 * [0xfd1a0000 - 0xfd1bffff] mem PCI: 02:04.0 14 * [0xfd1c0000 - 0xfd1dffff] mem PCI: 02:04.0 30 * [0xfd1e0000 - 0xfd1fffff] mem PCI: 02:05.0 24 * [0xfd200000 - 0xfd2003ff] mem PCI: 01:01.0 compute_allocate_mem: base: fd200400 size: 00200000 align: 20 gran: 20 done PCI: 01:01.0 20 <- [0x00fd100000 - 0x00fd2fffff] bus 2 mem PCI: 01:01.0 assign_resources, bus 2 link: 0 PCI: 02:03.0 10 <- [0x00fd180000 - 0x00fd19ffff] mem PCI: 02:03.0 18 <- [0x0000001000 - 0x000000103f] io PCI: 02:04.0 10 <- [0x00fd1a0000 - 0x00fd1bffff] mem PCI: 02:04.0 14 <- [0x00fd1c0000 - 0x00fd1dffff] mem PCI: 02:04.0 18 <- [0x0000001040 - 0x000000107f] io PCI: 02:04.0 30 <- [0x00fd1e0000 - 0x00fd1fffff] romem PCI: 02:05.0 10 <- [0x0000001090 - 0x0000001097] io PCI: 02:05.0 14 <- [0x00000010b0 - 0x00000010b3] io PCI: 02:05.0 18 <- [0x00000010a0 - 0x00000010a7] io PCI: 02:05.0 1c <- [0x00000010c0 - 0x00000010c3] io PCI: 02:05.0 20 <- [0x0000001080 - 0x000000108f] io PCI: 02:05.0 24 <- [0x00fd200000 - 0x00fd2003ff] mem PCI: 02:05.0 30 <- [0x00fd100000 - 0x00fd17ffff] romem PCI: 01:01.0 assign_resources, bus 2 link: 0 PCI: 01:01.1 10 <- [0x00fd300000 - 0x00fd300fff] mem64 PCI: 01:02.1 10 <- [0x00fd301000 - 0x00fd301fff] mem64 PCI: 01:03.0 compute_allocate_io: base: 00002000 size: 00001000 align: 12 gran: 12 PCI: 01:03.0 read_resources bus 4 link: 0 PCI: 01:03.0 read_resources bus 4 link: 0 done PCI: 04:06.0 14 * [0x00002000 - 0x000020ff] io PCI: 01:03.0 compute_allocate_io: base: 00002100 size: 00001000 align: 12 gran: 12 done PCI: 01:03.0 1c <- [0x0000002000 - 0x0000002fff] bus 4 io PCI: 01:03.0 compute_allocate_mem: base: fc000000 size: 01100000 align: 24 gran: 20 PCI: 01:03.0 read_resources bus 4 link: 0 PCI: 01:03.0 read_resources bus 4 link: 0 done PCI: 04:06.0 10 * [0xfc000000 - 0xfcffffff] mem PCI: 04:06.0 30 * [0xfd000000 - 0xfd01ffff] mem PCI: 04:01.0 30 * [0xfd020000 - 0xfd02ffff] mem PCI: 04:00.0 10 * [0xfd030000 - 0xfd030fff] mem PCI: 04:00.1 10 * [0xfd031000 - 0xfd031fff] mem PCI: 04:01.0 10 * [0xfd032000 - 0xfd032fff] mem PCI: 04:06.0 18 * [0xfd033000 - 0xfd033fff] mem PCI: 01:03.0 compute_allocate_mem: base: fd034000 size: 01100000 align: 24 gran: 20 done PCI: 01:03.0 20 <- [0x00fc000000 - 0x00fd0fffff] bus 4 mem PCI: 01:03.0 assign_resources, bus 4 link: 0 PCI: 04:00.0 10 <- [0x00fd030000 - 0x00fd030fff] mem PCI: 04:00.1 10 <- [0x00fd031000 - 0x00fd031fff] mem PCI: 04:01.0 10 <- [0x00fd032000 - 0x00fd032fff] mem PCI: 04:01.0 30 <- [0x00fd020000 - 0x00fd02ffff] romem PCI: 04:06.0 10 <- [0x00fc000000 - 0x00fcffffff] mem PCI: 04:06.0 14 <- [0x0000002000 - 0x00000020ff] io PCI: 04:06.0 18 <- [0x00fd033000 - 0x00fd033fff] mem PCI: 04:06.0 30 <- [0x00fd000000 - 0x00fd01ffff] romem PCI: 01:03.0 assign_resources, bus 4 link: 0 PCI: 01:04.1 20 <- [0x0000003ce0 - 0x0000003cef] io PCI: 01:04.2 10 <- [0x0000003cc0 - 0x0000003cdf] io PCI: 01:04.3 58 <- [0x0000003000 - 0x00000030ff] io PCI: 01:04.5 10 <- [0x0000003400 - 0x00000034ff] io PCI: 01:04.5 14 <- [0x0000003c80 - 0x0000003cbf] io PCI: 01:04.6 10 <- [0x0000003800 - 0x00000038ff] io PCI: 01:04.6 14 <- [0x0000003c00 - 0x0000003c7f] io PCI: 00:18.0 assign_resources, bus 1 link: 2 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] mem <gart> PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] mem <gart> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resourcess... PCI: 00:18.0 cmd <- 140 PCI: 00:00.0 missing enable_resources PCI: 00:00.1 missing enable_resources PCI: 00:01.0 missing enable_resources PCI: 00:01.1 missing enable_resources PCI: 00:00.0 missing enable_resources PCI: 00:01.0 missing enable_resources PCI: 00:01.1 missing enable_resources PCI: 00:01.2 missing enable_resources PCI: 00:01.3 missing enable_resources PCI: 01:01.0 bridge ctrl <- 0003 PCI: 01:01.0 cmd <- 147 PCI: 02:03.0 cmd <- 143 PCI: 02:04.0 cmd <- 143 PCI: 02:05.0 cmd <- 143 PCI: 01:01.1 cmd <- 146 PCI: 01:02.1 cmd <- 146 PCI: 01:03.0 bridge ctrl <- 0003 PCI: 01:03.0 cmd <- 147 PCI: 04:00.0 cmd <- 142 PCI: 04:00.1 cmd <- 142 PCI: 04:01.0 cmd <- 142 PCI: 04:06.0 cmd <- 1c3 PCI: 01:04.0 cmd <- 14f PCI: 01:04.1 cmd <- 141 PCI: 01:04.2 cmd <- 141 PCI: 01:04.3 cmd <- 141 PCI: 01:04.5 cmd <- 141 PCI: 01:04.6 cmd <- 141 PCI: 00:18.1 subsystem <- 161f/3017 PCI: 00:18.1 cmd <- 140 PCI: 00:18.2 subsystem <- 161f/3017 PCI: 00:18.2 cmd <- 140 PCI: 00:18.3 cmd <- 140 PCI: 00:19.0 cmd <- 140 PCI: 00:19.1 subsystem <- 161f/3017 PCI: 00:19.1 cmd <- 140 PCI: 00:19.2 subsystem <- 161f/3017 PCI: 00:19.2 cmd <- 140 PCI: 00:19.3 cmd <- 140 done. Initializing devices... Root Device init PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.0 init PCI: 00:19.1 init PCI: 00:19.2 init PCI: 00:19.3 init NB: Function 3 Misc Control.. done. APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor AMD device f5a Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent processor rev id = 0x004a, patch id = 0x00000000 microcode: patch id that want to apply= 0x00000047 microcode: updated to patch id = 0x00000047 success Setting up local apic... apic_id: 0 done. Clearing memory 1024K - 1048576K: --------------- done CPU #0 Initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +start_eip=0x00010000 #startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device f5a Sending STARTUP #2 to 1. After apic_write. Enabling cache at rSteutpt ipnogi nfti x1e.d fMWTaRiRtsi(n0g- 8f8o)r tsyepned: tUoC inish... fAfter SSteatrttiunpg. RiWxaeidt iMnTgR Rfso(r0 -11 6C)P UTSy pteo: sWtBo,p dMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff ADDRESS_MASK_HIGH=0xff call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent processor rev id = 0x004a, patch id = 0x00000000 microcode: patch id that want to apply= 0x00000047 microcode: updated to patch id = 0x00000047 success Setting up local apic... apic_id: 1 done. Clearing memory 1048576K - 2097152K: ---------------- done CPU #1 Initialized All AP CPUs stopped PCI: 01:01.0 init PCI: 01:03.0 init PCI: 01:04.0 init for IRQ, reg 0x00000000 value 0x00000700 0x00000000 for IRQ, reg 0x00000001 value 0x00010000 0x00000000 for IRQ, reg 0x00000002 value 0x00010000 0x00000000 for IRQ, reg 0x00000003 value 0x00010000 0x00000000 for IRQ, reg 0x00000004 value 0x00010000 0x00000000 for IRQ, reg 0x00000005 value 0x00010000 0x00000000 for IRQ, reg 0x00000006 value 0x00010000 0x00000000 for IRQ, reg 0x00000007 value 0x00010000 0x00000000 for IRQ, reg 0x00000008 value 0x00010000 0x00000000 for IRQ, reg 0x00000009 value 0x00010000 0x00000000 for IRQ, reg 0x0000000a value 0x00010000 0x00000000 for IRQ, reg 0x0000000b value 0x00010000 0x00000000 for IRQ, reg 0x0000000c value 0x00010000 0x00000000 for IRQ, reg 0x0000000d value 0x00010000 0x00000000 for IRQ, reg 0x0000000e value 0x00010000 0x00000000 for IRQ, reg 0x0000000f value 0x00010000 0x00000000 for IRQ, reg 0x00000010 value 0x00010000 0x00000000 for IRQ, reg 0x00000011 value 0x00010000 0x00000000 for IRQ, reg 0x00000012 value 0x00010000 0x00000000 for IRQ, reg 0x00000013 value 0x00010000 0x00000000 for IRQ, reg 0x00000014 value 0x00010000 0x00000000 for IRQ, reg 0x00000015 value 0x00010000 0x00000000 for IRQ, reg 0x00000016 value 0x00010000 0x00000000 for IRQ, reg 0x00000017 value 0x00010000 0x00000000 RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum enabling HPET @0xfed00000 PCI: 01:04.1 init PCI: 01:04.3 init set power on after power fail PCI: 02:03.0 init PCI: 02:04.0 init PCI: 02:05.0 init PCI: 04:01.0 init Reseting PHY... Done PCI: 04:06.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Wrote the mp table end at: 00000020 - 0000021c Moving GDT to 0x500...ok Wrote linuxbios table at: 00000530 - 00000df8 checksum 5f51 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 33:stream_init() - rom_stream: 0xfffd0000 - 0xfffdee87 Found ELF candiate at offset 0 header_offset is 0 Try to load at offset 0x0 n_type: 00000001 n_name(8): ELFBoot n_desc(10): Etherboot n_type: 00000002 n_name(8): ELFBoot n_desc(6): 5.2.6 Loading Etherboot version: 5.2.6 Dropping non PT_LOAD segment malloc Enter, size 32, free_mem_ptr 00043194 malloc 0x00043194 New segment addr 0x20000 size 0x18024 offset 0xb0 filesize 0x891c (cleaned up) New segment addr 0x20000 size 0x18024 offset 0xb0 filesize 0x891c lb: [0x0000000000004000, 0x000000000004e000) segment: [0x0000000000020000, 0x000000000002891c, 0x0000000000038024) bounce: [0x000000007ff88000, 0x000000007ff9091c, 0x000000007ffa0024) Loading Segment: addr: 0x000000007ff88000 memsz: 0x0000000000018024 filesz: 0x000000000000891c [ 0x000000007ff88000, 000000007ff9091c, 0x000000007ffa0024) <- 00000000000000b0 Clearing Segment: addr: 0x000000007ff9091c memsz: 0x000000000000f708 Loaded segments verified segments closed down stream Jumping to boot code at 0x20000 entry = 0x00020000 lb_start = 0x00004000 lb_size = 0x0004a000 adjust = 0x7ffb2000 buffer = 0x7ff6c000 elf_boot_notes = 0x0001b160 adjusted_boot_notes = 0x7ffcd160 ROM segment 0x0000 length 0x0000 reloc 0x00020000 CPU 2088 Mhz Etherboot 5.2.6 (GPL) http://etherboot.org Tagged ELF for [E1000] Relocating _text from: [00020000,00039710) to [7fee68f0,7ff00000) Boot from (N)etwork or (Q)uit? N .Probing pci nic... [e1000-82541gi]Ethernet addr: 00:D0:68:09:EC:FD e1000: Valid Link not detected [e1000-82541gi]Ethernet addr: 00:D0:68:09:EC:FE Searching for server (DHCP)... ...Me: xxx.xxx.xxx.xxx, Server: 134.155.45.16, Gateway xxx.xxx.xxx.xxx Loading xxx.xxx.xxx.xxx:/htxlinux.0 ... (ELF)... ............................................................................................................. ........................................................................................................................................................... ........................................................................................................................................................... ........................................................................................................................................................... ........................................................................................................................................................... ...................................................................done Firmware type: LinuxBIOS [View Less]

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coreboot July 2006