coreboot November 2006

coreboot@coreboot.org

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260 discussions

[LinuxBIOS] Recommendations on Fully Free Workstation hardware
by Dave Crossland 27 Nov '06

27 Nov '06

Hi, I contacted some UK custom PC shops and only one got back to me - nsys.co.uk - and I really recommend their customer service! :-) The machine they have put together totals £1018.27 The motherboard is a "Tyan Thunder K8SE (S2892G3NR)" with a single Opteron 250 2.4GHz Processor. Since this is a server-grade motherboard, it requires an expensive (£200) PSU - a "24Pin 8 Pin Enermax Server Grade". The "128MB Asus Radeon X300SE Extreme" appears to use the r300 chipset which is being steadily more supported by X.org I am considering "Seagate 250Gb NCQ" harddisk, and the NCQ features are not yet supported - http://en.wikipedia.org/wiki/Native_Command_Queuing#Operating_system_support - but should be soon. I wonder about firmware status of CD/DVD Optical disk drives and sound cards. Does this list have any recommendations and comments on the above? :-) When I get this machine, I'll write up a report about what I did and why as per http://www.fsf.org/campaigns/supportlinuxbios.html -- Regards, Dave

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[LinuxBIOS] r2508 build service
by LinuxBIOS information 26 Nov '06

26 Nov '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2508 to the LinuxBIOS source repository and caused the following changes: Change Log: Add support for the IEI NOVA-4899R 5.25 SBC mainboard (patch submitted by Luis Correia <luis.f.correia(a)gmail.com>). The code is loosely based on the Eaglelion 5bcm mainboard. Warning: this is work in progress! As of now, it does boot with serial console only (no vga), and two ethernet cards work sometimes. This has to do with the IRQ assignments, which are a complete mess. USB is now apparently working, but I can't make any device to be recognized. The PCI slot is still unusable due to the IRQ thing. Audio, other serial ports, irda, floppy and paralell port support is unknown aka untested yet. (closes #32) Signed-off-by: Luis Correia <luis.f.correia(a)gmail.com> Acked-by: Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of iwill:dk8_htx is still broken Compilation of msi:ms9185 is still broken If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] r2509 build service
by LinuxBIOS information 26 Nov '06

26 Nov '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2509 to the LinuxBIOS source repository and caused the following changes: Change Log: Cosmetic fix of the nova4899r CHIP_NAME(). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of iwill:dk8_htx is still broken Compilation of msi:ms9185 is still broken If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] #53: Add license headers to IEI NOVA-4899R code
by LinuxBIOS 26 Nov '06

26 Nov '06

#53: Add license headers to IEI NOVA-4899R code ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: critical | Milestone: Resolve license issues Component: code | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ The code committed in r2508 doesn't yet contain the proper license headers. This should be fixed ASAP. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/53> LinuxBIOS <http://www.linuxbios.org/>

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[LinuxBIOS] #32: New motherboard IEI NOVA4899R
by LinuxBIOS 26 Nov '06

26 Nov '06

#32: New motherboard IEI NOVA4899R --------------------------------------------------------+------------------- Reporter: Luis Correia <luis.f.correia(a)gmail.com> | Owner: somebody Type: enhancement | Status: new Priority: trivial | Milestone: Going mainstream Component: code | Version: v2 Keywords: | Include_gantt: 0 Dependencies: | Due_assign: MM/DD/YYYY Due_close: MM/DD/YYYY | --------------------------------------------------------+------------------- WARNING!!! this is work in progress! The following files add support for the IEI NOVA4899R 5.25 SBC mainboard. As of now, it does boot with serial console only (no vga), and two ethernet cards work sometimes. This has to do with the IRQ assignments, which are a complete mess. USB is now apparently working, but I can't make any device to be recognized. The PCI slot is still unusable due to the IRQ thing. Audio, other serial ports, irda, floppy and paralell port support is unknown aka untested yet. Please forgive me for not supplying a proper patch file. Signed-off-by: Luis Correia <luis.f.correia(a)gmail.com> -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/32> LinuxBIOS <http://www.linuxbios.org/>

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[LinuxBIOS] r2509 - trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r
by svn＠openbios.org 26 Nov '06

26 Nov '06

Author: uwe Date: 2006-11-26 20:07:20 +0100 (Sun, 26 Nov 2006) New Revision: 2509 Modified: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/mainboard.c Log: Cosmetic fix of the nova4899r CHIP_NAME(). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/mainboard.c 2006-11-26 19:05:16 UTC (rev 2508) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/mainboard.c 2006-11-26 19:07:20 UTC (rev 2509) @@ -7,6 +7,6 @@ #include "chip.h" struct chip_operations mainboard_iei_nova4899r_ops = { - CHIP_NAME("IEI nova4899r mainboard") + CHIP_NAME("IEI NOVA-4899R Mainboard") };

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[LinuxBIOS] r2508 - in trunk/LinuxBIOSv2: src/mainboard src/mainboard/iei src/mainboard/iei/nova4899r targets targets/iei targets/iei/nova4899r
by svn＠openbios.org 26 Nov '06

26 Nov '06

Author: uwe Date: 2006-11-26 20:05:16 +0100 (Sun, 26 Nov 2006) New Revision: 2508 Added: trunk/LinuxBIOSv2/src/mainboard/iei/ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/Config.lb trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/Options.lb trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/auto.c trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/chip.h trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/cmos.layout trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/debug.c trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/failover.c trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/mainboard.c trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/reset.c trunk/LinuxBIOSv2/targets/iei/ trunk/LinuxBIOSv2/targets/iei/nova4899r/ trunk/LinuxBIOSv2/targets/iei/nova4899r/Config.lb Log: Add support for the IEI NOVA-4899R 5.25 SBC mainboard (patch submitted by Luis Correia <luis.f.correia(a)gmail.com>). The code is loosely based on the Eaglelion 5bcm mainboard. Warning: this is work in progress! As of now, it does boot with serial console only (no vga), and two ethernet cards work sometimes. This has to do with the IRQ assignments, which are a complete mess. USB is now apparently working, but I can't make any device to be recognized. The PCI slot is still unusable due to the IRQ thing. Audio, other serial ports, irda, floppy and paralell port support is unknown aka untested yet. (closes #32) Signed-off-by: Luis Correia <luis.f.correia(a)gmail.com> Acked-by: Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/Config.lb 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,205 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +## +## Include the secondary Configuration files +## +#dir /pc80 +#config chip.h + +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + register "audio_irq" = "5" + register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC + register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG + register "unwanted_vpci[2]" = "0" # End of list has a zero + + device pci 12.0 on + chip superio/winbond/w83977tf + device pnp 2e.0 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # FDC + end + device pnp 2e.4 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power Management + io 0x60 = 0xe800 + end + register "com1" = "{115200}" + register "com2" = "{115200}" + end + device pci 12.1 on end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + + end + + # VGA onboard + device pci 12.4 on + chip drivers/pci/onboard + device pci 12.4 on end + register "rom_address" = "0xfffc0000" #256k image + #register "rom_address" = "0xfff80000" #512k image + #register "rom_address" = "0xfff00000" #1M image + end # VGA + end # VGA + + device pci 0a.0 on end # ETH0 + device pci 0b.0 on end # ETH1 + device pci 0c.0 on end # ETH2 + device pci 0f.0 on end # ETH3 + + device pci 13.0 on # USB + end + + end + end + + chip cpu/amd/model_gx1 + end + +end + Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/Options.lb 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,170 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_STREAM +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_COMPRESSED_ROM_STREAM_LZMA +uses CONFIG_COMPRESSED_ROM_STREAM_NRV2B +uses CONFIG_PRECOMPRESSED_ROM_STREAM + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=0 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=7 +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_STREAM = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 + +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +end + Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/auto.c 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,55 @@ +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +//#include "southbridge/intel/i440bx/i440bx_early_smbus.c" +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" +//#include "northbridge/intel/i440bx/raminit.h" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +//#include "debug.c" +//#include "lib/delay.c" + +#include "northbridge/amd/gx1/raminit.c" + +static void main(unsigned long bist) +{ + w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + sdram_init(); + + /* Check all of memory */ +#if 0 + ram_check(0x00000000, msr.lo); +#endif +#if 0 + static const struct { + unsigned long lo, hi; + } check_addrs[] = { + /* Check 16MB of memory @ 0*/ + { 0x00000000, 0x01000000 }, +#if TOTAL_CPUS > 1 + /* Check 16MB of memory @ 2GB */ + { 0x80000000, 0x81000000 }, +#endif + }; + int i; + for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + ram_check(check_addrs[i].lo, check_addrs[i].hi); + } +#endif +} Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/chip.h 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_iei_nova4899r_ops; + +struct mainboard_iei_nova4899r_config { + int nothing; +}; Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/cmos.layout (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/cmos.layout 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/debug.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/debug.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/debug.c 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,66 @@ + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/failover.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/failover.c 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,32 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/irq_tables.c 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,39 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up + * + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*5, /* there can be total 5 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0xe00, /* IRQs devoted exclusively to PCI usage */ + 0x1078, /* Vendor */ + 0x0002, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x2d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + // USB + {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + // eth0 + {0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x3, 0x0}, + // eth1 + {0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x2, 0x0}, + // eth2 + {0x00,(0x0c<<3)|0x0, {{0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x1, 0x0}, + // PCI slot + {0x00,(0x0f<<3)|0x0, {{0x04, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + } +}; +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/mainboard.c 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,12 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "chip.h" + +struct chip_operations mainboard_iei_nova4899r_ops = { + CHIP_NAME("IEI nova4899r mainboard") +}; + Added: trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/reset.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/reset.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/nova4899r/reset.c 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,43 @@ +#if 0 +//#include "arch/romcc_io.h" +#include <arch/io.h> + +typedef unsigned device_t; + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFF) << 16) | \ + (((DEV) & 0x1f) << 11) | \ + (((FN) & 0x7) << 8)) + +static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +static void pci_write_config32(device_t dev, unsigned where, unsigned value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +static unsigned pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#include "../../../northbridge/amd/amdk8/reset_test.c" + +void hard_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); +} +#endif Added: trunk/LinuxBIOSv2/targets/iei/nova4899r/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/iei/nova4899r/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/iei/nova4899r/Config.lb 2006-11-26 19:05:16 UTC (rev 2508) @@ -0,0 +1,27 @@ +# Config file for the IEI nova4899r motherboard +# This will make a target directory of nova4899r + +target nova4899r +mainboard iei/nova4899r + +#option ROM_SIZE=256*1024 + +#from OLPC definitions +option CONFIG_COMPRESSED_ROM_STREAM_NRV2B=1 +#option CONFIG_COMPRESSED_ROM_STREAM_LZMA=1 +#option CONFIG_PRECOMPRESSED_ROM_STREAM=0 +# leave 128k for vsa and 32k for VGA code +option ROM_SIZE=(256*1024)-(128*1024)-(32*1024) +option FALLBACK_SIZE=ROM_SIZE + +option DEFAULT_CONSOLE_LOGLEVEL = 8 +option MAXIMUM_CONSOLE_LOGLEVEL = 8 +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=64*1024 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" + payload /opt/linuxbios-SVN/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "fallback" +#"normal"

1 0

[LinuxBIOS] This is so bad it is funny.
by ron minnich 26 Nov '06

26 Nov '06

This is how you update EFI on a mac. I can't believe they do it this way, but I guess there is no EFI console. And, in the fashion of EFI, I guess you are not allowed to do this from the OS! Note what this means: EFI has the ability to write over itself. Oh joy. "hold down the power switch until it blinks a lot". Oh yeah. I like the part where you determine success. ron ====== This update is for Mac mini computers with Intel processors only. Note: Print or write down these instructions before you begin the update. To update the firmware on your Intel-based Mac mini: 1. Quit all other open applications. 2. Click Shut Down in the Mac mini EFI Firmware Update window and wait for your computer to shut down. 3. Press and hold the power button on your Mac mini until the power indicator light flashes repeatedly to begin the update. A status bar indicates the progress of the update. Important: Do not interrupt the update. Your computer restarts automatically when the update is completed and opens the Mac mini EFI Firmware Update. 4. Click OK, if the firmware is now up-to-date. If these instructions appear on your screen again, the firmware update was not successful. Repeat steps 2, 3 and 4.

2 1

[LinuxBIOS] Maybe a help for others: How to identify interrupt routing
by Juergen Beisert 26 Nov '06

26 Nov '06

Hi, attached a small text how to identify routing in an unknown system to create a pirq table, when there is no other chance to read it back from BIOS. Its Geode-GX1 specific, but maybe could help on other platforms also. Comments are welcome. Regards Juergen

1 0

[LinuxBIOS] Intel 815
by Shaddam Corrino IV 26 Nov '06

26 Nov '06

Hello, What's the latest word on support for Intel 815 chipset? [as usual, please cc] -- Thanks! Shaddam IV

2 1

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coreboot November 2006