coreboot November 2006

coreboot@coreboot.org

61 participants
260 discussions

Re: [LinuxBIOS] SPI flash focus
by Drew Lundsten 25 Nov '06

25 Nov '06

If grounding HOLD# at power-on is working for people so far, that's great to hear. The SST datasheet implies that this is not the specified behavior, in fact my reading is that HOLD# is only sampled on SCK, and with CE# low. So perhaps it will be necessary to power up with HOLD# grounded by a pin grabber, then attach the SO8-clip-dongle with the LB/factory image and reset so the chipset reads from the dongle instead. If the chipset drives HOLD# directly, though, it gets a little messier; then it may be best to put a tristate-able buffer on the SO8-clip and overdrive the mobo's SPI flash signals for the 1-2 seconds needed to rewrite the whole thing, tristating as soon as the write is finished. That starts to require a pretty fast interface, driven over a cable, and now it's a lot messier than simply hotswapping a PLCC chip! Maybe the cost/complexity is enough of an incentive for people to improve their soldering skills (and observe good ESD practice). Soldering a bent-in DIP socket down and loading the flash on another DIP carrier is <$5 of parts, and you'll need the soldering iron for a more complex homebrewed programmer anyway. I myself like the idea of using a USB-capable Cypress PSOC micro (e.g. CY8C24894) to improve the programming cycle time, while extending the programmer cable length, but it helps that I already have the eval board for this one. Enjoy, Drew -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Segher Boessenkool Sent: Friday, November 24, 2006 7:23 AM To: Peter Stuge Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] SPI flash focus > Unfortunately it requires some special characteristics in the board > schematic, to not risk destroying the chipset. > > "Warning: please do not try to use SF100 directly on the application > system if the scenario is not in the above two cases." > > ..from their manual. I agree with them, it could be dangerous to > drive the SPI chip while it's connected if you don't know exactly how > it is connected and that it really is safe on that particular board.. The only thing that is required is that they can safely pull the HOLD# pin to ground. Any sane design will have a pull-up resistor on that line (and most other SPI lines, for that matter). That said, there probably _are_ boards that do not have a sane design. Such a shame. [Oh, it obviously also doesn't work if the chipset or the motherboard design uses HOLD# for something else already. This isn't commonly done though]. Aaaaaanyway... It is really simple to build a device like this yourself for a few bucks. SPI flash has many nice characteristics. Segher -- linuxbios mailing list linuxbios(a)linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] SPI flash focus
by Drew Lundsten 24 Nov '06

24 Nov '06

</lurk> Is anyone else focused on hardware approaches to SPI flash programming? I know this is an inexorable push and welcome it from the layout perspective, but finding a way to rewrite SPI-flash BIOS in place is an interesting challenge. My thoughts to present are to overdrive (temporarily) the signals using a SO-8 clip and maybe an ACT buffer, but obviously it's not as optimal as a BIOS Savior. JTAG would be better where supported, but I don't see a general solder-free approach. Off-reflector replies welcome. <lurk> Drew Lundsten <drew.lundsten(a)ccpu.com> +1 858-882-8828/619-895-1764 cell Continuous Computing Corporation, 9380 Carroll Park Dr, San Diego 92121

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[LinuxBIOS] SiS chipset support?
by Drew Lundsten 24 Nov '06

24 Nov '06

I have a P4 box with a SiS96x chipset. I hunted around the Wiki to no avail - is SiS just a Bad Idea (due to NDA or other limitation) when it comes to LinuxBIOS support? I'd like to start with LinuxBIOS and this is already my Linux box, but I have an 865G and 915GM too so if SiS support is hopeless I can focus on these. Thanks, Drew Drew Lundsten <drew.lundsten(a)ccpu.com> +1 858-882-8828/619-895-1764 cell Continuous Computing Corporation, 9380 Carroll Park Dr, San Diego 92121

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[LinuxBIOS] flashrom: patch for jedec.c
by Giampiero Giancipoli 24 Nov '06

24 Nov '06

Fixed write_page_write_jedec() in jedec.c. Added a check-reprogram loop in the same function, to come around the high page write failure rate on some boards. Signed-off-by: Giampiero Giancipoli <gianci(a)email.it> --

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[LinuxBIOS] Potential port?
by Nathanael D. Noblet 24 Nov '06

24 Nov '06

So here is the lspci of the board I have (which includes a post lcd readout directly on the mobo). I'm a little concerned that the lspci doesn't recognize the Host and PCI bridges... So what are my chances on this one? This is the motherboard: http://www.abit-usa.com/products/mb/techspec.php?categories=1&model=311 And attached lspci

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[LinuxBIOS] Need help with northbridge section of Config.lb
by Jon Dufresne 23 Nov '06

23 Nov '06

Hello, I am currently trying to configure my Config.lb of the mainboard section to work with my board. I modeled my file after the digitallogic/adl855pc since it uses the same north/southbridge as my board. I am having trouble finding complete documenatation about how to write this section of the config, perhaps if I get this working I'd be willing to create some to help others. So I was wondering if anyone with more experience than I could look over what I have so far and let me know if I'm on the right track, or way off. I'm really not sure what to put where. I'm most confused about when to put lines between "on" and "end" and when not to. What to put under the southbridge, and what not to, things like that. I'll also attach my lspci to give you some idea about what my hardware is. I am also really confused about where to get the values that appear under the superio, should I look in my superio datasheet for those? Also in the example I started with I saw lots of "register" lines in the file. Can someone give me an idea what these lines do exactly? Thanks for any help! Here is what I have so far chip northbridge/intel/i855pm device pci_domain 0 on device pci 0.0 on end # host bridge deivce pci 0.1 on end # system peripheral device pci 0.3 on end # system peripheral device pci 1.0 on end # pci bridge device pci 2.0 on end # vga controller device pci 2.1 on end # display controller chip southbridge/intel/i82801dbm device pci 1d.0 on end # usb uhci device pci 1d.1 on end # unknown device pci 1d.2 on end # unknown device pci 1d.7 on end # usb2 ehci device pci 1e.0 on end # pci bridge device pci 1f.0 on end # isa bridge device pci 1f.1 on end # ide interface device pci 1f.3 on end # smbus device pci 1f.5 on end # audio chip superio/ite/it8712f device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 # where do I get these values? irq 0x70 = 4 end device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end end end end device pci_domain 2 on device pci 8.0 on end # ethernet end end my lspci 00:00.0 Host bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Region 0: Memory at e0000000 (32-bit, prefetchable) [size=256M] Capabilities: [40] Vendor Specific Information Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=x1 00: 86 80 80 35 06 01 90 20 02 00 00 06 00 00 80 00 10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 80 35 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 a0 05 81 00 00 00 00 00 00 c1 fe 02 28 00 0e 50: 00 01 44 00 00 00 00 00 00 10 11 11 00 00 00 00 60: 0a 39 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 02 09 00 00 56 60 00 02 01 00 80 00 00 00 00 00 80: 02 00 00 a4 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 01 00 00 00 00 00 00 00 b0: 00 00 f0 e9 00 00 00 00 00 00 00 00 20 10 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 02 00 09 01 00 00 00:00.1 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 86 80 84 35 06 00 80 00 02 00 80 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 84 35 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 10 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 50: 33 77 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 44 00 2a 00 00 00 00 30 04 f1 10 00 00 00 00 70: 71 99 00 20 01 00 00 00 74 e9 1f 00 00 00 00 00 80: 39 00 af 00 3c 03 00 00 10 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 84 c6 5a df 46 00 4e 40 a0: ff a2 0a 30 00 00 00 00 7a 15 02 00 00 00 00 00 b0: 00 00 00 00 8a c1 a7 00 2c 52 00 00 fc a3 c7 05 c0: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.3 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) Subsystem: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 86 80 85 35 06 00 80 00 02 00 80 08 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 85 35 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 04 00 00 00 00 11 11 3c 4c 62 09 4b 60 09 4b 50: 60 09 00 00 00 00 00 00 01 08 39 2d 30 33 02 0b 60: 00 00 00 00 00 00 00 00 04 04 00 00 2d 41 00 00 70: 00 00 00 00 04 04 41 27 e7 c7 0f 7f 7f 00 84 02 80: ff 1f 00 00 ef 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 80 13 1f 00 00 00 00 b0: 00 00 00 00 80 02 00 00 00 00 00 00 00 00 00 00 c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00 e0: 2a 00 1f 00 98 00 9f 00 00 00 00 00 00 04 00 00 f0: 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 PCI bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to AGP Controller (rev 02) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fdc00000-fdcfffff Prefetchable memory behind bridge: fdb00000-fdbfffff Secondary status: 66Mhz+ FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 00: 86 80 81 35 07 00 a0 00 02 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 e0 e0 a0 22 20: c0 fd c0 fd b0 fd b0 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 VGA compatible controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) (prog-if 00 [VGA]) Subsystem: Intel Corporation 82852/855GM Integrated Graphics Device Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 169 Region 0: Memory at f0000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at fdf00000 (32-bit, non-prefetchable) [size=512K] Region 2: I/O ports at ff00 [size=8] Capabilities: [d0] Power Management version 1 Flags: PMEClk- DSI+ D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 82 35 07 00 90 00 02 00 00 03 00 00 80 00 10: 08 00 00 f0 00 00 f0 fd 01 ff 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 82 35 30: 00 00 00 00 d0 00 00 00 00 00 00 00 0a 01 00 00 40: 09 a0 05 81 00 40 00 00 00 00 00 00 00 00 00 00 50: 00 01 44 00 00 00 00 00 00 00 02 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: ff a2 0a 30 00 00 00 00 0e 1c 02 00 00 00 00 00 b0: 00 00 00 00 74 06 a8 00 1c 59 00 00 64 0c c9 05 c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00 e0: 2a 00 1f 00 98 00 9f 00 00 00 00 00 00 04 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.1 Display controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) Subsystem: Intel Corporation 82852/855GM Integrated Graphics Device Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at 40000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at 48000000 (32-bit, non-prefetchable) [size=512K] Capabilities: [d0] Power Management version 1 Flags: PMEClk- DSI+ D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 82 35 02 00 90 00 02 00 80 03 00 00 80 00 10: 08 00 00 40 00 00 00 48 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 82 35 30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 40: 09 a0 05 81 00 40 00 00 00 00 00 00 00 00 00 00 50: 00 01 44 00 00 00 00 00 00 00 02 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: ff a2 0a 30 00 00 00 00 4a 1c 02 00 00 00 00 00 b0: 00 00 00 00 c4 0f a8 00 8c 59 00 00 ac 5a c9 05 c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00 e0: 2a 00 1f 00 98 00 9f 00 00 00 00 00 00 04 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1d.0 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 (rev 02) (prog-if 00 [UHCI]) Subsystem: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 169 Region 4: I/O ports at fe00 [size=32] 00: 86 80 c2 24 05 00 80 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fe 00 00 00 00 00 00 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1d.1 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 (rev 02) (prog-if 00 [UHCI]) Subsystem: Intel Corporation: Unknown device 24c2 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 177 Region 4: I/O ports at fd00 [size=32] 00: 86 80 c4 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fd 00 00 00 00 00 00 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1d.2 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 (rev 02) (prog-if 00 [UHCI]) Subsystem: Intel Corporation: Unknown device 24c2 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin C routed to IRQ 185 Region 4: I/O ports at fc00 [size=32] 00: 86 80 c7 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fc 00 00 00 00 00 00 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1d.7 USB Controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI]) Subsystem: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin D routed to IRQ 193 Region 0: Memory at fdfff000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 cd 24 06 00 90 02 02 20 03 0c 00 00 00 00 10: 00 f0 ff fd 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 cd 24 30: 00 00 00 00 50 00 00 00 00 00 00 00 09 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 c9 00 00 00 00 0a 00 80 20 00 00 00 00 60: 20 20 7f 00 00 00 00 00 01 00 00 00 00 00 08 80 70: 00 00 c5 0f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3f 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 78 bf 1f 00 88 83 00 00 60 0f 00 00 06 00 00 00 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 82) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Latency: 0 Bus: primary=00, secondary=02, subordinate=02, sec-latency=32 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fde00000-fdefffff Prefetchable memory behind bridge: fdd00000-fddfffff Secondary status: 66Mhz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 00: 86 80 4e 24 07 00 80 80 82 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 20 d0 d0 80 22 20: e0 fd e0 fd d0 fd d0 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 02 28 20 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 74 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 10 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 02 00 00 00 c0 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 52 2c 00:1f.0 ISA bridge: Intel Corporation 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 86 80 c0 24 0f 00 80 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 04 00 00 10 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 08 00 00 00 81 04 00 00 10 00 00 00 60: 8a 85 8b 8a d0 00 00 00 8b 80 80 89 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 55 54 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 20 02 00 00 00 00 00 00 12 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 55 15 41 09 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 86 29 20 00 02 0f 00 00 04 00 00 00 00 00 00 00 e0: 10 00 00 c0 01 08 03 34 33 22 11 00 91 02 67 45 f0: 0f 00 40 00 00 00 00 00 60 0f 02 00 00 00 81 00 00:1f.1 IDE interface: Intel Corporation 82801DB (ICH4) IDE Controller (rev 02) (prog-if 8a [Master SecP PriP]) Subsystem: Intel Corporation: Unknown device 24c2 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 185 Region 0: I/O ports at <unassigned> Region 1: I/O ports at <unassigned> Region 2: I/O ports at <unassigned> Region 3: I/O ports at <unassigned> Region 4: I/O ports at fb00 [size=16] Region 5: Memory at 48080000 (32-bit, non-prefetchable) [size=1K] 00: 86 80 cb 24 07 00 80 02 02 8a 01 01 00 00 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: 01 fb 00 00 00 00 08 48 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00 40: 00 80 07 a3 00 00 00 00 04 00 00 02 00 00 00 00 50: 00 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 60: 08 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller (rev 02) Subsystem: Intel Corporation: Unknown device 24c2 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin B routed to IRQ 201 Region 4: I/O ports at 0500 [size=32] 00: 86 80 c3 24 01 00 80 02 02 00 05 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 05 00 00 00 00 00 00 00 00 00 00 86 80 c2 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 00:1f.5 Multimedia audio controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller (rev 02) Subsystem: Unknown device 414c:4770 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 201 Region 0: I/O ports at f400 [size=256] Region 1: I/O ports at f900 [size=64] Region 2: Memory at fdffe000 (32-bit, non-prefetchable) [size=512] Region 3: Memory at fdffd000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 c5 24 07 00 90 02 02 00 01 04 00 00 00 00 10: 01 f4 00 00 01 f9 00 00 00 e0 ff fd 00 d0 ff fd 20: 00 00 00 00 00 00 00 00 00 00 00 00 4c 41 70 47 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 02 00 00 40: 09 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00 02:08.0 Ethernet controller: Intel Corporation 82801DB PRO/100 VE (LOM) Ethernet Controller (rev 82) Subsystem: Intel Corporation: Unknown device 0001 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (2000ns min, 14000ns max), Cache Line Size 08 Interrupt: pin A routed to IRQ 209 Region 0: Memory at fdeff000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at df00 [size=64] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=2 PME- 00: 86 80 39 10 07 00 90 02 82 00 00 02 08 40 00 00 10: 00 f0 ef fd 01 df 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 01 00 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0b 01 08 38 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 22 fe e0: 00 40 00 3a 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

4 4

[LinuxBIOS] Which BIOS savior for Tyan S2895?
by Daniel Drake 22 Nov '06

22 Nov '06

Hi, I have a Tyan S2895 (K8WE) and before I zap another bios I'd like to get a BIOS savior so that recovery is easier. The BIOS chip on the motherboard is a SSC 49LF080A, 1mb in size. There are no BIOS saviors suggested for this board because the largest ones are only 0.5mb. This size is OK for me: I can fit LinuxBIOS in that and keep the real BIOS on the original 1mb chip. So, my only question is which model of BIOS savior I should get? Thanks! Daniel

3 2

[LinuxBIOS] r2507 build service
by LinuxBIOS information 22 Nov '06

22 Nov '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2507 to the LinuxBIOS source repository and caused the following changes: Change Log: Fix location of the bug tracker in the manpage (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of iwill:dk8_htx is still broken Compilation of msi:ms9185 is still broken If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2507 - trunk/LinuxBIOSv2/util/flashrom
by svn＠openbios.org 22 Nov '06

22 Nov '06

Author: uwe Date: 2006-11-22 16:27:29 +0100 (Wed, 22 Nov 2006) New Revision: 2507 Modified: trunk/LinuxBIOSv2/util/flashrom/flashrom.1 Log: Fix location of the bug tracker in the manpage (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/util/flashrom/flashrom.1 =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flashrom.1 2006-11-22 11:41:32 UTC (rev 2506) +++ trunk/LinuxBIOSv2/util/flashrom/flashrom.1 2006-11-22 15:27:29 UTC (rev 2507) @@ -1,4 +1,4 @@ -.TH FLASHROM 1 "September 19, 2006" +.TH FLASHROM 1 "November 22, 2006" .SH NAME flashrom \- the universal LinuxBIOS flash utility .SH SYNOPSIS @@ -53,7 +53,7 @@ .\".B "\-\-version" .\"Show version information and exit. .SH BUGS -Please report any bugs at http://bugzilla.openbios.org/. +Please report any bugs at http://tracker.linuxbios.org/trac/LinuxBIOS/. .SH LICENCE .B flashrom is covered by the GNU General Public License (GPL), version 2 or later.

1 0

[LinuxBIOS] IPR issues reg. VGA BIOS and ACPI
by Abins Jose 22 Nov '06

22 Nov '06

Hi, I went through the documentation for building and installing Linux BIOS. It is mentioned that VGA BIOS and ACPI tables have to be extracted from the original BIOS and included into Linux BIOS. Can the resultant Linux BIOS image be distributed freely? If not, are there other options than using the VGA BIOS and ACPI tables from the original BIOS? Thanks and regards, Abins -- Don't think you are, know you are... -- Don't think you are, know you are...

4 4

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coreboot November 2006