coreboot November 2006

coreboot@coreboot.org

61 participants
260 discussions

[LinuxBIOS] LinuxBIOS and Intel VT?
by Fischer, Anna 28 Nov '06

28 Nov '06

Hi, I have a laptop with a Mobile Intel Express Chipset 945GM and an Intel Core Duo (T2300) processor. However, the provided BIOS does not allow me to enable Intel VT (Virtualization Technology) extension. Would LinuxBIOS be a possibility to enable VT on my machine? Has anyone ever tried that before? Thanks for your help!

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[LinuxBIOS] inifinite loop after raminit
by Jon Dufresne 28 Nov '06

28 Nov '06

I can get the bios to leave raminit and begin to copy the bios to ram. I believe I initialized the SDRAM right, but I have yet to fully verify this due to an infinite loop. The loop looks like it is in the file src/arch/i386/init/crt0.S.lb I have experience with using assembly and understand assembly concepts, however, my x86 specific assembly is a bit weak. I have mostly used MIPS and Motorolla 68HC11 assembly. I put debug messages into the file to help isolate where the loop occurs, however this only confused me more. I would appreciate any help in discovering why I am looping this way. If you look below, after I reach "point 4" I should either jump to right above "point 3" or continue on to "point 5", however, the program appears to jump to around "point 2" and then from point 2 it somehow gets to "point 5", once at point 5 I have no idea why it gets back to point 2. At this point the program infinitely ping pongs between point 2 and point 5. Is this an indication that my ram isn't initialized right, or am I missing something else. As always I appreicate any help you can give. ***** Here are my modifications and console output ****** #include <arch/asm.h> #include <arch/intel.h> #include <console/loglevel.h> /* * This is the entry code the code in .reset section * jumps to this address. * */ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits intel_chip_post_macro(0x01) /* delay for chipsets */ #include "crt0_includes.h" #if USE_DCACHE_RAM == 0 #ifndef CONSOLE_DEBUG_TX_STRING /* uses: esp, ebx, ax, dx */ # define __CRT_CONSOLE_TX_STRING(string) \ mov string, %ebx ; \ CALLSP(crt_console_tx_string) # if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) # define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) # else # define CONSOLE_DEBUG_TX_STRING(string) # endif #endif /* clear boot_complete flag */ xorl %ebp, %ebp __main: CONSOLE_DEBUG_TX_STRING($str_copying_to_ram) /* * Copy data into RAM and clear the BSS. Since these segments * isn\'t really that big we just copy/clear using bytes, not * double words. */ intel_chip_post_macro(0x11) /* post 11 */ cld /* clear direction flag */ /* copy linuxBIOS from it's initial load location to * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ #if !CONFIG_COMPRESS CONSOLE_DEBUG_TX_STRING($str0) movl $_liseg, %esi movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx rep movsb #else CONSOLE_DEBUG_TX_STRING($str1) leal 4+_liseg, %esi leal _iseg, %edi movl %ebp, %esp /* preserve %ebp */ movl $-1, %ebp /* last_m_off = -1 */ jmp dcl1_n2b /* ------------- DECOMPRESSION ------------- Input: %esi - source %edi - dest %ebp - -1 cld Output: %eax - 0 %ecx - 0 */ .macro getbit bits .if \bits == 1 addl %ebx, %ebx CONSOLE_DEBUG_TX_STRING($str2) jnz 1f .endif movl (%esi), %ebx subl $-4, %esi /* sets carry flag */ adcl %ebx, %ebx 1: .endm decompr_literals_n2b: movsb decompr_loop_n2b: addl %ebx, %ebx CONSOLE_DEBUG_TX_STRING($str3) jnz dcl2_n2b dcl1_n2b: getbit 32 dcl2_n2b: CONSOLE_DEBUG_TX_STRING($str4) jc decompr_literals_n2b xorl %eax, %eax incl %eax /* m_off = 1 */ loop1_n2b: getbit 1 adcl %eax, %eax /* m_off = m_off*2 + getbit() */ getbit 1 CONSOLE_DEBUG_TX_STRING($str5) jnc loop1_n2b /* while(!getbit()) */ xorl %ecx, %ecx subl $3, %eax CONSOLE_DEBUG_TX_STRING($str6) jb decompr_ebpeax_n2b /* if (m_off == 2) goto decompr_ebpeax_n2b ? */ shll $8, %eax movb (%esi), %al /* m_off = (m_off - 3)*256 + src[ilen++] */ incl %esi xorl $-1, %eax CONSOLE_DEBUG_TX_STRING($str7) jz decompr_end_n2b /* if (m_off == 0xffffffff) goto decomp_end_n2b */ movl %eax, %ebp /* last_m_off = m_off ?*/ decompr_ebpeax_n2b: getbit 1 adcl %ecx, %ecx /* m_len = getbit() */ getbit 1 adcl %ecx, %ecx /* m_len = m_len*2 + getbit()) */ jnz decompr_got_mlen_n2b /* if (m_len == 0) goto decompr_got_mlen_n2b */ incl %ecx /* m_len++ */ loop2_n2b: getbit 1 adcl %ecx, %ecx /* m_len = m_len*2 + getbit() */ getbit 1 jnc loop2_n2b /* while(!getbit()) */ incl %ecx incl %ecx /* m_len += 2 */ decompr_got_mlen_n2b: cmpl $-0xd00, %ebp adcl $1, %ecx /* m_len = m_len + 1 + (last_m_off > 0xd00) */ movl %esi, %edx leal (%edi,%ebp), %esi /* m_pos = dst + olen + -m_off */ rep movsb /* dst[olen++] = *m_pos++ while(m_len > 0) */ movl %edx, %esi jmp decompr_loop_n2b decompr_end_n2b: intel_chip_post_macro(0x12) /* post 12 */ movl %esp, %ebp #endif CONSOLE_DEBUG_TX_STRING($str_pre_main) leal _iseg, %edi jmp *%edi .Lhlt: intel_chip_post_macro(0xee) /* post fe */ hlt jmp .Lhlt #ifdef __CRT_CONSOLE_TX_STRING /* Uses esp, ebx, ax, dx */ crt_console_tx_string: mov (%ebx), %al inc %ebx cmp $0, %al jne 9f RETSP 9: /* Base Address */ #ifndef TTYS0_BASE #define TTYS0_BASE 0x3f8 #endif /* Data */ #define TTYS0_RBR (TTYS0_BASE+0x00) /* Control */ #define TTYS0_TBR TTYS0_RBR #define TTYS0_IER (TTYS0_BASE+0x01) #define TTYS0_IIR (TTYS0_BASE+0x02) #define TTYS0_FCR TTYS0_IIR #define TTYS0_LCR (TTYS0_BASE+0x03) #define TTYS0_MCR (TTYS0_BASE+0x04) #define TTYS0_DLL TTYS0_RBR #define TTYS0_DLM TTYS0_IER /* Status */ #define TTYS0_LSR (TTYS0_BASE+0x05) #define TTYS0_MSR (TTYS0_BASE+0x06) #define TTYS0_SCR (TTYS0_BASE+0x07) mov %al, %ah 10: mov $TTYS0_LSR, %dx inb %dx, %al test $0x20, %al je 10b mov $TTYS0_TBR, %dx mov %ah, %al outb %al, %dx jmp crt_console_tx_string #endif /* __CRT_CONSOLE_TX_STRING */ #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" str_copying_to_ram: .string "Copying LinuxBIOS to ram blah.\r\n" str_pre_main: .string "Jumping to LinuxBIOS.\r\n" str0: .string "point 0\r\n" str1: .string "point 1\r\n" str2: .string "point 2\r\n" str3: .string "point 3\r\n" str4: .string "point 4\r\n" str5: .string "point 5\r\n" str6: .string "point 6\r\n" str7: .string "point 7\r\n" str8: .string "point 8\r\n" str9: .string "point 9\r\n" str10: .string "point 10\r\n" .previous #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ #endif /* USE_DCACHE_RAM */ **** And here is my output ***** Copying LinuxBIOS to ram blah. point 1 point 4 point 2 point 2 point 5 point 2 point 2 point 5 point 2 point 2 point 5 point 2 point 2 point 5 point 2 point 2 point 5 point 2 point 2 point 5 point 2 point 2 point 5 point 2 point 2 point 5 **** and it continues in this fashion. ****

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[LinuxBIOS] Your Ideal LPC/SPI programmer?
by Drew Lundsten 28 Nov '06

28 Nov '06

Time to start a separate thread on Your Ideal LPC/SPI Emulator/Programmer? Aside from the software, this should be a $20 board on a 2-layer PCB, suitable for garage assembly. (if you can get to a laser printer.) I don't know what the software wants to look like though; I would think that USB is practical for cabling and laptop builds, but USB UARTs aren't exactly the ideal interface, and mass storage is a little much for emulation in a cheap USB-capable micro. I'm pretty sure this group has some diverse needs but equally sure a common denominator can be found and done for very cheap. Enjoy, Drew

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Re: [LinuxBIOS] BIOS Savior EOL from IOSS?
by Drew Lundsten 28 Nov '06

28 Nov '06

I was, however, successful with EksitData (at least, they took my order). USD55, shipped. They do have a lot of "out of stock" in their BIOS Savior section, but indicate they have stock of the RD1-PMC4. Drew Lundsten <drew.lundsten(a)ccpu.com> +1 858-882-8828/619-895-1764 cell Continuous Computing Corporation, 9380 Carroll Park Dr, San Diego 92121 -----Original Message----- From: Corey Osgood [mailto:corey_osgood@verizon.net] Sent: Monday, November 27, 2006 7:28 PM To: Drew Lundsten Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] BIOS Savior EOL from IOSS? Drew Lundsten wrote: > I just received this response to my RD1-PMC4 order. I'll hit up > EksitData and see what I can score. Meanwhile, if this group foresees a > need for a group buy, it's probably time to coordinate while IOSS can > still consider a last build. > > Drew > > > > Dear Drew, > > Thank you very much for your order. > > Since we don't have any RD1 stock and have no plan to make. > > Please contact to annbritt(a)eksitdata.com or their website. They may have > stock. > www.eksitdata.com > www.eksitdata.com/_uk > > We are very sorry for the inconvenience. > > Best Regards, > > > ---------------------------------------------- > Vivian Lu > > IOSS International Co., Ltd. > 17F-9, No.189, Sec2, Keelung Rd., Taipei 110 Taiwan > Tel:886-2-2737-1300 ext. 388 > Fax:886-2-2737-1381 > Email: vivian(a)ioss.com.tw > URL:http//www.ioss.com.tw > > I got a similar reply: Hi Thank you for interesting RD1. We are sorry that we stop selling RD1 product due to no stock. We are sorry for the inconvenience caused. Best Regards, ---------------------------------------------- Vivian Lu

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[LinuxBIOS] BIOS Savior EOL from IOSS?
by Drew Lundsten 28 Nov '06

28 Nov '06

I just received this response to my RD1-PMC4 order. I'll hit up EksitData and see what I can score. Meanwhile, if this group foresees a need for a group buy, it's probably time to coordinate while IOSS can still consider a last build. Drew Dear Drew, Thank you very much for your order. Since we don't have any RD1 stock and have no plan to make. Please contact to annbritt(a)eksitdata.com or their website. They may have stock. www.eksitdata.com www.eksitdata.com/_uk We are very sorry for the inconvenience. Best Regards, ---------------------------------------------- Vivian Lu IOSS International Co., Ltd. 17F-9, No.189, Sec2, Keelung Rd., Taipei 110 Taiwan Tel:886-2-2737-1300 ext. 388 Fax:886-2-2737-1381 Email: vivian(a)ioss.com.tw URL:http//www.ioss.com.tw

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Re: [LinuxBIOS] LinuxBIOS for AOpen Mini PC
by Drew Lundsten 28 Nov '06

28 Nov '06

http://www.intel.com/design/chipsets/mobile/915gmdocumentation.htm has plenty of goodies. I'd appreciate someone's glance at this to see if it's still inadequate to LinuxBIOS development (i.e. is the Restricted Secret BIOS Writer's Guide really needed). I do have access to the relevant RS/orange-cover docs but have not yet approached Intel about this specific chip in the context of LinuxBIOS. My plan was to see how I fare with the public docs, but it looks like someone is ready way earlier than I would be. :) Drew Lundsten <drew.lundsten(a)ccpu.com> +1 858-882-8828/619-895-1764 cell Continuous Computing Corporation, 9380 Carroll Park Dr, San Diego 92121 -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of ron minnich Sent: Monday, November 27, 2006 5:54 PM To: George Nincehelser Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] LinuxBIOS for AOpen Mini PC can you get the data sheets from intel? ron -- linuxbios mailing list linuxbios(a)linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] LinuxBIOS for AOpen Mini PC
by George Nincehelser 28 Nov '06

28 Nov '06

I'd like to get LinuxBIOS running on an AOpen Mini PC. >From the output below, do you think this is doable? Or am I doomed to living with 15-second BIOS times? If so, pointers on how to get started would be appreciated. Thanks George #lspci -vvv 00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 04) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Capabilities: [e0] Vendor Specific Information 00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04) (prog-if 00 [VGA]) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 193 Region 0: Memory at d0180000 (32-bit, non-prefetchable) [size=512K] Region 1: I/O ports at ea00 [size=8] Region 2: Memory at c0000000 (32-bit, prefetchable) [size=256M] Region 3: Memory at d0200000 (32-bit, non-prefetchable) [size=256K] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Region 0: Memory at d0100000 (32-bit, non-prefetchable) [size=512K] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 (rev 04) (prog-if 00 [UHCI]) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 177 Region 4: I/O ports at eb00 [size=32] 00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 (rev 04) (prog-if 00 [UHCI]) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 185 Region 4: I/O ports at ed00 [size=32] 00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 (rev 04) (prog-if 00 [UHCI]) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin C routed to IRQ 169 Region 4: I/O ports at e800 [size=32] 00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 (rev 04) (prog-if 00 [UHCI]) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin D routed to IRQ 193 Region 4: I/O ports at e900 [size=32] 00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 04) (prog-if 20 [EHCI]) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 177 Region 0: Memory at d0240000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d4) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: d0000000-d00fffff Prefetchable memory behind bridge: 0000000010000000-0000000010000000 Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [50] #0d [0000] 00:1e.2 Multimedia audio controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller (rev 04) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 201 Region 0: I/O ports at e000 [size=256] Region 1: I/O ports at ec00 [size=64] Region 2: Memory at d0241000 (32-bit, non-prefetchable) [size=512] Region 3: Memory at d0242000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge (rev 04) Subsystem: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00:1f.1 IDE interface: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller (rev 04) (prog-if 8a [Master SecP PriP]) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 169 Region 0: I/O ports at <unassigned> Region 1: I/O ports at <unassigned> Region 2: I/O ports at <unassigned> Region 3: I/O ports at <unassigned> Region 4: I/O ports at f000 [size=16] 00:1f.3 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller (rev 04) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin B routed to IRQ 185 Region 4: I/O ports at 5000 [size=32] 01:03.0 FireWire (IEEE 1394): Agere Systems FW323 (rev 61) (prog-if 10 [OHCI]) Subsystem: AOPEN Inc. Unknown device 030a Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (3000ns min, 6000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 185 Region 0: Memory at d0021000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 01:06.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit Ethernet (rev 10) Subsystem: AOPEN Inc. Unknown device 0589 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (8000ns min, 16000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 169 Region 0: I/O ports at d000 [size=256] Region 1: Memory at d0020000 (32-bit, non-prefetchable) [size=256] [virtual] Expansion ROM at 10000000 [disabled] [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME-

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[LinuxBIOS] r2510 build service
by LinuxBIOS information 27 Nov '06

27 Nov '06

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2510 to the LinuxBIOS source repository and caused the following changes: Change Log: add Config.lb files for abuild. This fixes both boards (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of iwill:dk8_htx has been fixed Compilation of msi:ms9185 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] r2510 - in trunk/LinuxBIOSv2/targets: iwill/dk8_htx msi/ms9185
by svn＠openbios.org 27 Nov '06

27 Nov '06

Author: stepan Date: 2006-11-27 17:32:49 +0100 (Mon, 27 Nov 2006) New Revision: 2510 Added: trunk/LinuxBIOSv2/targets/iwill/dk8_htx/Config-abuild.lb trunk/LinuxBIOSv2/targets/msi/ms9185/Config-abuild.lb Log: add Config.lb files for abuild. This fixes both boards (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- trunk/LinuxBIOSv2/targets/iwill/dk8_htx/Config-abuild.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/iwill/dk8_htx/Config-abuild.lb 2006-11-27 16:32:49 UTC (rev 2510) @@ -0,0 +1,25 @@ +# This will make a target directory of ./iwill_dk8_htx + +target iwill_dk8_htx +mainboard iwill/dk8_htx + +option CC="gcc -m32" +option CROSS_COMPILE="" +option HOSTCC="gcc" + +option CONFIG_COMPRESSED_ROM_STREAM_LZMA=1 + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x17000 + option LINUXBIOS_EXTRA_VERSION=".0-normal" + payload /home/stepan/svn/LinuxBIOSv2/util/abuild/LinuxBIOS-payloads/payloads/default/filo-0.5.0.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x17000 + option LINUXBIOS_EXTRA_VERSION=".0-fallback" + payload /home/stepan/svn/LinuxBIOSv2/util/abuild/LinuxBIOS-payloads/payloads/default/filo-0.5.0.elf +end +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" Added: trunk/LinuxBIOSv2/targets/msi/ms9185/Config-abuild.lb =================================================================== --- trunk/LinuxBIOSv2/targets/msi/ms9185/Config-abuild.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/msi/ms9185/Config-abuild.lb 2006-11-27 16:32:49 UTC (rev 2510) @@ -0,0 +1,25 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x17000 + option LINUXBIOS_EXTRA_VERSION=".0-normal" + payload PAYLOAD +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x17000 + option LINUXBIOS_EXTRA_VERSION=".0-fallback" + payload PAYLOAD +end +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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[LinuxBIOS] Advice for buying a new and not-obsolete workstation?
by Dave Crossland 27 Nov '06

27 Nov '06

Hi, I'm in the UK and would like to buy a workstation that can be 100% Free Software, using gNewSense and a Free Software BIOS - ie, LinuxBIOS - and am not sure where to turn. Any idea? :-) ---------- Forwarded message ---------- From: lee(a)dnuk.com <lee(a)dnuk.com> Date: 09-Nov-2006 09:44 Subject: Re: http://linuxbios.org To: Dave Crossland <dave(a)lab6.com> Thursday, November 9, 2006, 1:31:53 AM, you wrote: > Hi, > I would like to buy a workstation that supports 100% Free Software, > including a Free Software BIOS. That is, something listed as fully > supported on http://linuxbios.org/Supported_Motherboards > I could not see an easy way to tell this from your website. Hello Dave, I've checked that list and you'll find all those boards are quite old, i.e. socket 754, 940 and 604 which have been replaced some time ago. None of our motherboards support the BIOS and we don't plan to offer systems with this support. Regards, Lee ____________________________________________________________________ Digital Networks United Kingdom www.dnuk.com Linux workstations, servers and storage info(a)dnuk.com -- Regards, Dave -- Regards, Dave

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coreboot November 2006