coreboot December 2004

coreboot@coreboot.org

33 participants
95 discussions

VIA Northbridge's vt8601 and vt8604
by Adam Talbot 06 Dec '04

06 Dec '04

Can any one give the the difference between the VIA Northbridge's vt8601 and vt8604. Will the code from the vt8601 be able to boot the vt8604? -Adam Talbot

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epia problem
by Luc Belliveau 06 Dec '04

06 Dec '04

I compiled from freebios2 from cvs, when I boot all I get back from the serial port is: LinuxBIOS-1.1.7.0Normal <date> starting.. vt8601 init starting Slot 00 is SDRAM 04000000 bytes x2 Slot 01 is empty Slot 02 is empty Slot 03 is empty vt8601 is done 0 that's it. I tried changing the DEFAULT_CONSOLE_LOGLEVEL but when I do that the resulting rom stops at Slot 00 is SDRAM 04000000 bytes x2. I can't add uses DEFAULT_CONSOLE_LOGLEVEL or option DEFAULT_CONSOLE_LOGLEVEL in the Config.lb file either, the buildtarget scripts shuns it. I'm using FILO as the payload, with no vga bios yet. Could it be a FILO problem? I've never seen linuxBIOS before yesterday so I don't know what should be appearing on the terminal.. Any assistance would be appreciated :) Luc

4 14

jump to boot code
by Gin 05 Dec '04

05 Dec '04

This is the message I got in the end. Linuxbios tries to load the ELF image. It seems that there are 2 segments in the ELF. In the end, linuxbios jumps to an entry that looks like the in the middle of the first segment. Does it look right? The FILO.elf doesn't seem to load succeffully. Gin ============================================================ Found ELF candiate at offset 0 (cleaned up) New segment addr 0x100000 size 0x270f0 offset 0xa0 filesize 0xd068 (cleaned up) New segment addr 0x127100 size 0x48 offset 0xd120 filesize 0x48 Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000270f0 filesz: 0x00 0000000000d068 Loading Segment: addr: 0x0000000000127100 memsz: 0x0000000000000048 filesz: 0x00 00000000000048 Jumping to boot code at 0x1092e4 entry = 0x001092e4 lb_start = 0x00004000 lb_size = 0x00024000 adjust = 0xfe5d8400 buffer = 0xfe5b8400 elf_boot_notes = 0x00015680 adjusted_boot_notes = 0xfe5eda80

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Re: epia problem/Epia status update
by Luc Belliveau 05 Dec '04

05 Dec '04

Same thing, with one small difference... I turned debugging on and this is what I get : find_ide_controller: found PCI IDE controller 1106:0571 prog_if=0x8f find_ide_controller: primary channel: native PCI mode find_ide_controller: cmd_base=0x0 ctrl_base=0x0 ide_software_reset: Waiting for ide0 to become ready for reset.. ok init_drive: Testing for hda init_drive: Probing for hda Invalid IDE Configuration: 7ed8 <-- this line used to be 3ed8 with my previous conf init_drive: Testing for hda init_drive: Probing for hda print_status: IDE: status=0xa1, err=0x0 Drive 0 does not exist boot: Also the first time I compiled filo and the rom, it halted at the elfboot screen, then I recompiled with the same settings, and filo loaded.. strange.. Luc Ronald G. Minnich wrote: >try this one > >ron >p.s. make sure you do the make config or whatever it is to remake all the >files that depend on defconf > > ># !!! NOTE !!! ># Do NOT add spaces or comments at the end of option lines. ># It confuses some versions of make. > ># Image filename for automatic boot and optional command line parameter >AUTOBOOT_FILE = "hda1:/vmlinuz-normal initrd=hda1:/initrd-normal.gz root=/dev/ram0 console=ttyS0,115200" > ># Time in second before booting AUTOBOOT_FILE >AUTOBOOT_DELAY = 2 > ># Driver for hard disk, CompactFlash, and CD-ROM on IDE bus >IDE_DISK = 1 > ># VGA text console >VGA_CONSOLE = 1 >PC_KEYBOARD = 1 > ># Serial console >SERIAL_CONSOLE = 1 >SERIAL_IOBASE = 0x3f8 >SERIAL_SPEED = 115200 > ># Filesystems >FSYS_EXT2FS = 1 >FSYS_FAT = 0 >FSYS_JFS = 0 >FSYS_MINIX = 0 >FSYS_REISERFS = 0 >FSYS_XFS = 0 >FSYS_ISO9660 = 0 > ># Support for boot disk image in bootable CD-ROM (El Torito) >ELTORITO = 0 > ># PCI support >SUPPORT_PCI = 1 > ># Enable this if not all PCI buses are scanned (you can see it with DEBUG_PCI) ># K8-based boards may need it >PCI_BRUTE_SCAN = 1 >PCI_BRUTE_SCAN_LIMIT = 2 >PCI_BRUTE_SCAN_START = 1 >IDE_HINT_BUS=1 >IDE_HINT_DEV=4 >IDE_HINT_FUNC=1 > ># Sound support (needs SUPPORT_PCI) >#SUPPORT_SOUND = 1 > ># Sound drivers >#VIA_SOUND = 1 > ># Debugging >#DEBUG_ALL = 1 >#DEBUG_ELFBOOT = 1 >#DEBUG_ELFNOTE = 1 >#DEBUG_LINUXBIOS = 1 >#DEBUG_MALLOC = 1 >#DEBUG_MULTIBOOT = 1 >#DEBUG_SEGMENT = 1 >#DEBUG_SYS_INFO = 1 >#DEBUG_TIMER = 1 >#DEBUG_BLOCKDEV = 1 >#DEBUG_PCI = 1 >#DEBUG_VIA_SOUND = 1 >#DEBUG_LINUXLOAD = 1 >#DEBUG_IDE = 1 >#DEBUG_ELTORITO = 1 > > > >

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RE: K8 D0 support
by YhLu 05 Dec '04

05 Dec '04

Opteron Rev D0 support done. So I need to wait for AMD put the updated Bios porting guide including Opteron Rev D0 info. Only after that, I can commit the patch? Or ask the AMD to review the code? Regards YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Friday, December 03, 2004 6:24 PM To: YhLu Cc: Stefan Reinauer; linuxbios(a)clustermatic.org Subject: Re: K8 D0 support YhLu <YhLu(a)tyan.com> writes: > Eric, > > Are you working on Opteron D0 support? There are some memory initialization > changes to support D0... It is on the near term TODO list, as are way to many other things. I need to make certain I have some so I can test with them. My impression the biggest change was the E0 stepping processors. In any event until the information goes into the public datasheet I can't publish anything. Eric

3 2

EPIA-MII v2 Config
by Brian Abreu 04 Dec '04

04 Dec '04

Hello, I am having trouble getting freebios2 to build for a EPIA-MII board. I cannot find any information anywhere on how to build the v2 bios for EPIA-M based boards. Can someone please explain how you do this? Thanx, Brian Abreu

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Allocating Resource for Legacy VGA Buffer
by Li-Ta Lo 04 Dec '04

04 Dec '04

Eric, I tried to allocate a MEM resource for legacy VGA framebuffer (0xA0000 - 0xBFFFF) on AMDK8 NB Fun 1. I find a new mem_pair and assigned base and size of the resource as the code show in the bottom. But at the run time the resrouce allocation code still try to allocate that resource to 0xA0000 to 0x002ffffff. Why it does not care about the resource->size field nor the FIXED flag ? Ollie static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) { struct resource *resource; unsigned link; for (link = 0; link < dev->links; link++) { if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk_info("%s: bridge on link %d has VGA device\n", dev_path(dev), link); printk_info("creating MEM pair for VGA memory\n"); /* Initialize the io space constraints on the current bus */ resource = amdk8_find_mempair(dev, nodeid, link); printk_info("MEM pair register %x\n", resource->index - 0x100); resource->base = 0xa0000; resource->size = 0x20000; resource->gran = 16; resource->align = 16; resource->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; } } } static void amdk8_set_resources(device_t dev) { unsigned nodeid, link; int i; /* Find the nodeid */ nodeid = amdk8_nodeid(dev); amdk8_create_vga_resource(dev, nodeid); /* Set each resource we have found */ for (i = 0; i < dev->resources; i++) { amdk8_set_resource(dev, &dev->resource[i], nodeid); } for(link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; if (bus->children) { assign_resources(bus); } } }

2 2

about MAINBOARD_POWER_ON_AFTER_POWER_FAIL
by zhu shi song 04 Dec '04

04 Dec '04

I'm using i845gv based MB. The superio is w83627hf . I have set MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON.Before linux booting up, I turn off power switch, when turn on power swith again, MB can boot again. But when I have booted linux successfully, I can see the console and can login linux, at this time I turn off the power switch and after 10secs then turn on it, MB can't boot again. Who have such experience to make mainboard power on again after power fail using software solution? tks zhu __________________________________ Do you Yahoo!? Yahoo! Mail - 250MB free storage. Do more. Manage less. http://info.mail.yahoo.com/mail_250

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Re: about power on
by zhu shi song 03 Dec '04

03 Dec '04

Who know the software solution? tks zhu --- Alexander Amelkin <alexander(a)amelkin.msk.ru> wrote: > Hi! > > zss> I hope when power is on, my MB can boot > without > zss> press the switch. How can I do that? > > Browse the archive of the list for the answer. > Keyword is M789. > > The main idea is to put a small (~~20uF) capacitor > between the two pins > of the power switch header on the motherboard. > > You must only do that if your motherboard does not > have a "Power Loss > Restart" or similar option in the BIOS Setup. > > LinuxBIOS as far as I know, does not allow to set > the power loss restart > option. > > -- > WBR, Alexander > mailto:spirit@reactor.ru > > __________________________________ Do you Yahoo!? Meet the all-new My Yahoo! - Try it today! http://my.yahoo.com

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How I can start a cluster with M825G VIA KM266-8235,
by Edmanuel Torres 03 Dec '04

03 Dec '04

I want to build a cluster based in the M825G with chipset VIA KM266-8235 mainboard from PCCHIPS, but I have found that this is not supported by the available configuration files in the mainboards folder. I wonder is somebody can help me in to find the way to make this board work with LinuxBios?. below is the output of the -lspci -vvv command. Thanks in advance, Edmanuel 0000:00:00.0 Host bridge: VIA Technologies, Inc. VT8375 [KM266/KL266] Host Bridge Subsystem: VIA Technologies, Inc. VT8375 [KM266/KL266] Host Bridge Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 8 Region 0: Memory at ea000000 (32-bit, prefetchable) [size=4M] Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=x2,x4 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:01.0 PCI bridge: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: e8000000-e9ffffff Prefetchable memory behind bridge: e0000000-e7ffffff BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:11.0 ISA bridge: VIA Technologies, Inc. VT8235 ISA Bridge Subsystem: VIA Technologies, Inc. VT8235 ISA Bridge Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:11.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Interrupt: pin A routed to IRQ 20 Region 4: I/O ports at dc00 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 74) Subsystem: VIA Technologies, Inc. VT6102 [Rhine II] Embeded Ethernet Controller on VT8235 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (750ns min, 2000ns max), Cache Line Size: 0x08 (32 bytes) Interrupt: pin A routed to IRQ 23 Region 0: I/O ports at e000 [size=256] Region 1: Memory at ea401000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:01:00.0 VGA compatible controller: S3 Inc. VT8375 [ProSavage8 KM266/KL266] (prog-if 00 [VGA]) Subsystem: S3 Inc. VT8375 [ProSavage8 KM266/KL266] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (1000ns min, 63750ns max), Cache Line Size: 0x08 (32 bytes) Interrupt: pin A routed to IRQ 16 Region 0: Memory at e9000000 (32-bit, non-prefetchable) [size=512K] Region 1: Memory at e0000000 (32-bit, prefetchable) [size=128M] Expansion ROM at <unassigned> [disabled] [size=64K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA- ITACoh- GART64- HTrans- 64bi ================================================= Edmanuel Torres MSc. in Physics (Student) Mobile: 3008207876 - 3112022606 Phone: +57 (7)632 3477 - +57 (7)634 4000 Ext 2402 Fax: +57 (7)634 6149 - +57 (7)632 3477 Physics and Technology Plasma Group Physics School, Universidad Industrial de Santander, Bucaramanga, Colombia AA 678

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coreboot December 2004