coreboot September 2003

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68 participants
171 discussions

newer solo motherboards
by Stefan Reinauer 08 Sep '03

08 Sep '03

Testing the newmethod solo image on a newer motherboard I get the following: with 1 dimm module: LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 starting... setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 disabling dimm01 disabling dimm01 133Mhz disabling dimm01 RAM: … [View More]0x00040000 KB Ram3 Initializing memory: done Ram4 TOP_MEM: 0000000010000000 Testing DRAM : 00000000-10000000 DRAM fill: 00000000-10000000 [..] DRAM filled DRAM verify: 00000000-10000000 [..] DRAM verified Done. LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: NSC 87360 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 0 max: 1 PCI: 01:01.0 [1022/7454] enabled next_unitid: 0004 PCI: 01:04.0 [1022/7460] enabled next_unitid: 0008 HyperT reset needed HyperT reset not needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7454] ops PCI: 01:01.0 [1022/7454] enabled PCI: 01:02.0 [1022/7455] bus ops PCI: 01:02.0 [1022/7455] enabled PCI: 01:04.0 [1022/7460] enabled PCI: 01:05.0 [1022/7468] bus ops PCI: 01:05.0 [1022/7468] enabled PCI: 01:05.1 [1022/7469] ops PCI: 01:05.1 [1022/7469] enabled PCI: 01:05.2 [1022/746a] enabled PCI: 01:05.3 [1022/746b] ops PCI: 01:05.3 [1022/746b] enabled PCI: 01:05.5 [1022/746d] enabled PCI: 01:05.6 [1022/746e] enabled PCI: pci_scan_bus for bus 2 PCI: 02:00.0 [1002/5157] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: 03:00.0 [1022/7464] ops PCI: 03:00.0 [1022/7464] enabled PCI: 03:00.1 [1022/7464] ops PCI: 03:00.1 [1022/7464] enabled PCI: 03:00.2 [1022/7463] ops PCI: 03:00.2 [1022/7463] enabled PCI: 03:01.0 [1022/7462] enabled PCI: 03:05.0 [14e4/1645] enabled PCI: pci_scan_bus returning with max=03 Hyper transport scan link: 0 new max: 3 Hypertransport scan link done amdk8_scan_chains max: 3 done PCI: pci_scan_bus returning with max=03 done Allocating resources... ASSIGN RESOURCES, bus 0 PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 0 io PCI: 00:18.0 b8 <- [0xe0000000 - 0xf81fffff] node 0 link 0 mem ASSIGN RESOURCES, bus 1 PCI: 01:01.0 10 <- [0xe0000000 - 0xefffffff] prefmem PCI: 01:02.0 1c <- [0x00001000 - 0x00001fff] bus 2 io PCI: 01:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 2 prefmem PCI: 01:02.0 20 <- [0xf8000000 - 0xf80fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem PCI: 02:00.0 14 <- [0x00001000 - 0x000010ff] io PCI: 02:00.0 18 <- [0xf8000000 - 0xf800ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:04.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:04.0 24 <- [0xf8200000 - 0xf81fffff] bus 3 prefmem PCI: 01:04.0 20 <- [0xf8100000 - 0xf81fffff] bus 3 mem ASSIGN RESOURCES, bus 3 PCI: 03:00.0 10 <- [0xf8110000 - 0xf8110fff] mem PCI: 03:00.1 10 <- [0xf8111000 - 0xf8111fff] mem PCI: 03:00.2 10 <- [0xf8113000 - 0xf81130ff] mem PCI: 03:00.2 14 <- [0xf8114000 - 0xf811401f] mem PCI: 03:01.0 10 <- [0xf8112000 - 0xf8112fff] mem PCI: 03:05.0 10 <- [0xf8100000 - 0xf810ffff] mem ASSIGNED RESOURCES, bus 3 PCI: 01:05.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:05.0 00 <- [0x00000000 - 0xffffffff] mem PCI: 01:05.1 20 <- [0x000028e0 - 0x000028ef] io PCI: 01:05.2 10 <- [0x000028c0 - 0x000028df] io PCI: 01:05.5 10 <- [0x00002000 - 0x000020ff] io PCI: 01:05.5 14 <- [0x00002880 - 0x000028bf] io PCI: 01:05.6 10 <- [0x00002400 - 0x000024ff] io PCI: 01:05.6 14 <- [0x00002800 - 0x0000287f] io ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling resourcess... PCI: 00:18.0 cmd <- 00 PCI: 01:01.0 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 003e PCI: 01:02.0 cmd <- 07 PCI: 02:00.0 cmd <- 83 PCI: 01:04.0 bridge ctrl <- 0000 PCI: 01:04.0 cmd <- 07 PCI: 03:00.0 cmd <- 02 PCI: 03:00.1 cmd <- 02 PCI: 03:00.2 cmd <- 02 PCI: 03:01.0 cmd <- 02 PCI: 03:05.0 cmd <- 02 PCI: 01:05.0 cmd <- 0f PCI: 01:05.1 cmd <- 01 PCI: 01:05.2 cmd <- 01 PCI: 01:05.3 cmd <- 00 PCI: 01:05.5 cmd <- 01 PCI: 01:05.6 cmd <- 01 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 01:02.0 init PCI: 01:05.0 init lpc_init PCI: 01:05.1 init ide_init IDE1 IDE0 PCI: 01:05.3 init PCI: 03:00.0 init USB: Setting up controller.. done. PCI: 03:00.1 init USB: Setting up controller.. done. PCI: 03:00.2 init USB: Setting up controller.. done. Devices initialized mmio_base: 3670016KB totalram: 256M Initializing CPU #0 cpufixup RAM: 0x00040000 KB Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 256MB, type WB Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 rebooting... Finding PCI configuration type. [..] now it repeatedly resets into pci configuration... With 2 ram modules I found another interesting problem: LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 starting... setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 133Mhz RAM: 0x00080000 KB Ram3 Initializing memory: done Ram4 TOP_MEM: 0000000020000000 Testing DRAM : 00000000-20000000 DRAM fill: 00000000-20000000 [..] Now the testing of the first 256 MB work fine, but the second 256 MB fail completely: 10000008:0fffffc8 1000000c:0fffffcc 10000010:0fffffd0 10000014:0fffffd4 10000018:0fffffd8 10000020:0fffffe0 10000024:0fffffe4 10000028:0fffffe8 1000002c:0fffffec 10000030:0ffffff0 10000040:10000000 10000044:0fffffc4 10000048:0fffffc8 1000004c:0fffffcc [..] 10000130:0ffffff0 10000134:10000034 10000138:100000b8 10000140:10000000 10000144:0fffffc4 10000148:0fffffc8 1000014c:0fffffcc 10000150:0fffffd0 10000154:0fffffd4 10000160:0fffffe0 So far... Stefan -- Architecture Team SuSE Linux AG [View Less]

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Older Solo motherboards
by Stefan Reinauer 08 Sep '03

08 Sep '03

Hi, I chose an older solo motherboard for testing, but I can't get the system up, it bails out with "No memory" most of the time. After a coldstart it gets beyond testing the memory, but then it can't jump to the real linuxbios c image. logs attached Any idea? Stefan -- Architecture Team SuSE Linux AG

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Starting new port.
by jarcher＠pobox.com 08 Sep '03

08 Sep '03

Hey Ron, I'm starting my port to a new processor/NB and south bridge. Which tree should I be using? Thanks, Jordan At 10:22 PM 9/7/2003 -0600, ron minnich wrote: >we will test and commit if it all works. > >I think I'm going to try to get the emulator fixed and long term go with >that, but these fixes are needed for the emulator too. > >ron > > > >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios

2 1

New to list
by Mike Westfall 06 Sep '03

06 Sep '03

Hello, everyone here. This LinuxBios stuff sounds interesting. I have a Micron Millenium with a BCM DR737 motherboard sitting around doing nothing in my lab. I know, it's kind of old, but maybe it'll be good enough to provide me a learning experience... Any opinions on whether this MoBo is even worth experimenting with? ---------------------------------------------------------------------------- Mike Westfall Software/Systems Engineer, Phone: 505.665.5256 NIS-4, Space … [View More]

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about etherboot and mkelfImage
by elife elife 06 Sep '03

06 Sep '03

Hi, I am try etherboot in my epia 5000 now. When I used mkelfImage in linuxbios, it reports Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfff00000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 Loading Etherboot version: 5.2.0 Dropping non PT_LOAD segment New segment addr 0x20000 size 0xf4e0 offset 0xb0 filesize 0x5f1c (cleaned up) New segment addr 0x20000 size 0xf4e0 offset 0xb0 filesize … [View More]0x5f1c Loading Segment: addr: 0x0000000003f7f9a8 memsz: 0x000000000000f4e0 filesz: 0x0000000000005f1c Clearing Segment: addr: 0x0000000003f858c4 memsz: 0x00000000000095c4 Jumping to boot code at 0x20000 ROM segment 0x0000 length 0x0000 reloc 0x00020000 CPU 552 Mhz Etherboot 5.2.0 (GPL) http://etherboot.org Tagged ELF for [VIA 86C100] Relocating _text from: [00020000,000304f0) to [03eefb10,03f00000) Boot from (N)etwork or (Q)uit? �Probing pci nic... [dlink-530tx]rhine.c v1.0.1 2003-02-06 IO address 1800 Ethernet Address: 00:40:63:CA:E7:EC Analyzing Media type,this will take several seconds........OK Linespeed=100Mbs Fullduplex Searching for server (DHCP)... ..Me: 172.27.4.254, Server: 172.27.4.23, Gateway 172.27.4.23 Loading 172.27.4.23:kernel ...(ELF)... Loading Linux version: ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................done rhine disable Unknown bootloader class! type=0x00000000 data=0x00000000 Firmware type: LinuxBIOS �and halts. (The kernel(2.4.20) I uses work fine with linuxbios without etherboot) When I use the newest mkelfImage 2.5, mkelfImage said Internal error convert_magic 00000070 != a5a5a5a5 Any hint? By the way, what's the difference between mkelfImage and mkelfImage-1.6 in lb? Thanks! _________________________________________________________________ ��ĵ��ʼ�ϵͳ�� MSN Hotmail�� http://www.hotmail.com [View Less]

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Re: about etherboot and mkelfImage
by YhLu 06 Sep '03

06 Sep '03

1. You need to verify your Kernel is workable under Normal BIOS. 2. when you using mkelfimage, you need add parameters for Console port and baud rate. YH. -----邮件原件----- 发件人: rimy2000 [mailto:rimy2000@hotmail.com] 发送时间: 2003年9月5日 20:24 收件人: linuxbios(a)clustermatic.org 主题: Re: about etherboot and mkelfImage After I upgrade binutils to 2.14, mkelfImage 2.5 work find and the new output is Loading 172.27.4.23:vmlinuz.vo ...(ELF)... ..............................................................… [View More]

4 3

Hangs at PCI ressources
by Michel Belleau 05 Sep '03

05 Sep '03

Hi everyone. I just wanted to tell you that I finally received my two spare flash chips for my EPIA800. Considering I couldn't make it work with the Millenium, I'm trying to make it work with a standard flash chip now. At my surprise this morning, IT BOOTED! I saw something on the serial console. It looks like it's trying to allocate PCI ressources but just hangs in here. I see the greeting, it looks like it finds the southbridge but it hangs right after that. I remember seeing that it … [View More]

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Benefit of using ROM Emulator and debugging on VT8623/VT8235
by Andrew Ip 05 Sep '03

05 Sep '03

Hi, I ask those who are using ROM emulator for developing LinuxBIOS. What is the benefit of using it besides flashing romimage? Is it possible to do any code tracing? At the moment, I'm having hard time to trace an interrupt problem on vt8623/vt8235(similar to EPIA-M) where Award'USB works but LinuxBIOS doesn't. However, both has the same IRQ assignments. Furthermore, same code works on EPIA-M with proper IRQ settings. Any suggestion on debugging tools? Thanks. -Andrew -- Andrew Ip … [View More]

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re: [COMMIT] Infrastructure Updates 4
by YhLu 04 Sep '03

04 Sep '03

Eric, The AGP display Adapter shown out too. When enumerating the CPU 0 Link0 for 8151, it first collapse the early non-conherent device 5:0.0 ( 8151) and then assign unit id (1) to him. So the device id is change to 5:1.0. After that on bus5 there is a invalid device 5:0.0 is there.( Child of Bus 5). I wonder that We should remove that invalid device or change unit id back to 0 before calling pci_scan_bus. According to AMD datasheet, the device on bus other bus 0 can use 0 as unit id. Of' … [View More]course should name it some bigger unit id and after enumerating chain, change it back to 0. It hang out after scan link2 and link0. ??? Regards YH. Jumping to LinuxBIOS. LinuxBIOS-1.1.42.0_Fallback Fri Sep 5 02:45:43 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled PCI: 01:04.6 [1022/746e] enabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled PCI: 04:01.0 [1022/7462] enabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 4 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 Hypertransport link capability not foundPCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled PCI: 05:00.0 No device operations PCI: pci_scan_bus for bus 6 PCI: 06:00.0 [10de/0322] enabled PCI: pci_scan_bus returning with max=06 PCI: pci_scan_bus returning with max=06 Hyper transport scan link: 0 new max: 6 Hypertransport scan link done [View Less]

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A question on the SC 520
by ron minnich 04 Sep '03

04 Sep '03

My first shot at a simpler target for V2 is the AMD Elan SC520. It's as different from the K8 as I can get. I can thus test the structure of V2 and see how hard this will be. V2 is good at really complex systems such as the K8 (probably the most complex system we've ever done); how hard is it for really simple systems; how much of a burden is the "complex system" support when writing for a simple system? This is a pretty integrated chip. It can't be said to have a north/southbridge per se. … [View More]

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coreboot September 2003