coreboot September 2003

coreboot@coreboot.org

68 participants
171 discussions

Laptop with Sis 650 chipset
by prl-linuxbios＠sychron.com 09 Sep '03

09 Sep '03

I'm planning on getting a laptop; there's a likely candidate with a SiS 650 chipset. Out of curiosity, is it likely that this will be LinuxBIOSable in the near future? Obviously, I haven't got the thing yet, so I can't send the output of lspci -vv. :) I'd be motivated to help port, after a couple of years of heckling from the sidelines, especially if the v2 tree holds out the prospect of needing no assembly. This is it, if anyone is interested: http://www.eurosimm.com/sites/eurosimm.nsf/details.jsp?ItemCode=UKPD-5JBBUH

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Acquiring Flash Parts
by Nathanael Noblet 09 Sep '03

09 Sep '03

Hello, I have an EPIA 800. I would like to start with linux bios on this machine. Unfortunately, they only sell the flash parts in rails of 30. at 2.70 a piece we're not talking a passive investment. Wondering two things. Can I use a different part. If so, how do I find out, and which ones would work? Are there places I can order in fewer quantities? Does anyone else with an EPIA board have a different flash part then me (SST 39SF020A 70-4C-NH)? What parts are they using etc... How worried should I be, could I just flash it with linux bios? what is the likelyhood that I'd have problems? Thanks, -- Nathanael Noblet Gnat Solutions 4604 Monterey Ave NW Calgary, AB T3B 5K4 T/F 403.288.5360 C 403.809.5368 http://www.gnat.ca/

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epia-m -- accessing bios rom
by Niki Waibel 09 Sep '03

09 Sep '03

is it necessary to do some unlocking before reading/writing to the bios area of the epia-m (vt8235)? niki

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Re: [COMMIT] Infrastructure Updates 4
by YhLu 09 Sep '03

09 Sep '03

For the s2880/2882/2885, Amd8111 LPC is actually the PCI_DEV(1,0x4,0). Regards Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年9月8日 8:03 收件人: Stefan Reinauer 抄送: YhLu; ebiederman(a)lnxi.com; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 On Mon, 8 Sep 2003, Stefan Reinauer wrote: > * YhLu <YhLu(a)tyan.com> [030906 04:58]: > > Eric, > > > > Without hard_reset, s2885 is ok now. > > Did you have a look at the implementation of hard_reset in reset.c? > void hard_reset(void) > { > set_bios_reset(); > pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); > } the only reset.c I see is in the mainboard-specific code. Nevertheless this code really should do the find_device thing. on the list of fixes. ron

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Re: Acquiring Flash Parts
by Michel Belleau 08 Sep '03

08 Sep '03

Selon linuxbios-request(a)clustermatic.org: > Hello, > I have an EPIA 800. I would like to start with linux bios on this > machine. Unfortunately, they only sell the flash parts in rails of 30. > at 2.70 a piece we're not talking a passive investment. Wondering two > things. Can I use a different part. If so, how do I find out, and which > ones would work? Are there places I can order in fewer quantities? Does > anyone else with an EPIA board have a different flash part then me (SST > 39SF020A 70-4C-NH)? What parts are they using etc... Hi. I have a EPIA 800 too. I don't want to make an ad for them, but www.badflash.com sent me two blank chips by mail for 10$ each. That's fair and I can keep a backup copy of my original BIOS away from my test lab in case something goes terribly wrong. They didn't send me the exact same SST chip, but it works great. -- Michel Belleau <michel.belleau(a)malaiwah.com>

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newest code release for arima/hdama and ...
by ron minnich 08 Sep '03

08 Sep '03

linux is no longer seeing many of the pci devices. I'm going to take a look, didn't see any obvious reason for this, but ... This bit me as the IRQ router is no longer there. ron

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Re: K7SEM support broken in freebios?
by Alex Scarbro 08 Sep '03

08 Sep '03

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Re: [COMMIT] Infrastructure Updates 4
by ebiederman＠lnxi.com 08 Sep '03

08 Sep '03

YhLu <YhLu(a)tyan.com> writes: > Eric, > > In the k8/cpufixup.c, you have use 0x3f0000 for TOM ( you said leave 64M for > ROM and Device IO). In case that if the device need more MMIO range, it will > produce problems for example AGP. So You need compare mmio_basek with > 0x3f0000 to see if mmio_basek is smaller than 0x3f0000. ( 0xf0000000 in > bytes.) Hmm. The 64M hole was an initial hard code in raminit.c that was just a small arbitrary hole so we could access I/O devices until everything is setup properly. mmio_basek should be the lowest address at which we have devices. So cpufixup.c should be doing the right thing. Although I have a few pieces to update. > I have ever tried to move that hard_reset to mainboard.c, and it still does > not work for s2885. I will try it on s2880 again. Ok. It really depends on how your bus is enumerated. Eric

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Re: newer solo motherboards
by YhLu 08 Sep '03

08 Sep '03

HyperT reset needed HyperT reset not needed In the scan_hypertranport_chain.c missed one "else" YH. -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年9月8日 8:02 收件人: LinuxBIOS 主题: newer solo motherboards Testing the newmethod solo image on a newer motherboard I get the following: with 1 dimm module: LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 starting... setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 disabling dimm01 disabling dimm01 133Mhz disabling dimm01 RAM: 0x00040000 KB Ram3 Initializing memory: done Ram4 TOP_MEM: 0000000010000000 Testing DRAM : 00000000-10000000 DRAM fill: 00000000-10000000 [..] DRAM filled DRAM verify: 00000000-10000000 [..] DRAM verified Done. LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: NSC 87360 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 0 max: 1 PCI: 01:01.0 [1022/7454] enabled next_unitid: 0004 PCI: 01:04.0 [1022/7460] enabled next_unitid: 0008 HyperT reset needed HyperT reset not needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7454] ops PCI: 01:01.0 [1022/7454] enabled PCI: 01:02.0 [1022/7455] bus ops PCI: 01:02.0 [1022/7455] enabled PCI: 01:04.0 [1022/7460] enabled PCI: 01:05.0 [1022/7468] bus ops PCI: 01:05.0 [1022/7468] enabled PCI: 01:05.1 [1022/7469] ops PCI: 01:05.1 [1022/7469] enabled PCI: 01:05.2 [1022/746a] enabled PCI: 01:05.3 [1022/746b] ops PCI: 01:05.3 [1022/746b] enabled PCI: 01:05.5 [1022/746d] enabled PCI: 01:05.6 [1022/746e] enabled PCI: pci_scan_bus for bus 2 PCI: 02:00.0 [1002/5157] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: 03:00.0 [1022/7464] ops PCI: 03:00.0 [1022/7464] enabled PCI: 03:00.1 [1022/7464] ops PCI: 03:00.1 [1022/7464] enabled PCI: 03:00.2 [1022/7463] ops PCI: 03:00.2 [1022/7463] enabled PCI: 03:01.0 [1022/7462] enabled PCI: 03:05.0 [14e4/1645] enabled PCI: pci_scan_bus returning with max=03 Hyper transport scan link: 0 new max: 3 Hypertransport scan link done amdk8_scan_chains max: 3 done PCI: pci_scan_bus returning with max=03 done Allocating resources... ASSIGN RESOURCES, bus 0 PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 0 io PCI: 00:18.0 b8 <- [0xe0000000 - 0xf81fffff] node 0 link 0 mem ASSIGN RESOURCES, bus 1 PCI: 01:01.0 10 <- [0xe0000000 - 0xefffffff] prefmem PCI: 01:02.0 1c <- [0x00001000 - 0x00001fff] bus 2 io PCI: 01:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 2 prefmem PCI: 01:02.0 20 <- [0xf8000000 - 0xf80fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem PCI: 02:00.0 14 <- [0x00001000 - 0x000010ff] io PCI: 02:00.0 18 <- [0xf8000000 - 0xf800ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:04.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:04.0 24 <- [0xf8200000 - 0xf81fffff] bus 3 prefmem PCI: 01:04.0 20 <- [0xf8100000 - 0xf81fffff] bus 3 mem ASSIGN RESOURCES, bus 3 PCI: 03:00.0 10 <- [0xf8110000 - 0xf8110fff] mem PCI: 03:00.1 10 <- [0xf8111000 - 0xf8111fff] mem PCI: 03:00.2 10 <- [0xf8113000 - 0xf81130ff] mem PCI: 03:00.2 14 <- [0xf8114000 - 0xf811401f] mem PCI: 03:01.0 10 <- [0xf8112000 - 0xf8112fff] mem PCI: 03:05.0 10 <- [0xf8100000 - 0xf810ffff] mem ASSIGNED RESOURCES, bus 3 PCI: 01:05.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:05.0 00 <- [0x00000000 - 0xffffffff] mem PCI: 01:05.1 20 <- [0x000028e0 - 0x000028ef] io PCI: 01:05.2 10 <- [0x000028c0 - 0x000028df] io PCI: 01:05.5 10 <- [0x00002000 - 0x000020ff] io PCI: 01:05.5 14 <- [0x00002880 - 0x000028bf] io PCI: 01:05.6 10 <- [0x00002400 - 0x000024ff] io PCI: 01:05.6 14 <- [0x00002800 - 0x0000287f] io ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling resourcess... PCI: 00:18.0 cmd <- 00 PCI: 01:01.0 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 003e PCI: 01:02.0 cmd <- 07 PCI: 02:00.0 cmd <- 83 PCI: 01:04.0 bridge ctrl <- 0000 PCI: 01:04.0 cmd <- 07 PCI: 03:00.0 cmd <- 02 PCI: 03:00.1 cmd <- 02 PCI: 03:00.2 cmd <- 02 PCI: 03:01.0 cmd <- 02 PCI: 03:05.0 cmd <- 02 PCI: 01:05.0 cmd <- 0f PCI: 01:05.1 cmd <- 01 PCI: 01:05.2 cmd <- 01 PCI: 01:05.3 cmd <- 00 PCI: 01:05.5 cmd <- 01 PCI: 01:05.6 cmd <- 01 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 01:02.0 init PCI: 01:05.0 init lpc_init PCI: 01:05.1 init ide_init IDE1 IDE0 PCI: 01:05.3 init PCI: 03:00.0 init USB: Setting up controller.. done. PCI: 03:00.1 init USB: Setting up controller.. done. PCI: 03:00.2 init USB: Setting up controller.. done. Devices initialized mmio_base: 3670016KB totalram: 256M Initializing CPU #0 cpufixup RAM: 0x00040000 KB Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 256MB, type WB Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 rebooting... Finding PCI configuration type. [..] now it repeatedly resets into pci configuration... With 2 ram modules I found another interesting problem: LinuxBIOS-1.1.4.0Fallback Mon Sep 8 16:21:32 CEST 2003 starting... setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 133Mhz RAM: 0x00080000 KB Ram3 Initializing memory: done Ram4 TOP_MEM: 0000000020000000 Testing DRAM : 00000000-20000000 DRAM fill: 00000000-20000000 [..] Now the testing of the first 256 MB work fine, but the second 256 MB fail completely: 10000008:0fffffc8 1000000c:0fffffcc 10000010:0fffffd0 10000014:0fffffd4 10000018:0fffffd8 10000020:0fffffe0 10000024:0fffffe4 10000028:0fffffe8 1000002c:0fffffec 10000030:0ffffff0 10000040:10000000 10000044:0fffffc4 10000048:0fffffc8 1000004c:0fffffcc [..] 10000130:0ffffff0 10000134:10000034 10000138:100000b8 10000140:10000000 10000144:0fffffc4 10000148:0fffffc8 1000014c:0fffffcc 10000150:0fffffd0 10000154:0fffffd4 10000160:0fffffe0 So far... Stefan -- Architecture Team SuSE Linux AG _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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buildtarget - building config.py automatically
by Stefan Reinauer 08 Sep '03

08 Sep '03

Hi, I changed the buildtarget script so that it builds the config.py script automatically when it's not there (i.e. fresh checkout). It gets rebuild already if it's there but not current. Anything speaking against committing applied patch? Stefan -- Architecture Team SuSE Linux AG

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coreboot September 2003