coreboot September 2003

coreboot@coreboot.org

68 participants
171 discussions

Re: [COMMIT] Infrastructure Updates 4
by ebiederman＠lnxi.com 11 Sep '03

11 Sep '03

Stefan Reinauer <stepan(a)suse.de> writes: > * Eric W. Biederman <ebiederman(a)lnxi.com> [030902 19:28]: > > If you want all of your hypertransport devices to be on bus 0, that is > > feasible but it will take a little more work. Right now each > > hypertranport chain get's it's own bus. > > What is missing to achieve this? Just a little code. Merging busses into bus 0 is an interesting logicistics feat, but the current infrastructure will allow it. > Can this cause trouble with current board implementations? Not it is software only. > In the Tyan update code, some hardcoded bus numbers were changed. We should be able to complete remove that. Right now each Hypertransport chains appears to be it's own bus and all of that information is dynamically calculated. The busses that are Hypertranpsort chains are enumerated just like other busses. The way to look at the code is that: - device.c has the logic to enumerate and assign resources to devices and busses. - pci_device.c has the methods for doing that on pci devices. - hypertransport.c has the methods for doing that with hypertranport devices. - northbridge/amd/amdk8/northbridge.c has the drivers for the amdk8 specific northbridge. In short dynamic resource assignment should now be pretty simple and should remove the need for most of the hard codes. I have committed the code not in a final perfect state. But in a state where it works well enough to be useful. And whatever details we encounter are minor things. Passing information to the dynamic device tree from the static device tree is currently a weak area. But we are building one tree from the other so it is just a matter of a small amount of refactoring if we want to do something better. Basically what remains is to dive into the code see what it is doing, and tweak it a little if is not doing quite the right thing. But usually all that needs to happen is to improve a method of a device so that it operates better. Eric

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Re: [COMMIT] Infrastructure Updates 4
by YhLu 11 Sep '03

11 Sep '03

Eric, Without hard_reset, s2885 is ok now. In the k8/cpufixup.c need compare mmio_basek and 0x3f0000 and then assign that to TOM. Regards YH -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 12:44 收件人: ebiederman(a)lnxi.com 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 Eric, If I disable the hard_reset, it can enumerate from link2 to link0. And the 8131 on link2 and 8151 on link0 all show out. Maybe you can add MACRO to control reverse scan for AMKK8 northbridge. ( link2 then link0) But it continues to reboot. Regards Yinghai Lu Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 19:17:58 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled PCI: 01:04.6 [1022/746e] enabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled PCI: 04:01.0 [1022/7462] enabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 0 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 Hypertransport link capability not foundPCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled Copying LinuxBIOS to ram. -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:48 收件人: ebiederman(a)lnxi.com 抄送: Stefan Reinauer; LinuxBIOS 主题: re: [COMMIT] Infrastructure Updates 4 Eric, In the hypertransport_scan_chain, if the hard_reset is needed, it may produce problem. Hard_reset call 8111 LPC (B1, D4, F0) reg 0x47 to trigger Reset. But it is called before pci_scan_bus. At that time the 8111 LPC is still unkown. Regards YH -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:30 收件人: 'ebiederman(a)lnxi.com' 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 I still have problems for s2885. Amdk8_scan_bus for MC0 only from link0 to link2. link0 is connected to 8151 and link2 is connected to 8131. Then it reboot again and agin. After I reverse the scan from link2 to link0. It can scan out 8131 and 8111 but hung after "HyperT reset needed" is printed. Maybe the reset.c that I move from hdama got some problems. YH. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 17:07:56 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

4 4

re: newer solo motherboards
by YhLu 11 Sep '03

11 Sep '03

Stefan, If you set HAVE_HARD_RESET=0 in the Config.lb, does it work? YH. -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年9月8日 12:18 收件人: YhLu 抄送: LinuxBIOS 主题: Re: newer solo motherboards * YhLu <YhLu(a)tyan.com> [030908 18:55]: > HyperT reset needed > HyperT reset not needed > > In the scan_hypertranport_chain.c missed one "else" > > YH. ./src/devices/hypertransport.c:hypertransport_scan_chain() should do the right thing, i.e. trigger a reset. And it seems the reset should go to PCIDEV(1,4,0), as on all other hammer boards. But obviously the code does not do a reset, or does it continue at the same PC afterwards? > SMBus controller enabled > Ram1.00 > setting up CPU00 northbridge registers > done. > Ram2.00 How can i verify that the smbus channels LinuxBIOS uses are correct for my board? The old solos only found RAM in the first socket it seems. > Hyper transport scan link: 0 max: 1 > PCI: 01:01.0 [1022/7454] enabled next_unitid: 0004 > PCI: 01:04.0 [1022/7460] enabled next_unitid: 0008 > HyperT reset needed [ LinuxBIOS should restart HERE ] > HyperT reset not needed > PCI: pci_scan_bus for bus 1 > PCI: 01:01.0 [1022/7454] ops [..] Stefan -- Architecture Team SuSE Linux AG _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

2 1

flash_and_burn patch
by Niki Waibel 10 Sep '03

10 Sep '03

hello, i cleaned up the util/flash_and_burn dir of linuxbios cvs 20030910. everyting compiles without warnings now. i am about to add support for the msystems doc device chips. who actually maintains the util/flash_and_burn tree? i could not find any email address in the files. i am going to post a patch === $ ls -la flash_and_burn_20030910.patch.bz2 -rw-r----- 1 nwaibel staff 5539 2003-09-11 12:13 flash_and_burn_20030910.patch.bz2 === to this list if noone complains within the next 20 minutes. niki

1 1

National SC1200 with DP83815 Ethernetcontroller problem
by Bernd Mödeker 10 Sep '03

10 Sep '03

Hi list, all SC1200 internal devices were correctly detected by pci bus scan. But the only external device DP83815 count'nt be detected. Scanning PCI bus...PCI: pci_scan_bus for bus 0 POST: 0x24 PCI: 00:00.0 [1078/0001] PCI: 00:12.0 [100b/0500] PCI: 00:12.1 [100b/0501] PCI: 00:12.2 [100b/0502] PCI: 00:12.3 [100b/0503] PCI: 00:12.4 [100b/0504] PCI: 00:12.5 [100b/0505] PCI: 00:13.0 [0e11/a0f8] POST: 0x25 I am missing: PCI: 00:0E.0 [100b/0020] After some measurements I saw that there is a PCI frame generated during an access, but no ADxx signals are high during this frame. Normally AD24 which is connected to IDSEL of the Ethernetcontroller should be "high". So the DP83815 don't think that he is selected. My suggestion is that the external pci bus is not correct initialized. I attached some files of my configuration. Has anybody some advises to me? Thanks Benno Sorry for sending to admin

1 0

Heads up - /proc/kcore May Be Going Away
by prl-linuxbios＠sychron.com 10 Sep '03

10 Sep '03

Noticed this on kernel traffic shortly after noting that the description of extracting Video BIOS in the ADLO paper uses /dev/kcore. I take it that there'd be no problem in creating a more specialised architecture specific device for extracting things like parts of the BIOS. http://kt.zork.net/kernel-traffic/kt20030908_229.html#5

2 1

more than a segment of code
by Stefan Reinauer 10 Sep '03

10 Sep '03

Hi, I'm trying to adopt the AMD Quartet target to the new config scheme completely, but until now I failed when using the code I checked into CVS. The static tables and structures like the mem_controller cpu[] are twice as big as with the HDAMA most of the time, so the image does not fit in 64k anymore: /usr/lib/gcc-lib/i486-suse-linux/3.3/../../../../i486-suse-linux/bin/ld: section .reset [00000000fffffff0 -> 00000000ffffffff] overlaps section .payload [00000000ffffb5b0 -> 00000001000008ca] /usr/lib/gcc-lib/i486-suse-linux/3.3/../../../../i486-suse-linux/bin/ld: section .id [00000000ffffffd8 -> 00000000ffffffef] overlaps section .payload [00000000ffffb5b0 -> 00000001000008ca] When I set the image size to 128k (ROM_IMAGE_SIZE), I get /home/stepan/LinuxBIOS/freebios2/src/cpu/i386/reset16.inc:16:3: #error _ROMBASE is an unsupported value Is there any solution except stripping down? Best regards, Stefan Reinauer -- Architecture Team SuSE Linux AG

4 7

more on the arima/hdama pci bus problem
by ron minnich 10 Sep '03

10 Sep '03

the 8111 is being put on pci bus 1, but Linux never sees it. I'm not totally clear yet on why this is happening, but I've got to work on a different problem with this board, so if anyone has any suggestions I'll try them out later. thanks ron

2 4

overriding command line options in LinuxBIOS
by Adam Agnew 09 Sep '03

09 Sep '03

Are there currently any elf loaders that boot under linuxbios which will let you change the default command line in kernel's made with mkelfImage from the serial console? If not, can someone point me to an example of anywhere this works, perhaps outside of linuxbios? I'd like to add it. Thanks! - Adam Agnew

4 4

linuxbios, linux, hyperthreading, ACPI, and 2.4.22
by ron minnich 09 Sep '03

09 Sep '03

We're seeing an interesting problem here. 2.4.22 appears to want to rely on ACPI tables for information on hyperthreading. Diffs seem to show that the linux code that works directly with the hardware to work out hyperthreading is gone. What's happened now is that a dell box, without acpi bios support, will no longer enable hyperthreading. Turn the ACPI support on, and, on the occasions when 2.4.22 doesn't panic when coming up, it does find hyperthreaded CPUs. To panic 2.4.22 while coming up, just hit random keyboard characters while it is engaged in working out hyperthreading. It dies or, sometimes, locks up. This seems like a counterproductive change to me, as it moves Linux more in the direction of depending on factory BIOSes which may, at times, be broken. Has anyone else looked at 2.4.22, and can they confirm or disprove what we think we're seeing? thanks ron

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coreboot September 2003