coreboot November 2003

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133 discussions

re: About Hardreset on Opteron MB
by YhLu 18 Nov '03

18 Nov '03

noisy smbus? -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年11月18日 15:17 收件人: Stefan Reinauer 抄送: YhLu; 'linuxbios(a)clustermatic.org' 主题: Re: About Hardreset on Opteron MB Stefan Reinauer <stepan(a)suse.de> writes: > * YhLu <YhLu(a)tyan.com> [031118 22:50]: > > I have checked the latest code again for Opteron MB. The MB still needs to > > reset three times to get it done. > > > Can we only reset the MB only time to make the HT work at the need > > speed/width? > > It should be enough to set a global variable "reset_needed" (maybe even > in CMOS) and check this, probably after all device drivers have been > executed and thus had the chance to set that flag. > > > I mean only enable the reset in > > PCI: 00:19.3 init > > NB: Function 3 Misc Control.. resetting cpu > > When changing the parameters on Solo I always got it to one of the > reboots - My best result was to get it to the Misc Control reset before > it would hang hard. Reducing the number of reboots definitely needs to happen. I only coded the way it is currently because that generates obviously correct code. Right now I am looking at how to reduce problems when a board has a noisy smbus. So far I have not seen a single board without one. In the noisy smbus the more traffic you have the more chances there are you will have problems because of it. So it might make sense to set everything up in a very early pass before memory reset. Reset the system, and then let the existing resets will not trigger. Either that or Stefans delayed scheme. At this point I am not certain which will be easier to maintain. If we do implement the delayed reset I want to move the memory clear code up into the generic framework so we don't have to clear memory twice. But if we can get the resets over with before we initialize memory we are in better shape. That plus something like the kernels quirk interface to handle the various know bits of buggy hardware and we should be ok. Eric

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About Hardreset on Opteron MB
by YhLu 18 Nov '03

18 Nov '03

Eric, I have checked the latest code again for Opteron MB. The MB still needs to reset three times to get it done. 1. Hyper transport scan link: 0 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed 2. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. resetting cpu 3. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu Can we only reset the MB only time to make the HT work at the need speed/width? I mean only enable the reset in PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu Regards YH

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Off by eight.
by jarcher＠pobox.com 18 Nov '03

18 Nov '03

I'm generating an new CPU, SB and motherboard. I got the build up and running, but my image is off by eight bytes. The reset code that should be at the top of the ROM (xxxxFFF0) is at xxxxFFF8, so I'm short 8 bytes in the ROM image file. Anyone have a clue as to what I should look at to trace this down? Jordan

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".config" file for epia-m
by Xavier Pegenaute 18 Nov '03

18 Nov '03

Hi, anyone have a .config file for epia-m to put it as payload? at the moment my bzImage.elf is about 319Kb. Is it possible with epia and normal flash rom? Thanks.

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the really good news about i2c (smbus)
by ron minnich 18 Nov '03

18 Nov '03

SMBUS/I2C is a noisy, glitchy, buggy mess that can hang motherboards. And the motherboards, more and more, are depending on it working correctly for all their management functions. The PC world is really amazing sometimes. ron

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my question on the 8111
by ron minnich 18 Nov '03

18 Nov '03

mea culpa. Yikes, I forgot that in addition to the smbus interface on one function of this chip there is a full smbus set on the PM interface. Ooops. That makes much more sense now. ron

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linuxbios V2 on epia-m?
by Dave Ashley 18 Nov '03

18 Nov '03

I'm interested in having this but there is only epia. Can someone outline the steps involved in bringing V2 up on epia-m? I might tackle it if it looks to be something I can handle. However last time I checked (yesterday) I couldn't even build the v2 epia though. Don't let my interest stop anyone else from jumping in and doing this. -Dave

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question about amd8111_early_smbus.c
by ron minnich 18 Nov '03

18 Nov '03

Here's some enable code static void enable_smbus(void) { device_t dev; dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); } uint8_t enable; print_debug("SMBus controller enabled\r\n"); pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); enable = pci_read_config8(dev, 0x41); pci_write_config8(dev, 0x41, enable | (1 << 7)); /* clear any lingering errors, so the transaction will run */ outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); } Sounds OK, right? here's what I don't get: #define SMBUS_IO_BASE 0x0f00 #define SMBGSTATUS 0xe0 #define SMBGCTL 0xe2 #define SMBHSTADDR 0xe4 etc.etc. The io base is f00. The SMB registers get added to that: you get fe0, etc. I can interpret this two ways, one of them being that the IOBASE is fe0, and the way this is written is to optimize romcc behavior. But then I don't get this part: pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); I would expect this to be set to SUMBUS_IO_BASE|0xE0|1 so that that the IOBASE in the register is 0xfe0. Or something else is going on here and I am *really* lost. Somebody want to clear my confusion :-) ron

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440BX and SDRAM
by Erik Jansson 18 Nov '03

18 Nov '03

Hi all! I have been playing with LinuxBIOS on motherboards with Intel's 440BX chipset. I have a whole bunch of them: a Microbits Epox EP-61 BXA-M, an MSI MS6120 (dual), an Intel development board and a custom designed BX board). I have managed to get most of the stuff up and running. Two things are missing though... 1. I can't manage to initiate more than 128 MB of SDRAM (ramtest fails). I've tried a lot of different types and brands of memories, standard DIMMs and SO-DIMMS, different sizes, etc. I'm thinking it has something to do with "double sided" memory (or dual "module banks" or whatever terminology you choose). Buffer strength settings maybe? But I've tried the same settings as the standard BIOS uses (which sets up the memory correctly btw) and still no go. Some obscure bit in some obscure register? 2. Dual CPU support on the MSI board. My major concern is the memory support though. I just thought that I'd throw out a question and see if somebody has been or is working with the same thing and has bumped into something similar. The archives tell me that there has been some fierce fighting with SDRAM issues earlier and I see why... This stuff is complicated. I'm running a LinuxBIOS from CVS dated 2003-11-04. /Erik -- ______________________________________________ Check out the latest SMS services @ http://www.linuxmail.org This allows you to send and receive SMS through your mailbox. Powered by Outblaze

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re: Missing files from freebios2
by YhLu 18 Nov '03

18 Nov '03

Chris, The S2880 can boot from the very beginning. Lsi_scsi.c is about onboard scsi support. I don't know if you really need that feature. I didn't get the permission from LSI to release the code yet. So if you really need that feature, I will send the pre-built image to you. Today I will verify the config can work without that file. Regards YH. -----邮件原件----- 发件人: maillists(a)petrolhead.com [mailto:maillists@petrolhead.com] 发送时间: 2003年11月18日 9:43 收件人: 'linuxbios(a)clustermatic.org' 主题: RE: Missing files from freebios2 OK, ignore the last stupid question the zelf's are obviously the compressed kernels, guess I was a bit surprised to be there already! Doh. CVS is still missing lsi_scsi.c however. Chris > -----Original Message----- > From: maillists(a)petrolhead.com > Sent: 18 November 2003 17:27 > To: 'linuxbios(a)clustermatic.org' > Subject: Missing files from freebios2 > > > Hi, > > So my last question referred to S2880, however just noticed a > Quartet build does exist, which is what I really want, saves > me doing the port! What state is this port in at the moment? > Does it boot, I'm quite willing to help out bringing it up. > > The freebios2 cvs tree seems to be missing at least; > > tg3.zelf > lsi_scsi.c > > And more importantly for me > /suse/stepan/tg3--ide_disk.zelf > is missing, guess that's on Stefan's drive somewhere ;-) > > Chris > _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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coreboot November 2003