finally! I obtained the flash memories for epia m 10000, now i'm trying
to put LinuxBios, but in all the tests that i made no one printed
somethig throught serial line.
I have no idea about the problem. I know that serial line work because
if i put "console=tty0 console=ttyS0,115200" in lilo with the normal
bios i can see the msgs of kernel.
Any one have some binry image for an epia m-10000 ? or some other idea?
PD: I bought them in www.progshop.com
These discussions on romcc running out of registers, optimizations, inline
and all are surprising. Isn't the point of romcc to just get the system ram
up right at the beginning? Then once that is done any compiler (gcc) can be
used to write code. Because dram configuration is so complicated and
interpreting the SPD data from the dram, people would rather code that in 'C'
than in x86 asm, so that's the purpose of romcc?
* SONE Takeshi <ts1(a)tsn.or.jp> [031030 13:25]:
> On Thu, Oct 30, 2003 at 12:40:02PM +0100, Stefan Reinauer wrote:
> > * SONE Takeshi <ts1(a)tsn.or.jp> [031030 11:40]:
> > > On Thu, Oct 30, 2003 at 11:34:29AM +0100, Stefan Reinauer wrote:
> > > > I am using an etherboot payload that reads an elf image from
> > > > the first sectors on the disk. This works fine, I put filo there
> > > > so I can load a kernel from any filesystem. Unfortunately filo seems
> > > > to find no IDE controller, it says IDE channel 0 not found.
> > > > Etherboot and Linux can see the ide controller though (it's on bus 1)
> > >
> > > Maybe the problem is with my PCI code.
> > > Please send me the output log with DEBUG_ALL.
> > You only seem to scan bus 0:
> My PCI scan routine starts from bus 0, and recurses when PCI bridges are
> found. I think I took this algorithm from pciutils.
> However your board has only host bridges on bus 0, so FILO doesn't know
> if bus 1 exists.
> I checked Etherboot and it just scans bus 0 to 255 unconditionally.
> I don't know which is better.
> Anyway attached patch changes the PCI scan to Etherboot way.
Thanks. with this patch it also works using PCI.
Stefan Reinauer, SUSE LINUX AG
Teamleader Architecture Development