coreboot November 2003

coreboot@coreboot.org

44 participants
133 discussions

Re: [Fwd: NXTV's current linuxbios patch]
by Dave Ashley 06 Nov '03

06 Nov '03

>Hi, >please, now that i get the patch ...can you tell me how to apply it. >Tino. The ability to apply patches is probably a reasonable prerequisite for any hacking with freebios :^). But the posting was answering Ron's request for the patch. The problem with my patch is it is like my own fork off of an older version of freebios than what is available now. My patch would be more for informational purposes, however it could be incorporated into the freebios source in part or whole. I cut a few corners with my approach: 1) Cut and pasted some other spd/smbus code just to be able to view the DDR spd contents. The actual ddr ram configuration is *not* done in this patch, I left the code segments in hoping to study them and figure out how to do it for the epia-m. Basically the code in the smbus.inc is a copy of code that I found elsewhere in freebios. Right now it is just useless bloat. 2) I walk all over the CMOS ram contents just because I wanted a way to carry over a version string from linuxbios to linux. Linuxbios compresses everything so I couldn't easily scan the rom for a version string. There is probably another way to address this problem. I just copied the version string into the upper 128 bytes of the epia-m's cmos memory. I also use byte $0e of cmos as a flag because I do a hard pci bus reset to get the system cleanly setup. I need to keep track of whether I've already reset once so it doesn't just endlessly reset. 3) The config file used to build the epia-m is built as part of an external Makefile--I take the one inside the epia-m's directory and tack on a few extra lines that say where the payload is. The payload is built in another directory, based on etherboot code. This approach is foreign to freebios but served our purposes. There is no toplevel Makefile in the normal freebios tree. The really critical code to consider bringing into freebios/epia-m is A) VGA register init + setup B) VGA bios stuff C) VGA bios lockup fix, if an unacceptable INT is called, vga init is aborted. D) Actual pci reset on startup to reset the pci card to known state. This prevents lockups if the card is requesting an interrupt for example. E) Code to access the smbus/SPD which is a starting point to auto config of DDR F) VGA bios wants certain INT's implemented, these are implemented and seem to be ok. G) The pci firewire device comes up configured to respond to IO at 0 to 7f or so, which means the cmos ram can't be accessed. This part has to be moved out of the way. Normal pci configuration fixes this, but if you need to access some other device at those io ports early on you need to move the pci firewire device out of the way, this is a gotcha I had to get past. H) Audio + usb irq's were not initialized properly. I) The hardware status monitor was not initialized and activated. J) Shadow ram for copying the vga bios over wasn't initialized K) Shadow ram for vga bios wasn't write protected. Could be important. That's about it. I don't know the status of epia-m freebios (not freebios2). I don't know if vga is supported in the current CVS version, or any other details. -Dave

2 1

config -> default
by Stefan Reinauer 06 Nov '03

06 Nov '03

Hi, most of the builds are broken again since "config" in the mainboard config file now has to be renamed to "default". On the one hand I see the reason for most of these changes, even though I am not sure if we want to suggest that some stuff can be overridden in the target config file, like: -option CONFIG_IOAPIC=1 +default CONFIG_IOAPIC=1 Can those changing elementary stuff like this that breaks all builds try to apply some regexps on the Config files so that other builds don't break? Getting further is somewhat hard currently since the code almost instantly breaks after the last fixes are checked in.. Stefan -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

1 0

[Fwd: NXTV's current linuxbios patch]
by Xavier Pegenaute 06 Nov '03

06 Nov '03

Hi, the patch is this one, is a message from Tue, probably you will have also. If you don't have i'll send you the patch. About the memory, after the patch, in src/mainboard/via/epia-m/smbus.inc, at line 245, there is something i didn't tryed yet but i think is it. I think there is something more else... I saw in your log, i have also epia-m 10000 and ,my VGA is: lspci -n -> 01:00.0 Class 0300: 1106:3122 (rev 03) lspci -> 01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3122 (rev 03) Xavi. -----Forwarded Message----- > From: Dave Ashley <linuxbios(a)xdr.com> > To: linuxbios(a)clustermatic.org > Subject: NXTV's current linuxbios patch > Date: 04 Nov 2003 14:00:46 -0800 > > I did a clean cvs checkout of freebios, then updated to 2003/7/5, and > did a diff between what's in our cvs and that, and this is the result. > It appears to be everything I touched. I got rid of all the CVS tree > differences. >

2 1

Add size option and checks to flash_rom
by Peter Fox 06 Nov '03

06 Nov '03

The patch below adds a size option to flash_rom, and also verifies that the bios image being flashed matches the rom size. (Previously, if the rom image was too small, the image would be flashed at the beginning of the rom, so the reset vector would be in the wrong place.) The advantage of this change is that it is no longer necessary to pack the bios image up to the rom size, thus saving programming time. And it is also not necessary to hack the code if you've wired the top bit to a switch as a BIOS saviour. It still doesn't check for an image too big, though that should be taken care of in the build process. Index: flash_rom.c =================================================================== RCS file: /home/fox/freebios-latest/freebios/util/flash_and_burn/flash_rom.c,v retrieving revision 1.23 diff -u -r1.23 flash_rom.c --- flash_rom.c 2003/09/12 22:41:53 1.23 +++ flash_rom.c 2003/11/06 08:41:33 @@ -272,11 +272,12 @@ return 0; } -struct flashchip * probe_flash(struct flashchip * flash) +struct flashchip * probe_flash(struct flashchip * flash, int pretend_size) { int fd_mem; volatile char * bios; unsigned long size; + int total_size; if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); @@ -288,15 +289,18 @@ flash++; continue; } - printf("Trying %s, %d KB\n", flash->name, flash->total_size); - size = flash->total_size * 1024; + total_size = flash->total_size; + if((pretend_size != -1)&&(pretend_size < total_size)) + total_size = pretend_size; + printf("Trying %s, %d KB\n", flash->name, total_size); + size = total_size * 1024; /* BUG? what happens if getpagesize() > size!? -> ``Error MMAP /dev/mem: Invalid argument'' NIKI */ if(getpagesize() > size) { size = getpagesize(); printf("%s: warning: size: %d -> %ld\n", __FUNCTION__, - flash->total_size * 1024, (unsigned long)size); + total_size * 1024, (unsigned long)size); } bios = mmap (0, size, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) (0 - size)); @@ -310,6 +314,7 @@ if (flash->probe(flash) == 1) { printf ("%s found at physical address: 0x%lx\n", flash->name, (0 - size)); + flash->total_size = total_size; return flash; } munmap ((void *) bios, size); @@ -441,11 +446,12 @@ void usage(const char *name) { - printf("usage: %s [-rwv] [-c chipname][file]\n", name); + printf("usage: %s [-rwv] [-c chipname] [-s size] [file]\n", name); printf("-r: read flash and save into file\n" "-w: write file into flash (default when file is specified)\n" "-v: verify flash against file\n" "-c: probe only for specified flash chip\n" + "-s: pretend device is smaller, specify the size in k\n" " If no file is specified, then all that happens\n" " is that flash info is dumped\n"); exit(1); @@ -456,6 +462,7 @@ { char * buf; unsigned long size; + int pretend_size = -1; FILE * image; struct flashchip * flash; int opt; @@ -464,7 +471,7 @@ setbuf(stdout, NULL); - while ((opt = getopt(argc, argv, "rwvc:")) != EOF) { + while ((opt = getopt(argc, argv, "rwvc:s:")) != EOF) { switch (opt) { case 'r': read_it = 1; @@ -478,6 +485,9 @@ case 'c': chip_to_probe = strdup(optarg); break; + case 's': + pretend_size = atoi(optarg); + break; default: usage(argv[0]); break; @@ -500,7 +510,7 @@ */ (void) enable_flash_write(); - if ((flash = probe_flash (flashchips)) == NULL) { + if ((flash = probe_flash (flashchips, pretend_size)) == NULL) { printf("EEPROM not found\n"); exit(1); } @@ -527,12 +537,18 @@ fclose(image); printf("done\n"); } else { + unsigned long filesize = 0; if ((image = fopen (filename, "r")) == NULL) { perror(filename); exit(1); } - fread (buf, sizeof(char), size, image); + filesize = fread (buf, sizeof(char), size, image); fclose(image); + if(filesize != size) + { + fprintf(stderr, "File size doesn't match device size\n"); + exit(1); + } } if (write_it || (!read_it && !verify_it)) -- Peter Fox <peter.fox(a)aeroflex.com> Aeroflex Test Solutions Principal Design Engineer Stevenage Any opinions expressed above are http://www.aeroflex.com/ not necessarily those of Aeroflex. Tel: + 44 (0) 1438 742200

1 0

Bug in am29f040b.c causes flash device not to be recognised
by Peter Fox 06 Nov '03

06 Nov '03

The following patch needs to be applied to am29f040b.c in the utils/flash_and_burn directory: ---------------------- --- am29f040b-nv.c Wed Nov 5 14:33:34 2003 +++ am29f040b.c Wed Nov 5 14:20:26 2003 @@ -76,8 +76,8 @@ *(bios + 0x2AA) = 0x55; *(bios + 0x555) = 0x90; - id1 = *(unsigned char *) bios; - id2 = *(unsigned char *) (bios + 0x01); + id1 = *(volatile unsigned char *) bios; + id2 = *(volatile unsigned char *) (bios + 0x01); *bios = 0xF0; ---------------------- My C compiler was reordering the writes and reads, so that the flash wasn't ready to give an id when the reads occurred. I notice that all the other flash devices already seem to have this correct. -- Peter Fox <peter.fox(a)aeroflex.com> Aeroflex Test Solutions Principal Design Engineer Stevenage Any opinions expressed above are http://www.aeroflex.com/ not necessarily those of Aeroflex. Tel: + 44 (0) 1438 742200

2 2

LinuxBios in epia m-10000 (freebios2)
by Xavier Pegenaute 05 Nov '03

05 Nov '03

Hi, now i know more things :-) Yes was there some thing printed in serial line, but i was so nervious and i did'nt see it, i'm sorry. The line that is printed is: "Serial controller not found", if i search for this line in the code i find it only in: src/southbridge/via/vt8231/vt8231_early_serial.c, inside this code the lines are: static void enable_vt8231_serial(void) { unsigned long x; uint8_t c; device_t dev; outb(6, 0x80); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); if (dev == PCI_DEV_INVALID) { outb(7, 0x80); die("Serial controller not found\r\n"); ... etc. if i'm not wrong, the first problem is the southbridge, the code for epia is looking for vt8231, and i have vt8235 :-) Ok. I saw in "freebios" that there is code for vt8235, then i think that i'm going to try first with the old version, and once that i see how LinuxBios is in live, if i have enough (i hope, at least for curiosity) time i'll port it to the new one if nobody made it before. By the other hand, the northbridge in the manual is CLE266, that axactly i don't know how is named in the standard way (vt8633 may be ?), i don't know if i'll have the same problem (probably i think). ------------------------------------------------------------------ My lspci, is this: 00:00.0 Host bridge: VIA Technologies, Inc.: Unknown device 3123 00:01.0 PCI bridge: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP] 00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. OHCI Compliant IEEE 1394 Host Controller (rev 80) 00:10.0 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80) 00:10.1 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80) 00:10.2 USB Controller: VIA Technologies, Inc. UHCI USB (rev 80) 00:10.3 USB Controller: VIA Technologies, Inc.: Unknown device 3104 (rev 82) 00:11.0 ISA bridge: VIA Technologies, Inc.: Unknown device 3177 00:11.1 IDE interface: VIA Technologies, Inc. Bus Master IDE (rev 06) 00:11.5 Multimedia audio controller: VIA Technologies, Inc. AC97 Audio Controller (rev 50) 00:12.0 Ethernet controller: VIA Technologies, Inc. Ethernet Controller (rev 74) 01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3122 (rev 03) ------------------------------------------------------------------ And lspci -n, is this one: 00:00.0 Class 0600: 1106:3123 00:01.0 Class 0604: 1106:b091 00:0d.0 Class 0c00: 1106:3044 (rev 80) 00:10.0 Class 0c03: 1106:3038 (rev 80) 00:10.1 Class 0c03: 1106:3038 (rev 80) 00:10.2 Class 0c03: 1106:3038 (rev 80) 00:10.3 Class 0c03: 1106:3104 (rev 82) 00:11.0 Class 0601: 1106:3177 00:11.1 Class 0101: 1106:0571 (rev 06) 00:11.5 Class 0401: 1106:3059 (rev 50) 00:12.0 Class 0200: 1106:3065 (rev 74) 01:00.0 Class 0300: 1106:3122 (rev 03) ------------------------------------------------------------------ Thanks a lot. Xavi. PD: Sorry by the long text.

5 8

Trying to get a handle on CMOS usage
by ron minnich 05 Nov '03

05 Nov '03

I just found an issue with CMOS usage, and I am trying to figure out what tools use CMOS in which cases. So, can we summarize: - does etherboot do anything to bits in CMOS? If so, what? - what bits in CMOS is linuxbios V2 currently messing with? (yeah, I should know this, but it turns out I don't currently; I'm still looking for the place where linuxbios V2 writes to cmos nowadays) Finally, is the CMOS really 256 bytes nowadays on something like the EPIA, or are we stuck at 128 still? I'm not sure at this point. Any and all information would be nice to have. The problem I've hit is that I'm storing authentication data for Plan 9 in cmos, and it appears that linuxbios/etherboot are storing to bytes at location 0x1f or so, which is bad for me. I need to find 112 bytes that will be unmolested by either linuxbios or etherboot. thanks ron

3 2

Re: migrate VIA vt5426 to PCChip M787CL(not M787CL+)
by ron minnich 04 Nov '03

04 Nov '03

On Wed, 5 Nov 2003 riskin(a)esinosoft.com wrote: > After I migrated VIA vt5426 to new mainboard(PCChips M787CL,not M787CL+: > NB is VT8601,SB is VT82C686B),when probing PCI devices,the kernel > halted.So is there any option in LinuxBIOS need to be configed to avoid > the kernel halt? But the kernel can work well on PCChips M/B bios. This is an old bug with the chipset. I think we may still have a patch for it. If linux scans any devfn above (I think) 0x40, the chipset locks up. Sorry. ron

1 0

migrate VIA vt5426 to PCChip M787CL(not M787CL+)
by riskin＠esinosoft.com 04 Nov '03

04 Nov '03

Hello ron, After I migrated VIA vt5426 to new mainboard(PCChips M787CL,not M787CL+: NB is VT8601,SB is VT82C686B),when probing PCI devices,the kernel halted.So is there any option in LinuxBIOS need to be configed to avoid the kernel halt? But the kernel can work well on PCChips M/B bios. I used freebios 1.x,not 2.x because I knew about 1.x more than 2.x. Could you help me?thanks! riskin The boot messages: LinuxBIOS-1.0.0 Tue Nov 4 17:39:15 CST 2003 starting... Enabled first bank of RAM: 0x04000000 bytes Copying LinuxBIOS to ram. Jumping to LinuxBIOS. VGA not ready yet. POST: 0x39 LinuxBIOS-1.0.0 Tue Nov 4 17:39:15 CST 2003 booting... POST: 0x40 Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f Scanning PCI bus...PCI: pci_scan_bus for bus 0 POST: 0x24 PCI: 00:00.0 [1106/0601] PCI: 00:01.0 [1106/8601] PCI: 00:07.0 [1106/0686] PCI: 00:07.2 [1106/3038] PCI: 00:07.3 [1106/3038] PCI: 00:07.4 [1106/3057] PCI: 00:07.5 [1106/3058] PCI: 00:07.6 [1106/3068] PCI: 00:0e.0 [10ec/8139] POST: 0x25 PCI: pci_scan_bus for bus 1 POST: 0x24 PCI: 01:00.0 [1023/8500] POST: 0x25 PCI: pci_scan_bus returning with max=01 POST: 0x55 PCI: pci_scan_bus returning with max=01 POST: 0x55 done POST: 0x66 Allocating PCI resources... PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it ASSIGN RESOURCES, bus 0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io PCI: 00:01.0 24 <- [0xfe900000 - 0xfe8fffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xfd800000 - 0xfe8fffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xfd800000 - 0xfdffffff] mem PCI: 01:00.0 14 <- [0xfe800000 - 0xfe81ffff] mem PCI: 01:00.0 18 <- [0xfe000000 - 0xfe7fffff] mem ASSIGNED RESOURCES, bus 1 PCI: 00:07.2 20 <- [0x00001c00 - 0x00001c1f] io PCI: 00:07.3 20 <- [0x00001c20 - 0x00001c3f] io PCI: 00:07.5 10 <- [0x00001000 - 0x000010ff] io PCI: 00:07.5 14 <- [0x00001c40 - 0x00001c43] io PCI: 00:07.5 18 <- [0x00001c50 - 0x00001c53] io PCI: 00:07.6 10 <- [0x00001400 - 0x000014ff] io PCI: 00:0e.0 10 <- [0x00001800 - 0x000018ff] io PCI: 00:0e.0 14 <- [0xfe900000 - 0xfe9000ff] mem ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. POST: 0x88 Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:07.0 cmd <- 87 PCI: 00:07.2 cmd <- 01 PCI: 00:07.3 cmd <- 01 PCI: 00:07.4 cmd <- 00 PCI: 00:07.5 cmd <- 01 PCI: 00:07.6 cmd <- 01 PCI: 00:0e.0 cmd <- 03 PCI: 01:00.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized POST: 0x89 Disable Cache Bank2 64MB (MA type 0x8) bank 4 MA 0x0: 0 bytes bank 4 MA 0x8: 0 bytes bank 4 MA 0xe: 0 bytes Enable Cache Total 56MB + frame buffer 8MB Enabling shadow DRAM at 0xC0000-0xFFFFF: done POST: 0x70 totalram: 56M Initializing CPU #0 POST: 0x60 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB Setting fixed MTRRs(24-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 32MB, type WB Setting variable MTRR 1, base: 32MB, range: 16MB, type WB Setting variable MTRR 2, base: 48MB, range: 8MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs POST: 0x6a done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x03 Feature flags : 0x00803035 POST: 0x92 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Disabling local apic...done. POST: 0x9b CPU #0 Initialized Mainboard fixup IDE enable in reg. 48 is 0x3 set IDE reg. 48 to 0x1 IRQs in reg. 4a are 0x4 setting reg. 4a to 0x44 enables in reg 0x42 0xc9 enables in reg 0x42 read back as 0x9 IDE enable in reg.1-40 is 0x8 set IDE reg.1-40 to 0xb IDE enable in reg.1-40 read back is 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x80 command in reg 0x4 reads back as 0x7 POST: 0x75 POST: 0x77 POST: 0x91 POST: 0x92 keyboard_on POST: 0x05 POST: 0x05 POST: 0x05 POST: 0x05 POST: 0x05 POST: 0x95 Final mainboard fixup Southbridge fixup keyboard_on POST: 0x05 POST: 0x05 POST: 0x05 POST: 0x05 IDE enable in reg. 48 is 0x5 set IDE reg. 48 to 0x5 IRQs in reg. 4a are 0x4 setting reg. 4a to 0x44 enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 IDE enable in reg.1-40 is 0xb set IDE reg.1-40 to 0xb IDE enable in reg.1-40 read back is 0xb enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 Initializing vt8601 vga...POST: 0xa0 done. Setting graphics mode... pcx file at fffe0004 length 0 vga_load_pcx: not a compatible .pcx file. clocks_per_usec: 911 alpha mode set. POST: 0xa1 POST: 0xec POST: 0x9a Checking IRQ routing tables... /home/chenyq/linuxbios/NOW/freebios/src/arch/i386/lib/pirq_routing.c: 30:check_pirq_routing_table() - irq_routing_table located at: 0x0000c240 done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...succeed POST: 0x96 Wrote linuxbios table at: 00000500 - 00000688 checksum 871a Jumping to linuxbiosmain()... POST: 0xed Welcome to start32, the open sourced starter. This space will eventually hold more diagnostic information. January 2000, James Hendricks, Dale Webster, and Ron Minnich. Version 0.1 POST: 0xf1 Trying polled ide Waiting for ide disks to spin up This is a hard coded delay and longer than necessary. .. init_controller 0 at (1f0, 3f4) Testing for disk 0 Probing for disk 0 disk0 31296k cap: 200 Gunzip setup gunzip_setup output data is 0x00100000 Gunzipping boot code ................flush 0x00100000 count 0x00008000 ...................................flush 0x00108000 count 0x00008000 .....................................flush 0x00110000 count 0x00008000 ..................................flush 0x00118000 count 0x00008000 ....................................flush 0x00120000 count 0x00008000 .....................................flush 0x00128000 count 0x00008000 .....................................flush 0x00130000 count 0x00008000 ....................................flush 0x00138000 count 0x00008000 ..................................flush 0x00140000 count 0x00008000 ......................................flush 0x00148000 count 0x00008000 .....................................flush 0x00150000 count 0x00008000 ...................................flush 0x00158000 count 0x00008000 .....................................flush 0x00160000 count 0x00008000 .................................flush 0x00168000 count 0x00008000 .................................flush 0x00170000 count 0x00008000 ........................flush 0x00178000 count 0x00008000 ....................................flush 0x00180000 count 0x00008000 ....................................flush 0x00188000 count 0x00008000 ..................................flush 0x00190000 count 0x00008000 .....................................flush 0x00198000 count 0x00008000 .....................................flush 0x001a0000 count 0x00008000 ................................flush 0x001a8000 count 0x00008000 ...............................flush 0x001b0000 count 0x00008000 ................................flush 0x001b8000 count 0x00008000 ..............................flush 0x001c0000 count 0x00008000 ....................................flush 0x001c8000 count 0x00008000 ....................................flush 0x001d0000 count 0x00008000 .....................................flush 0x001d8000 count 0x00008000 ..................................flush 0x001e0000 count 0x00008000 ......................................flush 0x001e8000 count 0x00008000 ...................................flush 0x001f0000 count 0x00008000 ...............................flush 0x001f8000 count 0x00008000 .......................................flush 0x00200000 count 0x00008000 ......................................flush 0x00208000 count 0x00008000 ....................................flush 0x00210000 count 0x00008000 ......................................flush 0x00218000 count 0x00008000 ....................................flush 0x00220000 count 0x00008000 ....................................flush 0x00228000 count 0x00008000 ....................................flush 0x00230000 count 0x00008000 ....................................flush 0x00238000 count 0x00008000 ..................................flush 0x00240000 count 0x00008000 ..................................flush 0x00248000 count 0x00008000 .....................................flush 0x00250000 count 0x00008000 .....................................flush 0x00258000 count 0x00008000 ....................................flush 0x00260000 count 0x00008000 ...................................flush 0x00268000 count 0x00008000 ....................................flush 0x00270000 count 0x00008000 ...................................flush 0x00278000 count 0x00008000 .................................flush 0x00280000 count 0x00008000 ...................................flush 0x00288000 count 0x00008000 .................................flush 0x00290000 count 0x00008000 .............................flush 0x00298000 count 0x00008000 .......................flush 0x002a0000 count 0x00008000 ................flush 0x002a8000 count 0x00008000 ......................flush 0x002b0000 count 0x00008000 ...........flush 0x002b8000 count 0x00008000 ....................flush 0x002c0000 count 0x00008000 ..................flush 0x002c8000 count 0x00008000 ........................flush 0x002d0000 count 0x00008000 ...................flush 0x002d8000 count 0x00008000 .................flush 0x002e0000 count 0x00008000 ...............flush 0x002e8000 count 0x00008000 ............flush 0x002f0000 count 0x00008000 ............................flush 0x002f8000 count 0x00008000 ................................flush 0x00300000 count 0x00008000 ....................flush 0x00308000 count 0x00008000 ..............flush 0x00310000 count 0x00008000 ......................flush 0x00318000 count 0x00008000 ........................flush 0x00320000 count 0x00008000 .........................flush 0x00328000 count 0x00008000 ....................flush 0x00330000 count 0x00008000 ................................flush 0x00338000 count 0x00008000 ....................flush 0x00340000 count 0x00008000 .................flush 0x00348000 count 0x00008000 .......................................flush 0x00350000 count 0x00008000 ....................................flush 0x00358000 count 0x00008000 ...............................flush 0x00360000 count 0x00008000 .....flush 0x00368000 count 0x00002c10 <1029> POST: 0xf8 POST: 0xf9 POST: 0xfa command line - [root=/dev/hda2 rw console=ttyS0,115200n8 init=/linuxrc] Jumping to boot code POST: 0xfe Linux version 2.4.20 (root@SETI) (gcc version egcs-2.91.66 19990314/Linux (egcs-1.1.2 release)) #19 Tue Sep 9 18:04:04 CST 2003 BIOS-provided physical RAM map: BIOS-e801: 0000000000000000 - 000000000009f000 (usable) BIOS-e801: 0000000000100000 - 0000000003700000 (usable) 55MB LOWMEM available. On node 0 totalpages: 14080 zone(0): 4096 pages. zone(1): 9984 pages. zone(2): 0 pages. Kernel command line: root=/dev/hda2 rw console=ttyS0,115200n8 init=/linuxrc Initializing CPU#0 Detected 800.049 MHz processor. Calibrating delay loop... 1595.80 BogoMIPS Memory: 52592k/56320k available (1656k kernel code, 3340k reserved, 690k data, 112k init, 0k highmem) Checking if this processor honours the WP bit even in supervisor mode... Ok. Dentry cache hash table entries: 8192 (order: 4, 65536 bytes) Inode cache hash table entries: 4096 (order: 3, 32768 bytes) Mount-cache hash table entries: 1024 (order: 1, 8192 bytes) Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) Page-cache hash table entries: 16384 (order: 4, 65536 bytes) CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line) CPU: L2 Cache: 64K (32 bytes/line) CPU: Centaur VIA Samuel 2 stepping 03 Checking 'hlt' instruction... OK. Checking for popad bug... OK. POSIX conformance testing by UNIFIX PCI: Using configuration type 1 PCI: Probing PCI hardware

1 0

Re: LinuxBios in epia m-10000 (freebios2)
by Dave Ashley 04 Nov '03

04 Nov '03

>Please can you send me the patch ? This is problematic...my version is probably way out of date. Here are my original posts though: http://www.clustermatic.org/pipermail/linuxbios/2003-July/004061.html I vaguely remember sending a small tarball but I think that was to Andrew directly. The stuff in the above link doesn't have the VGA bios crash fix I came up with. It seems like no one else had any trouble with it crashing though. I can dig that up if necessary. I'll try to get a complete diff of my tree against the snapshot I started with...maybe that will be most helpful. -Dave

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2003