"Lawrence LL. Dai" <lawrence(a)tyanchina.com> writes:
> Hi, Eric
> I suppose that mknbi and mkelf would also cause this problem.Because
> they both tag a kernel, but the kernel must be the one like vmlinuz and vmlinux
> needs BIOS functions such as INT 10. (I know vmlinux does not need INT X, but
> vmlinux can not be tagged by mknbi and mkelf. Or I have missed something else?)
The difference is mknbi/mkelf that come standard with etherboot when
the process the linux kernel start the kernel in 16bit mode and run
it's BIOS code, mkelfImage simulates the effect of the 16bit BIOS
code by reading LinuxBIOS tables or making the needed BIOS calls
itself, and then it enters Linux at it's unofficial 32bit entry
mkelfImage can take either a bzImage or a vmlinux.
Where can I buy 6 rackmount servers 1GHz+ with LinuxBIOS potential?
They are for production website, so must be *stable*, if none available
with LinuxBIOS then it's back to the old (BIOS) grind. It's just that I
have the opportunity to build this from scratch, and I'd like to go
LinuxBIOS if possible.
2 need 3 ethernet + DOC roof fs + no disk - router/apache load bal
2 need 2 ethernet + load kernel over net and do NFS root ) webservers
2 need at least 2 disks hotswap SCSI (small database)
It would be wonderful to have all 6 the same chassis/motherboard, with
the difference being cards/disk plugged in. Also nice would be ability
to fall back to vendor bios in case of trouble in testing phase.
Delivery must be in 2 weeks at most.
Sorry, I do not mean I have finished the porting, I just read the raminit.inc about E7500, now I am reading E7501 and E7500 Intel bios specification. I try to find the difference between two chipsets. But I am raw in ram initialization. The part is so complex. I want to get help from you.
From: Eric W. Biederman [mailto:email@example.com]
Sent: Friday, January 10, 2003 1:26 PM
To: Terry B. Chen
Subject: Re: about E7501
"Terry B. Chen" <terryc(a)tyanchina.com> writes:
> Is anyone interested in E7501?
> What is the difference between FSB 533 and 400 in Northbridge? I have a thought
> to port E7501 to E7500.
Hey before you do that could you give me a copy of your E7501 port?
Sorry I could not resist. I doubt the differences are especially large
but I have not gone through the documents and looked closely yet.
Is anyone interested in E7501?
What is the difference between FSB 533 and 400 in Northbridge? I have a thought to port E7501 to E7500.
Someone give me some suggestions!
Thank you !
When I try Linux bios to boot from Ethernet, I find it will be blocked by an instruction of INT 10.
The kernel downloaded from TFTP server has the INT 10 instruction, while INT 10 has not been realized in Linux bios.
So it is stopped. How can I resolve the problem?
interesting note on intel speeds that I never noticed.
---------- Forwarded message ----------
Date: Thu, 09 Jan 2003 08:45:26 -0500
From: JOHN DEGOOD <jdegood(a)sarnoff.com>
Subject: Intel A, B, etc. nomenclature
When Intel does a die turn the speed range of the new processor sometimes
overlaps with the earlier die, so to distinguish the chips they use "2.0 GHz",
"2.0A GHz", "2.0B GHz", etc. The functionality often is significantly
different, e.g. the P4 "1.8 GHz" has 256K cache, while the P4 "1.8A GHz" has
512K cache, so the "1.8A" benchmarks much better.
Hi, this is not the first time I write but in the past months I was too
busy and I had no time to build a nice linuxbios-box!
However now I'm going to buy a pchips motheboard so I can start to
I've read the useful guide on the web; however I have some doubts:
what about that disc on chip device: how much does it cost more or less?
Why can't we use a normal FLASH memory like the ones used to store a
standard BIOS? I can think those chips provide particular features, but
which ones exactly? Aren't common flash/eeprom chips much easier to find
and cheaper to buy? An external programmer could be needed (like for the
eproms of etherboot) but most people could have access to such a device.
Bye bye and thank you!
P.S. I've read just now that on the pchips motherboard for athlon cpus
the L2 cache is not working. Is it true? As the cache is on the
processor and not on the mainboard, I thought this wouldn't be a problem...
Just committed a small change to Config for Intel Clearwater.
The change makes ZKERNEL_START = 0xfff00000 for a failover inage and
0xfff10000 for a primary.
This change allows for two copies of bootselect. The one at 0xfff00000
should be considered part of the failover.
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