coreboot January 2003

coreboot@coreboot.org

63 participants
95 discussions

IPMI support in Linux
by Andrew Ip 26 Mar '03

26 Mar '03

Does anyone know if IPMI works under LinuxBIOS? AFAIK, there is a Linux driver patch but dunno if it still works under LinuxBIOS. -Andrew -- Andrew Ip Email: aip(a)cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.

6 6

sourceforge cvs and wrong web page
by Alessio Sangalli 11 Feb '03

11 Feb '03

Hi. On http://www.linuxbios.org/developer/download/index.html you show the commands to checkout linuxbioss from sourceforge cvs: cvs -d:pserver:anonymous@cvs.freebios.sourceforge.net:/cvsroot/freebios login cvs-z3 -d:pserver:anonymous@cvs.freebios.sourceforge.net:/cvsroot/freebios co freebios this is wrong and "cvs.sourceforge.net" should be used (or you won't be able to download anything). bye as

3 2

giving the user a boot option
by John Allen 06 Feb '03

06 Feb '03

Does anyone think it is possible the offer the user a choice of commandline parameters. I would like to use the serial console, or something else convienient, to allow the user to choose commandline1 or commandline2. One of them mounts root over nfs, the other from the hard drive. I guess this would be a simplified boot loader such as lilo or grub. Unfortunately this 'boot loader' must reside in the flash chip, since my hard drive will initially be completely blank. John

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pc chips 810
by Alessio Sangalli 01 Feb '03

01 Feb '03

Hi. Still waiting for our burocracy to buy cwlinux motherboards, we got a pcchips 810 lmr motherboard. I've download the prepackaged image from cwlinux website and the cvs version of freebios. I flashed the file: ftp.cwlinux.com/pub/downloads/linuxbios-sdk/images/romimages/m810-ide.rom on the hard disk, connected as hda, I've made a partition hda1 of few MB and formatted as ext2. Here I've placed a kernel compiled from vanilla 2.4.20 sources and processed with: mkelfImage --kernel=/usr/src/linux-2.4.20/linux/arch/i386/boot/bzImage --command-line="console=ttyS0,115200 CONSOLE=ttyS0,115200 root=/dev/hda1 video=sisfb:640x480-8@60,font:VGA8x16" --output=kernel.elf I've renamed the kernel.elf image in "kernel" and I put it on hda1. hda2 is my root fs. When I turn the computer on, I can see (as soon as the monitor resumes from the silly dpms powerdown) a tux logo and a cursor flashing. On a serial terminal I get the attached log. At this point caps lock and no scroll leds are blinking. Frame buffer seems to work well! Why isn't my system booting properly? bye thank you as 0 LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS.LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 booting... Finding PCI configuration type. PCI: Using configuration type 1 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 0, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 0, Superio SiS 950 handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 0, done #0 handle_superio done Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1039/0730] PCI: 00:00.1 [1039/5513] PCI: 00:01.0 [1039/0008] PCI: 00:01.1 [1039/0900] PCI: 00:01.2 [1039/7001] PCI: 00:01.3 [1039/7001] PCI: 00:01.4 [1039/7018] PCI: 00:01.6 [1039/7013] PCI: 00:02.0 [1039/0001] PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1039/6300] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done totalram: 120M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB Setting variable MTRR 1, base: 64MB, range: 32MB, type WB Setting variable MTRR 2, base: 96MB, range: 16MB, type WB Setting variable MTRR 3, base: 112MB, range: 8MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : AuthenticAMD Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x08 Processor Mask : 0x00 Processor Stepping : 0x00 Feature flags : 0x0183f9ff MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] mem PCI: 00:00.1 10 <- [0x00002c90 - 0x00002c93] io PCI: 00:00.1 14 <- [0x00002ca0 - 0x00002ca3] io PCI: 00:00.1 18 <- [0x00002cb0 - 0x00002cb3] io PCI: 00:00.1 1c <- [0x00002cc0 - 0x00002cc3] io PCI: 00:00.1 20 <- [0x00002c80 - 0x00002c8f] io PCI: 00:01.1 10 <- [0x00002000 - 0x000020ff] io PCI: 00:01.1 14 <- [0xfc100000 - 0xfc100fff] mem PCI: 00:01.2 10 <- [0xfc101000 - 0xfc101fff] mem PCI: 00:01.3 10 <- [0xfc102000 - 0xfc102fff] mem PCI: 00:01.4 10 <- [0x00002400 - 0x000024ff] io PCI: 00:01.4 14 <- [0xfc103000 - 0xfc103fff] mem PCI: 00:01.6 10 <- [0x00002800 - 0x000028ff] io PCI: 00:01.6 14 <- [0x00002c00 - 0x00002c7f] io PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 ÿÿÿÿÿÿio PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 ÿÿÿÿÿÿprefmem PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 ÿÿÿÿÿÿmem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io Allocating VGA resource done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 07 PCI: 00:00.1 cmd <- 01 PCI: 00:01.0 cmd <- 0c PCI: 00:01.1 cmd <- 03 PCI: 00:01.2 cmd <- 02 PCI: 00:01.3 cmd <- 02 PCI: 00:01.4 cmd <- 03 PCI: 00:01.6 cmd <- 01 PCI: 00:02.0 cmd <- 27 PCI: 01:00.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized Enabled in SIS 503 regs 0x40 and 0x45 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 1, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 1, done #0 handle_superio done PCCHIPS M810LMR (and similar)...Entering the initregs process Southbridge fixup done for SIS 503 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 2, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call finishup handle_superio Pass 2, done #0 handle_superio done Copying IRQ routing tables to 0xf0000...done. Wrote linuxbios table at: 00000500 - 0000066c checksum 8a04 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 (cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: 0x0000000000008789 Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417 Jumping to boot code ROM segment 0x0000 length 0x0000 reloc 0x0000 Etherboot 5.0.6 (GPL) ELF for [SIS900] Boot from (N)etwork or from (L)ocal? clocks_per_tick = 784464 N I am now initializing the ide system init_drive sectors_per_track = [63], num_heads = [16],num_cylinders=[16383], num_sectors = [117231408] LBA mode supported Boot: (hd0,0)/kernel part=[0], part_start=[0x0000003f, 63] valid partition: current_slice [131] (ELF)... done Unknown bootloader class! type=0x000101C0 data=0x000103BE Firmware type: LinuxBIOS 0 LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS.LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 booting... Finding PCI configuration type. PCI: Using configuration type 1 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 0, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 0, Superio SiS 950 handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 0, done #0 handle_superio done Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1039/0730] PCI: 00:00.1 [1039/5513] PCI: 00:01.0 [1039/0008] PCI: 00:01.1 [1039/0900] PCI: 00:01.2 [1039/7001] PCI: 00:01.3 [1039/7001] PCI: 00:01.4 [1039/7018] PCI: 00:01.6 [1039/7013] PCI: 00:02.0 [1039/0001] PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1039/6300] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done totalram: 120M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB Setting variable MTRR 1, base: 64MB, range: 32MB, type WB Setting variable MTRR 2, base: 96MB, range: 16MB, type WB Setting variable MTRR 3, base: 112MB, range: 8MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : AuthenticAMD Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x08 Processor Mask : 0x00 Processor Stepping : 0x00 Feature flags : 0x0183f9ff MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] mem PCI: 00:00.1 10 <- [0x00002c90 - 0x00002c93] io PCI: 00:00.1 14 <- [0x00002ca0 - 0x00002ca3] io PCI: 00:00.1 18 <- [0x00002cb0 - 0x00002cb3] io PCI: 00:00.1 1c <- [0x00002cc0 - 0x00002cc3] io PCI: 00:00.1 20 <- [0x00002c80 - 0x00002c8f] io PCI: 00:01.1 10 <- [0x00002000 - 0x000020ff] io PCI: 00:01.1 14 <- [0xfc100000 - 0xfc100fff] mem PCI: 00:01.2 10 <- [0xfc101000 - 0xfc101fff] mem PCI: 00:01.3 10 <- [0xfc102000 - 0xfc102fff] mem PCI: 00:01.4 10 <- [0x00002400 - 0x000024ff] io PCI: 00:01.4 14 <- [0xfc103000 - 0xfc103fff] mem PCI: 00:01.6 10 <- [0x00002800 - 0x000028ff] io PCI: 00:01.6 14 <- [0x00002c00 - 0x00002c7f] io PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 ÿÿÿÿÿÿio PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 ÿÿÿÿÿÿprefmem PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 ÿÿÿÿÿÿmem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io Allocating VGA resource done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 07 PCI: 00:00.1 cmd <- 01 PCI: 00:01.0 cmd <- 0c PCI: 00:01.1 cmd <- 03 PCI: 00:01.2 cmd <- 02 PCI: 00:01.3 cmd <- 02 PCI: 00:01.4 cmd <- 03 PCI: 00:01.6 cmd <- 01 PCI: 00:02.0 cmd <- 27 PCI: 01:00.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized Enabled in SIS 503 regs 0x40 and 0x45 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 1, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 1, done #0 handle_superio done PCCHIPS M810LMR (and similar)...Entering the initregs process Southbridge fixup done for SIS 503 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 2, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call finishup handle_superio Pass 2, done #0 handle_superio done Copying IRQ routing tables to 0xf0000...done. Wrote linuxbios table at: 00000500 - 0000066c checksum 8a04 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 (cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: 0x0000000000008789 Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417 Jumping to boot code ROM segment 0x0000 length 0x0000 reloc 0x0000 Etherboot 5.0.6 (GPL) ELF for [SIS900] Boot from (N)etwork or from (L)ocal? clocks_per_tick = 784576 N I am now initializing the ide system init_drive sectors_per_track = [63], num_heads = [16],num_cylinders=[16383], num_sectors = [117231408] LBA mode supported Boot: (hd0,0)/kernel part=[0], part_start=[0x0000003f, 63] valid partition: current_slice [131] (ELF)... done Unknown bootloader class! type=0x000101C0 data=0x000103BE Firmware type: LinuxBIOS

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keyboard enable
by gonzapata＠vtr.net 01 Feb '03

01 Feb '03

Hi, I wanna know if there is a parameter for the config file of linuxbios to active the keyboard, everything works fine except that i don't have keyboard. Thanx Gonzalo Zapata

3 2

APM support in linuxbios.
by sivakumar 30 Jan '03

30 Jan '03

Hi, When I was reading a document about the APM, it is mentioned that we need to have BIOS support to have APM on the machine. Also it is mentioned that if the BIOS is not properly supported it will lead the APM to crash the system. So I want to know about APM support in the case of LINUXBIOS. Can any one help me out? Also yesterday I have downloaded the latest code of the Linuxbios. Still now I was working with old source base from sourceforge.net. After compiling with the new code, I found some new file like c_start.s and linuxbios_c.*. what I have to do with these file? Thanks, Siva -- sivakumar <sivakumar.subramani(a)wipro.com> wipro

4 3

BIOS replacement Intel '486
by Richard Bonomo 29 Jan '03

29 Jan '03

Hello! I am working with a Real Time Devices PC-104 standard system equipped with a '486DX processor, and. In order to decrease boot time to our OS (which is QNX/Neutrino) I would like to eliminate the BIOS, replacing it with my own code which does minimal initialization, and then loads the OS immediately (the OS is not dependent on BIOS calls). If anyone who has done this sort of thing before is willing to spend a few minutes on the telephone with me, I'd be most appreciative. Roy Minnich of LANL appears willing, but he is out for a number of days. Thank you. Richard B. P.S. please reply direct. -- ************************************************ Richard Bonomo UW Space Astronomy Laboratory ph: (608) 263-4683 telefacsimile: (608) 263-0361 SAL-related email: bonomo(a)sal.wisc.edu all other email: bonomo(a)ece.wisc.edu web page URL: http://www.cae.wisc.edu/~bonomo ************************************************

1 0

keyboard problem
by Paulo Richards 29 Jan '03

29 Jan '03

Hi, i finally succeeded burning the DoC, with linuxbios and my custom kernel, loading the root file system on hda1.. it works almost perfect, but i can't get keyboard working, I searched on the web, but i found nothing useful (i made what Antony Stone wrote on his guide, but still don't work), I don't Know if is problem of the kernel or my linuxbios configuration. Any idea how can i fix it? There are attached the linuxbios and kernel configs files, if you want to take a look, please tell me if anything is missing or are something wrong. Thanks Paulo Richards PD: i'm working with a pcchips 810lmr

1 0

Re: [fb-d] (no subject)
by ebiederman＠lnxi.com 29 Jan '03

29 Jan '03

"JAson Hensler" <omegadraconis(a)insight.rr.com> writes: > Hey, > I'm i was wondering if the i440 bx chipsets are supported. Yes, there are motherboards using the 440bx chipset in the tree. > My mb is an asus pbp. I have 256ram(read as only 128 for some > reason) and am looking to clear this problem up thanks, Dig into the code and have fun. The primary discussion list is linuxbios(a)clustermatic.org Eric

1 0

sdram on board
by daniel＠dmhome.net 29 Jan '03

29 Jan '03

I am trying to get an embedded pc board to run with linuxbios. The board is an arbor emcore6352 and is (almost) identical to the technoland sbc710 from the CVS tree. The onboard ethernet is an intel chipset however, and the cpu is a low power pentium iii. * Linuxbios is coming up and so is the kernel. The pirq table however, is not successfully copied to 0xf0000, or so the debuging message tells me. Ethernet and usb both have irq zero assigned in linux ... Any tips where I can start looking? * The other thing , is that the board has it's sdram (128mb) soldered on the pcb, and there's no serial eeprom to read the stuff that usually comes from the smbus. So far the only way to get linuxbios to come up is to plug in extra sdram(in an sodimm socket) that DOES have the usual serial eeprom to do spd. I have the datasheets of the sdram components, so I guess it's a matter of hardcoding the information about those chips somewhere? Could you please give me a hint as to where would be the best place to insert this code into the source tree? Or any useful links about (basics) of sdram initialization, since I am a total newbie with this stuff. Thanks

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coreboot January 2003