coreboot December 2002

coreboot@coreboot.org

45 participants
68 discussions

gcc 2.96 != gcc 2.96
by Ronald G. Minnich 08 Dec '02

08 Dec '02

gcc 2.96 on redhat 8.0 compiles linuxbios just fine. gcc 2.96 on redhat 7.3 gets an error on that pirq change I made recently. I have now put in, tested, and committed the following patch, let me know if this helps: #if GCC_VERSION < 3000 struct irq_info slots[1]; #else struct irq_info slots[]; #endif Compiles now on my redhat 7.3 ron

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RE: Booting from floppy
by Phil Brooks 06 Dec '02

06 Dec '02

We are interested in using LinuxBIOS on our medical system, running the Digital Logic P5 PC-104 SBC. After reading these posts, and scanning the FAQ, I am confused about boot methods: Will LinuxBIOS work on a stand-alone system with a EIDE disk? If floppy boot won't be supported, can it boot from cdrom? Thanks very much, Phil Brooks Phil Brooks - Software Engineer Olympic Medical 206-268-5119 philb(a)olymed.com -----Original Message----- From: Ronald G. Minnich [mailto:rminnich@lanl.gov] Sent: Friday, December 06, 2002 2:21 PM To: Big Pilot Cc: adam(a)cfar.umd.edu; linuxbios(a)clustermatic.org Subject: Re: Booting from floppy On Fri, 6 Dec 2002, Big Pilot wrote: > > So there are two issues: a) DOS isn't supported and b) the floppy as a > boot device isn't supported. That will make it a very difficult sell for > mobo manufacturers. Can you imagine me buying a Linux PC with LinuxBIOS > and it crashing. How am I going to repair it then? floppies are dead. What's wrong with a cdrom boot? ron _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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Booting from floppy
by Big Pilot 06 Dec '02

06 Dec '02

I'm wondering whether it is still possible to boot DOS (or a free equivalent) from a floppy if LinuxBIOS is installed on the mobo. Also, if Linux fails, how is one supposed to repair it? Or is the only option booting Linux off a floppy and repairing using that? -- ______________________________________________ http://www.linuxmail.org/ Now with POP3/IMAP access for only US$19.95/yr Powered by Outblaze

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Re: VIA EPIA - Status
by Andrew Ip 06 Dec '02

06 Dec '02

Oliver, > i just want to check, what is the status of the epia port? AFAIK, Kelvin has fixed the irq problem by changing IDE mode, and he will send a patch to us once he has cleaned up the code. I'll also look into it again some time next week. -Andrew -- Andrew Ip Email: aip(a)cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.

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VIA EPIA - Status
by OliverArnold＠via.com.tw 05 Dec '02

05 Dec '02

hello ng, i just want to check, what is the status of the epia port? oliver

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2.4.19 and sparse e820 map
by Ronald G. Minnich 05 Dec '02

05 Dec '02

The first problem is this: BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000000bcc (reserved) BIOS-e820: 0000000000000bcc - 00000000000a0000 (usable) BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved) BIOS-e820: 0000000000100000 - 0000000020000000 (usable) BIOS-e820: 0000000100000000 - 0000000120000000 (usable) 3712MB HIGHMEM available. 896MB LOWMEM available. those MEM numbers are quite bogus. The second problem is that it can't find the initrd in the image. On a good load the initrd is at 2000a000 i.e. 512MB+some, and that puts it on this mem right at memory that doesn't exist. I think it is getting confused early in the game and ending up with an initrd somewhere bogus. ron

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linux 2.4.19 and E820 problems CONFIRMED
by Ronald G. Minnich 05 Dec '02

05 Dec '02

I have just confirmed that 2.4.19 won't work at all with the memory split. I set remap_high to disable in cmos and the node is now workig correctly. I think I'm going to have a CONFIG option to disable this completely, since if it gets turned on accidently I have an unbootable node. Comments? ron

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common flash hw write enable methods
by Andrew Kohlsmith 04 Dec '02

04 Dec '02

So I've got linuxbios booting inside Bochs and I feel I'm confident enough to roll the dice and burn it to a real board (TSSOP package, no sockets) using /dev/bios. After some head-scratching, I realize that the hardware RP# and VPP are tied together, and at a logic low, preventing any flash attempts. These are pins 10 and 11 on the TSSOP part. :-( Now I imagine that these are tied to a MOSFET to +12V which is run off of a GPIO pin. The question is, without tracing an 8-layer board out to try and identify how exactly reflash is enabled, how to reflash this? I can always cut the traces and hard-wire to +12V but I'd like to see if I can't do this programmatically. I have a number of boards I want to use and hardware hacking is something I'd like to avoid doing if possible. Now I know that every motherboard is different and that there may be other things locking me out, but generally speaking is there an "industry standard" way of enabling/disabling BIOS reflash? It's currently a PhoenixBIOS, so I imagine if I located a reflash tool and ran it in a Bochs session with a lot of I/O debugging I could figure out what it's doing but before I embark on that I'd like to see if anyone has any hints that may save me a lot of time. Regards, Andrew

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question on e7500 sizeram
by Ronald G. Minnich 04 Dec '02

04 Dec '02

freebios/src/northbridge/intel/E7500/northbridge.c In this file there is a variable called remap_high. I assume the function of this is to remap the high memory (512MB) so it is contiguous with the low 512MB. Even when remap_high is true, on -current, I end up with two 512MB segemnts, one at 0 and one at 4 GB. Anybody have any idea as to why this would happen? It's confusing 2.4.19 from what I can see. ron

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Re: Question regarding instructions...
by Nathanael Noblet 04 Dec '02

04 Dec '02

Hello again, So I ordered 6 of the flash chips and got a PLCC removal tool. I'm ready to start getting this working on my machine. I am still unclear as to the steps to proceed in order to do that. I have looked at the tiara source, there seems to be quite a bit there so that is promising. Where I become confused is where to put my code and such, how to break it up. Looking at making a Config file, it says to set the target (for example winfast) does that mean I need to make my own for arbor (maker of this SBC)? and then all the mainboard/model stuff as well. How do I know where everything is to go? Are there any docs relating to how to proceed to get all the devices setup and placement of files. There seems to be quite a few directories with nothing in them and that is confusing as well. I have the output of lspci -vvvv and the datasheet for the sis530 that is the chipset on this board. I don't see anything similar to the superio chips that seem to be related to the other sis boards etc... So basically I'm wondering: 1) What are the basic things I need to implement / create to get linuxbios up and compiled etc.. 2) Is there anything that better explains the directory/file structure of the source tree? a) if there isn't, then how can I determine what to put where? I think that is it for now. Thanks for the help so far, this is exciting, I hope to be able to help the project out by getting LinuxBIOS on one more box, albeit a somewhat older one (but good for embedded development). :) -- Nathanael Noblet Gnat Solutions 4604 Monterey Ave NW Calgary, AB T3B 5K4 T/F 403.288.5360 C 403.809.5368 http://www.gnat.ca/

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coreboot December 2002