coreboot November 2002

coreboot@coreboot.org

65 participants
108 discussions

Peculiar behavor during the build process for the l440gx port
by Gregg C Levine 17 Nov '02

17 Nov '02

Hello from Gregg C Levine I am getting some darned strange error messages from the Python based builder script. It seems to reject the way the config file is setup, in favor of something totally different. Well I tried that. It did not work. So, I setup a shell script file to automate some of the steps. And with the exact same config file, as the one I've attached, I ended up with the exact same output from the scripting output. Even thiough the output is provided as a an attachment, I am going to paste it here: Script started on Sun Nov 17 17:49:12 2002 root@drwho:/usr/src/lobos/work# ./buildit.sh Process config file: /usr/src/lobo/freebios/src/mainboard/intel/l440gx/Config ===> Warning: /usr/src/lobos/work/l440gx.config:4: /usr/src/lobo/freebios/src/mainboard/intel/l440gx/Config not found Will place Makefile, crt0.S, etc. in /usr/src/lobos/work/l440gx-build/l440gx /usr/src/lobos/work/l440gx.config:10: arch, target, or mainboard must be the first commands, not option root@drwho:/usr/src/lobos/work# exit Script done on Sun Nov 17 17:49:30 2002 -------------------------------------------------------- And here is the l440gx config file: ---- # This will make a target directory of ./winfast # Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE # CONFIG TOOL. Make it absolute if you like mainboard intel/l440gx target /usr/src/lobos/work/l440gx-build/l440gx # Enable Serial Console for debugging # It will come up at 115200,8n1 option SERIAL_CONSOLE =1 # Enable MicroCode update and L2 Cache init for PII and PIII option UPDATE_MICROCODE=1 option CONFIGURE_L2_CACHE=0 # Use the internal VGA frame buffer device #option HAVE_FRAMEBUFFER option USE_CACHE_RAM=0 option USE_GENERIC_ROM=1 option USE_ELF_BOOT=1 #makedefine PHLASH_BASE_NAME=p13-0125 #makedefine BOOT_IMAGE=/tftpboot/netboot.ebi makedefine BOOT_IMAGE=vmlinux.bin.gz.block # Path to your kernel (vmlinux) # NOTE; you need a path to your test12 kernel here. #linux ~/projects/linux/linux-2.4.0-test9.eb5.4 linux /usr/src/linux-2.4.17 # Kernel command line parameters commandline ro panic=5 root=/dev/hda1 console=ttyS0,115200 debug 3 ----------------------------------------- What "Config" file is it talking about? This is on Slackware 8.0, with the current collection of tools, as of when Slackware 8.0 was released. And I am open to suiggestions. Gregg C Levine drwho8(a)worldnet.att.net "Oh my!" The Second Doctor's nearly favorite phrase.

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overflowed source buffer ... segment exceeding memory
by Bill Rugolsky Jr. 15 Nov '02

15 Nov '02

I'm still trying to get LinuxBIOS booting on my Tyan S2462 board, and encountering some problems. This is with mkelfImage-1.17, binutils 2.13.90.0.2, etherboot-5.1.0.eb1, and LinuxBIOS from CVS. [ Building the LinuxBIOS CVS tree requires: perl -ni -e 'print if !/secondary\.inc/' src/mainboard/tyan/guiness/Config perl -pi -e 's/w832627hf/w83627hf/' src/mainboard/tyan/guiness/mainboard.c ] What I've done is produce a "normal" and a "fallback" romimage, catenated them together, and written the whole 512kB to the flash chip. [ At first glance I couldn't grok the whole fallback logic. ] Normal: option USE_FALLBACK_IMAGE=0 option ROM_SIZE=524288 option ROM_IMAGE_SIZE=65536 Fallback: option USE_FALLBACK_IMAGE=1 option ROM_SIZE=524288 option ROM_IMAGE_SIZE=45056 I tried several kernels with/without ramdisk; same results. At this point the sun was coming up and it was time to go to work. :-/ The boot log follows. Regards, Bill Rugolsky ==== LinuxBIOS-1.0.0 Wed Nov 13 00:17:27 EST 2002 starting... LinuxBIOS-1.0.0 Wed Nov 13 00:17:27 EST 2002 booting... Finding PCI configuration type. handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e Scanning PCI bus...done Allocating PCI resources...done. Enabling PCI resourcess...done. Initializing PCI devices... PCI devices initialized totalram: 1024M Initializing CPU #1 Enabling cache...done. Setting up local apic...done. CPU #1 Initialized clocks_per_usec: 1152 Initializing CPU #0 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Enabling cache...done. Setting up local apic...done. CPU #0 Initialized handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 Searching for 16 byte tags 63:rom_read_bytes() - overflowed source buffer. max_block = 0 init_bytes found 0 tags ROM segment 0x0000 length 0x0000 reloc 0x9400 clocks_per_tick = 753184 Etherboot 5.1.0.eb1 (GPL) ELF (Multiboot) for [3C90X] Boot from (N)etwork or from (L)ocal? N Found 3Com980-Cyclone at 0x1C00, ROM address 0x0000 Probing...[3C90X] The PCI BIOS has not enabled this device! Updating PCI command 0003->0007. pci_bus 0000 pci_device_fn 0078 3C90X Driver 2.00 Copyright 1999 LightSys Technology Services, Inc. Portions Copyright 1999 Steve Smith Provided with ABSOLUTELY NO WARRANTY. ------------------------------------------------------------------------------- MAC Address = 00:E0:81:03:4A:31 Connectors present: 10Base-T / 100Base-TX. Searching for server (DHCP)... -\Me: 192.168.0.251, Server: 192.168.0.1, Gateway 192.168.0.1 Loading 192.168.0.1:kernel |/-(ELF)... No base memory found assuming 640K segment exceeding memory Unable to load file. <sleep> <abort> Issuing RESET: Boot from (N)etwork or from (L)ocal? N Found 3Com980-Cyclone at 0x1C00, ROM address 0x0000 Probing...[3C90X] 3C90X Driver 2.00 Copyright 1999 LightSys Technology Services, Inc. Portions Copyright 1999 Steve Smith Provided with ABSOLUTELY NO WARRANTY. ------------------------------------------------------------------------------- MAC Address = 00:E0:81:03:4A:31 Connectors present: 10Base-T / 100Base-TX. Searching for server (DHCP)... \|/-\|/Me: 192.168.0.251, Server: 192.168.0.1, Gateway 192.168.0.1 Loading 192.168.0.1:kernel -\|/(ELF)... segment exceeding memory Unable to load file. <sleep> <abort> Issuing RESET: Boot from (N)etwork or from (L)ocal? N Found 3Com980-Cyclone at 0x1C00, ROM address 0x0000 Probing...[3C90X]

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ide problem with pcm-5823
by Andrew Ip 15 Nov '02

15 Nov '02

Does any see the following errors? hdc is unusable. ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx CS5530: IDE controller on PCI bus 00 dev 92 CS5530: chipset revision 0 CS5530: not 100% native mode: will probe irqs later ide0: BM-DMA at 0x1800-0x1807, BIOS settings: hda:pio, hdb:pio ide1: BM-DMA at 0x1808-0x180f, BIOS settings: hdc:pio, hdd:pio hda: C/H/S=0/0/0 from BIOS ignored hda: LEAD DATA, ATA DISK drive hda: cs5530_set_xfer_mode(PIO 1) hda: set_drive_speed_status: status=0x51 { DriveReady SeekComplete Error } hda: set_drive_speed_status: error=0x04 { DriveStatusError } hdc: SanDisk SDCFB-16, ATA DISK drive hdc: IRQ probe failed (0xfef8) hdc: cs5530_set_xfer_mode(PIO 0) hdc: set_drive_speed_status: status=0x51 { DriveReady SeekComplete Error } hdc: set_drive_speed_status: error=0x04 { DriveStatusError } ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 ide1 at 0x170-0x177,0x376 on irq 15 (serialized with ide0) hda: 64000 sectors (33 MB) w/0KiB Cache, CHS=1000/16/4 hdc: 31360 sectors (16 MB) w/1KiB Cache, CHS=490/2/32 Partition check: hda: hda1 hdc:hdc: lost interrupt hdc: lost interrupt hdc: lost interrupt hdc: lost interrupt hdc: lost interrupt hdc: lost interrupt hdc: lost interrupt hdc: lost interrupt hdc: lost interrupt hdc: lost interrupt [PTBL] [15/32/63] hdc1 -Andrew -- Andrew Ip Email: aip(a)cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.

3 4

Check the status page.
by Ronald G. Minnich 15 Nov '02

15 Nov '02

The table there is perl-generated. ron

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change coming.
by Ronald G. Minnich 15 Nov '02

15 Nov '02

As per my note from last night on the PIIX4E, I am going to move the SMBUS and PM base address assignment from the l440gx mainboard code to the piix4e southbridge code so that all platforms do the right thing. I'll let you know how it goes. ron

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[COMMIT] pirq_routing.c
by Andrew Ip 15 Nov '02

15 Nov '02

freebios/src/arch/i386/lib/pirq_routing.c - Added verification of the copy of pirq routing table. -Andrew -- Andrew Ip Email: aip(a)cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.

6 23

status tool committed
by Ronald G. Minnich 14 Nov '02

14 Nov '02

util/buildstatus/buildstatus.pl It's a trivial tool that makes use of trivial perl features (maximum portability ... we've had perl portability problems on this project) to build a web page. Comments welcome. But I don't want mods that make use of tricky perl or html code. There is a reason I didn't use perl objects. now we all need to get our STATUS files up to date ... thanks ron

1 0

STATUS file
by Ronald G. Minnich 14 Nov '02

14 Nov '02

Thanks to you (all two of you) who have started filling in the STATUS files. How do I know you did this? Because the first cut of the tool is working. And the web site is down, I see, we're working on it. Hopefully, tomorrow, the status page goes up. If not, then next week. I will commit the tool source in a bit. ron

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proposed change to piix4e RFC
by Ronald G. Minnich 14 Nov '02

14 Nov '02

I note the following code in src/mainboard/intel/l440gx/mainbard.c printk_debug("enabling smbus\n"); #if 0 smbus_io = NewPciIo(0x10); #else smbus_io = 0xFFF0; #endif pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */ pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */ pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */ printk_debug("enable pm functions\n"); #if 0 pm_io = NewPciIo(0x40); #else pm_io = 0xFF80; #endif pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */ pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */ This code sets the base addresses of the piix4e smbus and PM to reasonable values < 0x1000. This would fix a problem I have had on the smartcore p5, where the PM and SMBUS were getting mapped to 0x1000 and 0x1040 in early assembly startup, and the PCI was starting I/O allocation at 0x1000, with the result that some I/O devices did not work correctly -- their I/O was preempted by the piix4e SMBUS and PM I/O. A question to this group: Doesn't it make more sense to put this code in the piix4e/southbridge.c file? The way it is now, some mainboards get fixed but others don't. Is there a problem with doing this? Unless this causes trouble I would like to move this chunk of code so that all boards that use the piix4e can benefit from it. thanks ron

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Re: Compact Flash (fwd)
by Eugen Leitl 14 Nov '02

14 Nov '02

---------- Forwarded message ---------- Date: Thu, 14 Nov 2002 06:59:52 -0800 From: R/db <daryl.bunce(a)attws.com> Reply-To: wear-hard(a)haven.org To: wear-hard(a)haven.org Subject: Re: Compact Flash Resent-Date: Thu, 14 Nov 2002 10:02:09 -0500 Resent-From: wear-hard(a)haven.org Try http://noflushd.sourceforge.net/ Love it. Been running with this and without swap for well over a year. Ignore the message that it thinks another noflushd is running. Also, check the recent Linux Kernel ml on CONFIG_TINY - good stuff about getting rid of swap. >From the site: This is noflushd, a daemon that spins down disks that have not been read from after a certain amount of time, and then prevents disk writes from spinning them back up. It's for use with kernel versions 2.2.11 and up, where the userland bdflush (update) daemon has been fully integrated in the new kernel thread kupdated (formerly known as kupdate). noflushd uses the sleep support logic from bdflush-1.6.2. bdflush was originally written by Eric Youngdale, Pavel Machek added the sleep support. On Thu, Nov 14, 2002 at 09:29:27AM -0500, McCarty, Paul wrote: > Why can't we just tweak the linux kernel a little to do more aggressive > disk caching? Or make use of RAM disks to keep things off the disk until > we want to save things? for wearable applications compact disk space is > more expensive then RAM: <rest deleted>

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coreboot November 2002