coreboot December 2011

coreboot@coreboot.org

34 participants
174 discussions

#95: Run coreboot in VirtualBox
by coreboot 10 Dec '14

10 Dec '14

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+---------------… [View More]

2 8

EHCI debug port finder
by Carl-Daniel Hailfinger 30 May '14

30 May '14

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, … [View More]

5 13

New patch to review: 49493f5 T60: add volume CMOS setting
by gerrit＠coreboot.org 28 Jan '13

28 Jan '13

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12 -gerrit

6 10

#131: New flashrom motherboard support
by coreboot 18 Sep '12

18 Sep '12

#131: New flashrom motherboard support ---------------------------------+------------------------------------------ Reporter: anonymous | Owner: somebody Type: enhancement | Status: new Priority: trivial | Milestone: Going mainstream Component: flashrom | Version: v2 Keywords: flashrom asus | Dependencies: Patchstatus: there is no patch | --… [View More]

1 15

Re: [coreboot] how to delete symbol link created at compile time
by She, Kerry 18 Jul '12

18 Jul '12

> -----Original Message----- > From: Marc Jones [mailto:marcj303@gmail.com] > Sent: Tuesday, October 18, 2011 10:39 AM > To: Stefan Reinauer > Cc: She, Kerry; coreboot > Subject: Re: [coreboot] how to delete symbol link created at compile time > > On Mon, Oct 17, 2011 at 4:44 PM, Stefan Reinauer > <stefan.reinauer(a)coreboot.org> wrote: > > * Marc Jones <marcj303(a)gmail.com> [111016 10:10]: > >> >> > I have created 2 devicetree … [View More]file : > >> >> > > >> >> > devicetree_f15.cb for platform with family 15 CPU > >> >> > > >> >> > devicetree_f10.cb for platform with family 10 CPU > >> >> > > >> >> > > >> >> > > >> >> > I changed the makefile to create a symbol link "devicetree.cb" > link to > >> >> > devicetree_f10.cb or devicetree_f15.cb at compile time. > >> >> > > >> >> > The problem is that I can't delete the symbol link when make > >> >> > clean/distclean. > >> > > >> > Please fix the problem by using one device tree for both platforms. > > > >> Stefan, > >> > >> Can you explain your thoughts on how that would work? Can we put a #if > >> in the devicetree.cb? It uses the c precompiler? It requires different > >> CPU files/device locations. We can try it next week. > > > > Usually the way this is handled in coreboot is that there is one socket > > that binds together all CPU types. Then in the device tree only the > > socket type is specified, and code for both CPUs is pulled in. > > Maybe we need something like a socket for northbridge code, since the > > northbridge now lives in the CPU? > > > > It seems like a bad idea to have to recompile your BIOS because you > > change the CPU. We did a lot of nastyness with K8 and Fam10, but we > > should find a better way to do this for future chipsets/CPUs. > > > Yes, we are discussing how the AGESA code would work. The socket > decision is rather complicated as we need a way to handle multiple > calls with the same names (function point tables etc). I think that > there may be a solution within AGESA, but the device tree may still be > a problem as the CPUs have different HT link numbering. This makes it > hard to have the same device tree layout for the same socket. Because of the function name conflict, put cpu code of 2 families together would not compile. We need to dig into AGESA more to figure out a solution. As for the devicetree problem, following text is the devicetree difference in detail: --- devicetree_fam10.cb 2011-08-15 15:00:14.426692437 +0800 +++ devicetree_fam15.cb 2011-08-15 15:00:14.426692437 +0800 @@ -16,19 +16,17 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -chip northbridge/amd/agesa/family10/root_complex +chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on - chip cpu/amd/agesa/family10 - device lapic 0x10 on end + chip cpu/amd/agesa/family15 + device lapic 0x20 on end end end device pci_domain 0 on subsystemid 0x15d9 0xab11 inherit #SuperMicro - chip northbridge/amd/agesa/family10 # CPU side of HT root complex - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on end # link 2 - device pci 18.0 on # link 3, SB on socket0 link 2, on internal Node0 Link 3 + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on end # Link 0 + device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1) chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 [View Less]

2 4

#135: Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E)
by coreboot 24 Mar '12

24 Mar '12

#135: Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E) ---------------------------------+------------------------------------------ Reporter: Jan@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ------------… [View More]

1 11

Set top box update
by Gregg Levine 11 Mar '12

11 Mar '12

Hello! Amazon tells me that there are now two people selling their Akimbo boxes. Perhaps I'll definitely buy one. And Joe here is the linked page which contains a reference to the STB kit from Intel: http://cerberus.teamhackaday.com/?p=3 It turns out that it comes up right below the description for the device. It seems the only thing nonstandard about it is the crappy BIOS that Akimbo insisted on. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

2 2

flaschip (and compatibles)
by Oliver Schinagl 22 Feb '12

22 Feb '12

Hey list, I want (in the far? future) play with coreboot on my new board, an Asus M5A97 (900 series amd chipset) thing. Having it not even build into my case yet, I was wondering if you guys know what a compatible flash chip is. I have an 8 legged little socketable chip on here, with the following markings: MXIC b111376-12G MX25L3206EPI 3F204500 So far I found the best results from google with the MX25L3206EPI labeling but the few links I got where mostly in chinese and the datasheet … [View More]

4 8

FOSDEM 2012
by Carl-Daniel Hailfinger 29 Jan '12

29 Jan '12

Hey, it seems we forgot to apply for a devroom (well, at least I didn't see anything on the mailing list). Should we submit talks to the individual devrooms? Should we ask for a coreboot/flashrom booth/table? Regards, Carl-Daniel

2 3

tiny bootblock problem
by Nils 05 Jan '12

05 Jan '12

Hi all, I was updating some old patches to get them ready for inclusion and tested latest coreboot trunk. (first time with tiny bootblock) My geode GX2 target does boot, but it takes 30 seconds to load fallback/coreboot_ram . Is that a caching problem introduced by tiny bootblock? What is needed to get it right? Thanks, Nils.

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coreboot December 2011