Anyone with detailed knowledge of (or more manuals than I have for) the Opteron,
I just noticed that the Nvidia ck804 reduces the amount of credits which the Opteron gives it (probably due to an errata.) Does that mean that there should be more credits available for the other HT links? Is buffer space per link or does the CPU share it all between all the links? What if a link is disabled? Should you give its credits to the others?
In the BKDG for the Opteron it says that you shouldn't change the values in general, because software picks the right values, but that's us. It doesn't say how you should pick new values.
Thanks, Myles
Myles Watson wrote:
Anyone with detailed knowledge of (or more manuals than I have for) the Opteron,
I just noticed that the Nvidia ck804 reduces the amount of credits which the Opteron gives it (probably due to an errata.) Does that mean that there should be more credits available for the other HT links? Is buffer space per link or does the CPU share it all between all the links? What if a link is disabled? Should you give its credits to the others?
In the BKDG for the Opteron it says that you shouldn't change the values in general, because software picks the right values, but that's us. It doesn't say how you should pick new values.
Myles,
I assume that you are talking about the XBAR buffer allocation, 4.6.12? The links are profiled by the designers and then appropriate values are assigned. There are some limitations in allocating the buffers so you can't just take some form one place an use it somewhere else. For the most part, you shouldn't run out of buffers in a typical system, so nothing would be gained by adding more to a particular interface.
Generally, we should set what the factory bios sets since those settings are validated. If a customer is building their own platforms we will work with them to set appropriate values for their silicon.
Marc
-----Original Message----- From: Marc Jones [mailto:marc.jones@amd.com] Sent: Thursday, July 17, 2008 4:28 PM To: Myles Watson Cc: 'Coreboot' Subject: Re: [coreboot] HT credits and the Opteron
Myles Watson wrote:
Anyone with detailed knowledge of (or more manuals than I have for) the Opteron,
I just noticed that the Nvidia ck804 reduces the amount of credits which
the
Opteron gives it (probably due to an errata.) Does that mean that there should be more credits available for the other HT links? Is buffer
space
per link or does the CPU share it all between all the links? What if a
link
is disabled? Should you give its credits to the others?
In the BKDG for the Opteron it says that you shouldn't change the values
in
general, because software picks the right values, but that's us. It
doesn't
say how you should pick new values.
Myles,
Marc,
Thanks for the quick response.
I assume that you are talking about the XBAR buffer allocation, 4.6.12?
Sorry. I should have been more clear. I was talking about 3.3.15: LDTi Buffer Count Registers. Does your answer still apply?
The links are profiled by the designers and then appropriate values are assigned. There are some limitations in allocating the buffers so you can't just take some form one place an use it somewhere else. For the most part, you shouldn't run out of buffers in a typical system, so nothing would be gained by adding more to a particular interface.
Generally, we should set what the factory bios sets since those settings are validated. If a customer is building their own platforms we will work with them to set appropriate values for their silicon.
Now that there is an open-source HT core from the University of Mannheim, anyone could do this, but maybe most people will leave it alone.
Thanks, Myles
Myles Watson wrote:
I assume that you are talking about the XBAR buffer allocation, 4.6.12?
Sorry. I should have been more clear. I was talking about 3.3.15: LDTi Buffer Count Registers. Does your answer still apply?
I am looking at the public BKDG Publication # 32559 Revision: 3.08 draft Issue Date: July 2007.
The LDTi buffers(4.3.15) are part of the XBAR buffers (4.6.10).
"4.3.15 LDTi Buffer Count Registers These registers specify the number of command and data buffers for each virtual channel available for use by the transmitter at the other end of the specific HyperTransport™ technology link. See “XBAR Flow Control Buffers” on page 156 for more information on command and data buffers. Note: The reset values for each of the LDTn Buffer Count registers depend on the link connection type (coherent HyperTransport or noncoherent HyperTransport technology). Because hardware attempts to choose optimal settings, this register should not, in general, need to be changed."
Now that there is an open-source HT core from the University of Mannheim, anyone could do this, but maybe most people will leave it alone.
The core should still be profiled by the designers and recommended values documented by them. If none are given than I would assume that it is optimized to work with the default settings.
Marc
-
Marc Jones -
Myles Watson