the following patch was just integrated into master: commit c939c3d9957c2a3c7a6619815374520226f7f78d Author: Duncan Laurie dlaurie@chromium.org Date: Tue Jul 10 15:15:41 2012 -0700
ME: Move ME v8 lockdown to finalize step
The ME device was being sent EOP and the PCI device hidden during coreboot so it was not available in the SMI finalize step.
This also flips the PCI vendor/device dword around for the match.
Boot on Panther Point with serial and SMI debugging enabled and see that ME EOP message is sent and the device is hidden at end of U-boot and before the kernel loads.
Finalizing Coreboot
SMI# #0 ME: mkhi_end_of_post ME: END OF POST message successful (0) PM1_STS: TMROF PM1_EN: 120
Starting kernel ...
Change-Id: I230038c62c50db2a1c94078c0a2a67bdc232440e Signed-off-by: Duncan Laurie dlaurie@chromium.org
Build-Tested: build bot (Jenkins) at Wed Jul 25 02:58:44 2012, giving +1 Reviewed-By: Ronald G. Minnich rminnich@gmail.com at Thu Jul 26 20:31:12 2012, giving +2 See http://review.coreboot.org/1338 for details.
-gerrit