Hi all,
Can someone advise on how logical/physical processors are numbered for Ivy Bridge CPUs?
I am hoping to build coreboot with hyper-threading (SMT) disabled. I guess this can be done by skipping over the right processor IDs in the for loop in intel_cores_init in src/cpu/intel/model_206ax/model_206ax_init.c:470 ?
But do I skip over odd numbers? even numbers? Or are the extra threads at the end of the sequence?
Best regards, Davíð
Hi Davíð,
On 13.01.2018 15:34, Davíð Steinn Geirsson wrote:
I am hoping to build coreboot with hyper-threading (SMT) disabled. I guess this can be done by skipping over the right processor IDs in the for loop in intel_cores_init in src/cpu/intel/model_206ax/model_206ax_init.c:470 ?
no, you can't just ignore (logical) cores there. I suppose they would still be visible to the OS but not functional.
It seems the PCH is supposed to tell the CPU package after reset how many (logical) cores should be enabled. There is a register to override the settings: SOFT_RESET_DATA. Setting bit 0 in that register + a reset should disable hyper-threading.
Though, this register is already used in set_flex_ratio_to_tdp_nominal() in `src/cpu/intel/model_206ax/bootblock.c`.
You can check if hyper-threading is enabled by looking at MSR 0x35 (CORE_THREAD_COUNT) or CPUID (eax 0x0b, ecx 0x00 / 0x01). Both should be documented in Intel's SDM [1].
You should combine the decision to disable HT with the already present code for the flex ratio. If any of the two settings need to change, program SOFT_RESET_DATA accordingly and perform a reset.
Hope that helps, Nico
On 13.01.2018 17:13, Nico Huber wrote:
You can check if hyper-threading is enabled by looking at MSR 0x35 (CORE_THREAD_COUNT) or CPUID (eax 0x0b, ecx 0x00 / 0x01). Both should be documented in Intel's SDM [1].
Forgot the link: [1] https://software.intel.com/en-us/articles/intel-sdm
Thanks Nico, this info is very helpful. I now know where to start reading.
Best regards, Davíð
On Sat, Jan 13, 2018 at 05:13:01PM +0100, Nico Huber wrote:
Hi Davíð,
On 13.01.2018 15:34, Davíð Steinn Geirsson wrote:
I am hoping to build coreboot with hyper-threading (SMT) disabled. I guess this can be done by skipping over the right processor IDs in the for loop in intel_cores_init in src/cpu/intel/model_206ax/model_206ax_init.c:470 ?
no, you can't just ignore (logical) cores there. I suppose they would still be visible to the OS but not functional.
It seems the PCH is supposed to tell the CPU package after reset how many (logical) cores should be enabled. There is a register to override the settings: SOFT_RESET_DATA. Setting bit 0 in that register + a reset should disable hyper-threading.
Though, this register is already used in set_flex_ratio_to_tdp_nominal() in `src/cpu/intel/model_206ax/bootblock.c`.
You can check if hyper-threading is enabled by looking at MSR 0x35 (CORE_THREAD_COUNT) or CPUID (eax 0x0b, ecx 0x00 / 0x01). Both should be documented in Intel's SDM [1].
You should combine the decision to disable HT with the already present code for the flex ratio. If any of the two settings need to change, program SOFT_RESET_DATA accordingly and perform a reset.
Hope that helps, Nico
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