Hi all,
Is there any documentation around describing how coreboot scans for PCI Express buses and devices?
I have an expansion module for the Intense PC I'd like to get working with Coreboot. The expansion module adds 4 Intel Gigabit Ethernet interfaces (82574L) via PCI Express 4 PCIe ports. All interfaces are on the same physical FACE module.
In the vendor firmware, all four cards are properly detected: 01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 03:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 06:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 07:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
But in coreboot, only the first two cards are detected: 01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 03:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
It seems from the coreboot uart output that coreboot isn't scanning PCIe buses 6 & 7. Looking at pci_scan_bus in src/device/pci_device.c it seems coreboot should be recursively scanning PCI bridges for any devices behind them. The lspci output from the vendor firmware and coreboot lists the same number of PCI bridges: 00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09) 00:01.1 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09)
From the boot logs, it seems that coreboot stops scanning after PCI bus 05:
PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [8086/10d3] enabled Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L0s and L1 Failed to enable LTR for dev = PCI: 01:00.0 scan_bus: scanning of bus PCI: 00:01.0 took 18672 usecs PCI: pci_scan_bus for bus 02 scan_bus: scanning of bus PCI: 00:01.1 took 2609 usecs PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/10d3] enabled ... PCI: pci_scan_bus for bus 05 PCI: 05:00.0 [10ec/8168] enabled Enabling Common Clock Configuration ASPM: Enabled L1 Failed to enable LTR for dev = PCI: 05:00.0 scan_bus: scanning of bus PCI: 00:1c.2 took 14395 usecs scan_bus: scanning of bus PCI: 00:1f.0 took 2 usecs scan_bus: scanning of bus PCI: 00:1f.3 took 2 usecs scan_bus: scanning of bus DOMAIN: 0000 took 222594 usecs scan_bus: scanning of bus Root Device took 231592 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 238973 exit 0 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. Done reading resources.
I grepped in src/ but couldn't find where the min/max PCI bus IDs are set.
Given that these work with the vendor firmware, and they appear to be on buses above what coreboot normally initializes (at least from my log output), I'm wondering how I can force coreboot to continue scanning/initializing PCIe buses above bus 05.
Thanks, Hal