Patch set updated for coreboot: 64f465a Add an option to keep the ROM cached after romstage
Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/739
-gerrit
commit 64f465a0154da1e425c5ef09f93662eab746cf4d Author: Stefan Reinauer reinauer@chromium.org Date: Wed Nov 2 16:12:34 2011 -0700
Add an option to keep the ROM cached after romstage
Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer reinauer@google.com --- src/arch/x86/include/arch/acpi.h | 4 +++- src/cpu/x86/Kconfig | 4 +++- src/cpu/x86/lapic/Makefile.inc | 1 + src/cpu/x86/lapic/boot_cpu.c | 3 ++- src/cpu/x86/mtrr/mtrr.c | 14 +++++++++++++- src/include/cpu/x86/lapic.h | 4 ++++ 6 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 030745d..504d71b 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr);
int acpi_get_sleep_type(void); - +#else +#define acpi_slp_type 0 #endif
/* northbridge/amd/amdfam10/amdfam10_acpi.c */ @@ -434,6 +435,7 @@ void generate_cpu_entries(void); #else // CONFIG_GENERATE_ACPI_TABLES
#define write_acpi_tables(start) (start) +#define acpi_slp_type 0
#endif
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 348f0ef..fdbd527 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -39,4 +39,6 @@ config LOGICAL_CPUS bool default y
- +config CACHE_ROM + bool + default n diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index af20956..f3fcadc 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -2,3 +2,4 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +ramstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index 87418d0..0fb9d5d 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,7 +1,8 @@ +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h>
#if CONFIG_SMP -static int boot_cpu(void) +int boot_cpu(void) { int bsp; msr_t msr; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 46d8e2d..9015ad4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,9 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <arch/acpi.h>
#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; @@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = { MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, };
- void enable_fixed_mtrr(void) { msr_t msr; @@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) while(var_state.reg < MTRRS) { set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } + +#if CONFIG_CACHE_ROM + /* Enable Caching and speculative Reads for the + * complete ROM now that we actually have RAM. + */ + if (boot_cpu() && (acpi_slp_type != 3)) { + set_var_mtrr(7, (4096-4)*1024, 4*1024, + MTRR_TYPE_WRPROT, address_bits); + } +#endif + printk(BIOS_SPEW, "call enable_var_mtrr()\n"); enable_var_mtrr(); printk(BIOS_SPEW, "Leave %s\n", __func__); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 8b44a6c..016870d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -1,6 +1,7 @@ #ifndef CPU_X86_LAPIC_H #define CPU_X86_LAPIC_H
+#ifndef __ROMCC__ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> #include <arch/hlt.h> @@ -156,4 +157,7 @@ int start_cpu(struct device *cpu);
#endif /* !__PRE_RAM__ */
+int boot_cpu(void); +#endif + #endif /* CPU_X86_LAPIC_H */
-
Stefan Reinauer