Patch set updated for coreboot: 84a6f2f Added RAMINIT_SYSINFO and declared the necessary structs
Oskar Enoksson (enok@lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/236
-gerrit
commit 84a6f2f02377a6d4e2b6ae4d058255199eaff77a Author: Oskar Enoksson enok@lysator.liu.se Date: Tue Oct 4 22:15:51 2011 +0200
Added RAMINIT_SYSINFO and declared the necessary structs
Functionality should be as before, but more clean/safe declaration through struct mb_sysconf_t. It's more consistent with other MB's and I've tested it thoroughly on my DL145. This is a second change-attempt, without any style fixes or other unrelated changes.
Signed-off-by: Oskar Enoksson enok@lysator.liu.se Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be --- src/mainboard/hp/dl145_g1/Kconfig | 1 + src/mainboard/hp/dl145_g1/get_bus_conf.c | 52 ++++++++++++---------------- src/mainboard/hp/dl145_g1/irq_tables.c | 19 +++------- src/mainboard/hp/dl145_g1/mb_sysconf.h | 20 +++++++++++ src/mainboard/hp/dl145_g1/mptable.c | 36 +++++++------------ src/mainboard/hp/dl145_g1/romstage.c | 55 +++++++++++++++++------------- 6 files changed, 94 insertions(+), 89 deletions(-)
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index eb90b07..ebd7ffd 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO # select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index e4721ce..a951328 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -10,19 +10,12 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h>
+#include "mb_sysconf.h"
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default -unsigned char bus_8131_0 = 1; -unsigned char bus_8131_1 = 2; -unsigned char bus_8131_2 = 3; -unsigned char bus_8111_0 = 1; -unsigned char bus_8111_1 = 4; -unsigned apicid_8111 ; -unsigned apicid_8131_1; -unsigned apicid_8131_2; - -unsigned pci1234x[] = +struct mb_sysconf_t mb_sysconf; + +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -34,7 +27,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -45,8 +38,6 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned sbdn3; -
static unsigned get_bus_conf_done = 0; @@ -63,6 +54,9 @@ void get_bus_conf(void)
get_bus_conf_done = 1;
+ sysconf.mb = &mb_sysconf; + struct mb_sysconf_t *m = sysconf.mb; + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; @@ -72,36 +66,36 @@ void get_bus_conf(void) get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - sbdn3 = sysconf.hcdn[0] & 0xff; + m->sbdn3 = sysconf.hcdn[0] & 0xff;
- bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; - bus_8111_0 = bus_8131_0; + m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; + m->bus_8111_0 = m->bus_8131_0;
/* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0); }
/* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0)); if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0); }
/* 8132-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0); }
@@ -111,7 +105,7 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + m->apicid_8111 = apicid_base+0; + m->apicid_8131_1 = apicid_base+1; + m->apicid_8131_2 = apicid_base+2; } diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index b53a992..24fc9be 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -11,6 +11,7 @@ #include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h> +#include "mb_sysconf.h"
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, @@ -30,23 +31,13 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev pirq_info->rfu = rfu; }
-extern unsigned char bus_8131_0; -extern unsigned char bus_8131_1; -extern unsigned char bus_8131_2; -extern unsigned char bus_8111_0; -extern unsigned char bus_8111_1; - -extern unsigned sbdn3; - - - unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; uint8_t *v; + struct mb_sysconf_t *m = sysconf.mb;
uint8_t sum=0; int i; @@ -66,7 +57,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_8111_0; + pirq->rtr_bus = m->bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
pirq->exclusive_irqs = 0; @@ -81,10 +72,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge -// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// write_pirq_info(pirq_info, m->bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++;
pirq_info++; slot_num++; diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h new file mode 100644 index 0000000..0bceab4 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h @@ -0,0 +1,20 @@ +#ifndef MB_SYSCONF_H + +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_8131_0; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_0; + unsigned char bus_8111_1; + + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2; + + unsigned sbdn3; +}; + +#endif + diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 3cd9fd6..20bf30f 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -5,17 +5,7 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdk8_sysconf.h> - -extern unsigned char bus_8131_0; -extern unsigned char bus_8131_1; -extern unsigned char bus_8131_2; -extern unsigned char bus_8111_0; -extern unsigned char bus_8111_1; -extern unsigned apicid_8111; -extern unsigned apicid_8131_1; -extern unsigned apicid_8131_2; - -extern unsigned sbdn3; +#include "mb_sysconf.h"
static void *smp_write_config_table(void *v) { @@ -30,31 +20,33 @@ static void *smp_write_config_table(void *v)
get_bus_conf();
+ struct mb_sysconf_t *m = sysconf.mb; + mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base); + smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base); } } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base); + smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base); } }
}
- mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0); + mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
// // The commented-out lines are auto-detected on my servers. @@ -66,18 +58,18 @@ static void *smp_write_config_table(void *v) //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); // Integrated AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); // On board ATI Rage XL //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); // On board Broadcom nics - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); // On board LSI SCSI //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
// PCIX-133 Slot - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index f51b4c4..c0a12d9 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -1,17 +1,17 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> +#include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/amdk8.h" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/early_serial.c" @@ -55,7 +55,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); } while ((ret!=0) && (i-->0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); }
@@ -77,6 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); }
+#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -86,8 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c"
-#define RC0 ((1<<1)<<8) // Not sure about these values -#define RC1 ((1<<2)<<8) // Not sure about these values +#define RC0 ((1<<1)<<8) +#define RC1 ((1<<2)<<8)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -101,13 +101,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) RC1|DIMM1, RC1|DIMM3, 0, 0, #endif }; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset = 0; + unsigned bsp_apicid = 0;
if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -115,47 +116,53 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + setup_dl145g1_resource_map(); //setup_default_resource_map();
- needs_reset = setup_coherent_ht_domain(); - - wait_all_core0_started(); +#if CONFIG_MEM_TRAIN_SEQ == 1 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram +#endif + setup_coherent_ht_domain(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif
- needs_reset |= ht_setup_chains_x(); + ht_setup_chains_x(sysinfo);
- if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + }
enable_smbus();
int i; for(i=0;i<2;i++) { - activate_spd_rom(&ctrl[i]); + activate_spd_rom(&sysinfo->ctrl[i]); } - for(i=2;i<8;i<<=1) { + for(i=RC0;i<=RC1;i<<=1) { change_i2c_mux(i); }
- //dump_spd_registers(&ctrl[0]); - //dump_spd_registers(&ctrl[1]); + //dump_spd_registers(&sysinfo->ctrl[0]); + //dump_spd_registers(&sysinfo->ctrl[1]); //dump_smbus_registers();
allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes(); //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
memreset_setup(); - sdram_initialize(nodes, ctrl); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
//dump_pci_devices();
-
Oskar Enoksson