Intel i855pm northbridge

[Vincent Legoll]

Hello,

I'm trying to understand i855pm code, and reading reset_test.c, I see:
#define MCH_DRC 0x70

whereas the 252613.pdf I downloaded from intel web site, at:
http://www.intel.com/Assets/PDF/datasheet/252613.pdf
"Intel(R) 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet"
revision 003, page 71, has the following:

3.7.20. DRC – DRAM Controller Mode Register – Device #0
Offset:             7C-7Fh
Default:            1000_0001h
Access:             Read/Write
Size:               32 bits

So what am I missing in the 0x70h versus 0x7Ch difference ?

Could someone please gently enlighten me ?

[Uwe Hermann]

On Sun, Oct 05, 2008 at 01:27:01AM +0200, Vincent Legoll wrote:
> I'm trying to understand i855pm code, and reading reset_test.c, I see:
> #define MCH_DRC 0x70
>
> whereas the 252613.pdf I downloaded from intel web site, at:
> http://www.intel.com/Assets/PDF/datasheet/252613.pdf
> "Intel(R) 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet"
> revision 003, page 71, has the following:
>
> 3.7.20. DRC – DRAM Controller Mode Register – Device #0
> Offset:             7C-7Fh
> Default:            1000_0001h
> Access:             Read/Write
> Size:               32 bits
>
> So what am I missing in the 0x70h versus 0x7Ch difference ?
>
> Could someone please gently enlighten me ?

Looks like a typo to me, I guess in the code, but it could also be in
the datasheet.

Be careful with the 855pm code though, I think it's unfinished and
possibly never ever worked. If you really plan to add support for some
newer Intel chipsets (which is not a small project mind you), I'd start
with the i3100 code, which is in good shape quality-wise and has been
confirmed working on hardware.

Uwe.

[Corey Osgood]

On Sat, Oct 4, 2008 at 8:44 PM, Uwe Hermann  wrote:
> On Sun, Oct 05, 2008 at 01:27:01AM +0200, Vincent Legoll wrote:
> > I'm trying to understand i855pm code, and reading reset_test.c, I see:
> > #define MCH_DRC 0x70
> >
> > whereas the 252613.pdf I downloaded from intel web site, at:
> > http://www.intel.com/Assets/PDF/datasheet/252613.pdf
> > "Intel(R) 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz
>
> Datasheet"
> > revision 003, page 71, has the following:
> >
> > 3.7.20. DRC – DRAM Controller Mode Register – Device #0
> > Offset:             7C-7Fh
> > Default:            1000_0001h
> > Access:             Read/Write
> > Size:               32 bits
> >
> > So what am I missing in the 0x70h versus 0x7Ch difference ?
> >
> > Could someone please gently enlighten me ?
>
> Looks like a typo to me, I guess in the code, but it could also be in
> the datasheet.
>
> Be careful with the 855pm code though, I think it's unfinished and
> possibly never ever worked.

My understanding is that it's mostly a straight copy of and old version of
i440bx that was somewhat fixed up but never completed. I'd avoid it like the
plague. I'm pretty sure I requested removing it at one point, but it must
have been shot down.

-Corey
> If you really plan to add support for some
> newer Intel chipsets (which is not a small project mind you), I'd start
> with the i3100 code, which is in good shape quality-wise and has been
> confirmed working on hardware.
> Uwe.
>
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

[Vincent Legoll]

On Sun, Oct 5, 2008 at 2:44 AM, Uwe Hermann  wrote:
> > So what am I missing in the 0x70h versus 0x7Ch difference ?
> >
> > Could someone please gently enlighten me ?
>
> Looks like a typo to me, I guess in the code, but it could also be in
> the datasheet.
>
> Be careful with the 855pm code though, I think it's unfinished and
> possibly never ever worked. If you really plan to add support for some
> newer Intel chipsets (which is not a small project mind you), I'd start
> with the i3100 code, which is in good shape quality-wise and has been
> confirmed working on hardware.

I looked at the other intel northbridges, and this certainly looks more like
a typo than anything else now. For example the 7501 has the 0x7Ch
from its datasheet... No other intel northbridge seem to have a
reset_test()...

I've already understood that I'll need more than i855pm, for example
it's single channel RAM...

Thanks for the i3100 hint, btw

[Stefan Reinauer]

Vincent Legoll wrote:
> Hello,
>
> I'm trying to understand i855pm code

Don't! That code never worked.

There's a version on the mailing list some years ago that works with one
ram configuration on one mainboard. But it was never merged.

Stefan