PIRQ checksum drama

[John Usher (Maptek)]

G'day all...

I am currently having trouble with the irq_tables.c produced by getpir.

I am receiving the following error from the linuxbios boot:

Checking IRQ routing
tables.../root/aug2002/lb/freebios/src/arch/i386/lib/pirq_routing.c:
24:check_pirq_routing_table() - irq_routing_table located at: 0x0000b0c0
/root/aug2002/lb/freebios/src/arch/i386/lib/pirq_routing.c:
31:check_pirq_routing_table() - checksum is: 0x26 but should be: 0x7a
/root/aug2002/lb/freebios/src/arch/i386/lib/pirq_routing.c:
49:check_pirq_routing_table() - checksum error in irq routing table
done.
Copying IRQ routing tables to 0xf0000...done.

As can be seen from irq_tables.c, the checksum internally is 0x26, and
getpir did not report any errors when it downloaded the table. Does
anyone have any ideas?

John...

irq_tables.c follows:

/* This file was generated by getpir.c, do not modify! 
   (but if you do, please run checkpir on it to verify)
   Contains the IRQ Routing Table dumped directly from your memory ,
wich BIOS sets up

Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/

#include <arch/pirq_routing.h>

const struct irq_routing_table intel_irq_routing_table = {
    PIRQ_SIGNATURE, /* u32 signature */
    PIRQ_VERSION,   /* u16 version   */
    32+16*8,        /* there can be total 8 devices on the bus */
    0,           /* Where the interrupt router lies (bus) */
    0x38,           /* Where the interrupt router lies (dev) */
    0xe00,         /* IRQs devoted exclusively to PCI usage */
    0x8086,         /* Vendor */
    0x7000,         /* Device */
    0,         /* Crap (miniport) */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
    0x26,         /*  u8 checksum , this hase to set to some value
that would give 0 after the sum of all bytes for this structure
(including checksum) */
    {
    	{0,0x48, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62,
0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0},
    	{0,0x50, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63,
0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0},
    	{0,0x58, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60,
0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0},
    	{0,0x60, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61,
0xdeb8}, {0x62, 0xdeb8}}, 0x4, 0},
    	{0,0x68, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60,
0xdeb8}, {0x61, 0xdeb8}}, 0x5, 0},
    	{0,0x70, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63,
0xdeb8}, {0x60, 0xdeb8}}, 0x6, 0},
    	{0,0x39, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62,
0xdeb8}, {0x63, 0xdeb8}}, 0, 0},
    	{0,0x8, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8},
{0x63, 0xdeb8}}, 0, 0},
    }
};