This little series fixes various bugs and annoyances in coreboot and coreboot64.
With this both coreboot and coreboot64 start up and work reasonably well on Brya (x86 Chromebook) and U-Boot can boot common Linux distros.
- Make coreboot64 debug UART start reliably - Avoid the long USB-init delay on startup - Correct the timer speed on coreboo64 - Fix a bootstd cros bug (will likely be squashed into another patch) - Fix the terribly slow console scrolling
With v2 I have also brought in some lost x86 patches so they are all in one series.
Changes in v2: - Update the malloc size too - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch - Add new patch
Simon Glass (20): x86: coreboot: Add IDE and SATA x86: coreboot: Enable standard boot x86: coreboot: Rearrange arch_cpu_init() x86: Set the CPU vendor in SPL x86: Allow APCI in SPL x86: coreboot: Look for DBG2 UART in SPL too x86: coreboot: Enable CONFIG_SYS_NS16550_MEM32 x86: coreboot: Drop USB init on startup x86: coreboot: Align options between coreboot and coreboot64 x86: coreboot: Enable VIDEO_COPY efi: x86: Correct the condition for installing ACPI tables x86: smbios: Add a Kconfig indicating SMBIOS-table presence x86: Record the position of the SMBIOS tables efi: x86: Use the installed SMBIOS tables efi: x86: Install the SMBIOS tables if present x86: coreboot: Record the position of the SMBIOS tables x86: doc: Move into its own directory x86: doc: Update summaries and add links x86: doc: Split out manual booting into its own file x86: doc: coreboot: Mention 64-bit Linux distros
arch/x86/cpu/coreboot/coreboot.c | 16 +- arch/x86/cpu/x86_64/cpu.c | 7 + arch/x86/dts/coreboot.dts | 1 + arch/x86/include/asm/global_data.h | 1 + arch/x86/lib/coreboot/cb_sysinfo.c | 1 + arch/x86/lib/tables.c | 3 + configs/coreboot64_defconfig | 25 +-- configs/coreboot_defconfig | 21 +- doc/arch/index.rst | 2 +- doc/arch/x86/index.rst | 12 ++ doc/arch/x86/manual_boot.rst | 276 +++++++++++++++++++++++++++ doc/arch/{ => x86}/x86.rst | 295 ++--------------------------- doc/board/coreboot/coreboot.rst | 38 +++- drivers/serial/Kconfig | 2 +- drivers/video/coreboot.c | 12 ++ include/asm-generic/global_data.h | 8 + lib/Kconfig | 20 +- lib/efi_loader/Makefile | 4 +- lib/efi_loader/efi_setup.c | 20 +- lib/efi_loader/efi_smbios.c | 37 +--- 20 files changed, 447 insertions(+), 354 deletions(-) create mode 100644 doc/arch/x86/index.rst create mode 100644 doc/arch/x86/manual_boot.rst rename doc/arch/{ => x86}/x86.rst (64%)
Add these options to permit access to more disk types.
Add some documentation as well.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v1)
configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 9 +++++++++ doc/board/coreboot/coreboot.rst | 20 ++++++++++++++++++++ 3 files changed, 30 insertions(+)
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 8aadaa68c279..ded0e6f2422d 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 8e11de663819..56cc542df6c6 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -22,8 +22,10 @@ CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y +CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -48,6 +50,13 @@ CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_SYS_IDE_MAXDEVICE=4 +CONFIG_SYS_ATA_DATA_OFFSET=0 +CONFIG_SYS_ATA_REG_OFFSET=0 +CONFIG_SYS_ATA_ALT_OFFSET=0 +CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_NVME_PCI=y # CONFIG_PCI_PNP is not set CONFIG_SOUND=y diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index d660a223d9c8..be5b0de5495e 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -41,6 +41,26 @@ At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This works correctly for link though.
+You can run via QEMU using:: + + qemu-system-x86_64 -bios build/coreboot.rom -serial mon:stdio + +The `-serial mon:stdio` part shows both output in the display and on the +console. It is optional. You can add `nographic` as well to *only* get console +output. + +To run with a SATA drive called `$DISK`:: + + qemu-system-x86_64 -bios build/coreboot.rom -serial mon:stdio \ + -drive id=disk,file=$DISK,if=none \ + -device ahci,id=ahci \ + -device ide-hd,drive=disk,bus=ahci.0 + +Then you can scan it with `scsi scan` and access it normally. + +To use 4GB of memory, typically necessary for booting Linux distros, add +`-m 4GB`. + 64-bit U-Boot -------------
Enable bootstd options and provide instructions on how to boot a linux distro using coreboot.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v1)
configs/coreboot64_defconfig | 14 ++------------ configs/coreboot_defconfig | 1 + doc/board/coreboot/coreboot.rst | 16 ++++++++++++++-- 3 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index ded0e6f2422d..602465175d20 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -10,40 +10,30 @@ CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_SYS_MONITOR_BASE=0x01120000 CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_CMD_SOUND=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y # CONFIG_SPL_MAC_PARTITION is not set # CONFIG_SPL_DOS_PARTITION is not set -CONFIG_ISO_PARTITION=y -CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 56cc542df6c6..735cd6eb4c22 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -10,6 +10,7 @@ CONFIG_TARGET_COREBOOT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_SYS_MONITOR_BASE=0x01110000 CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index be5b0de5495e..88437c27740e 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -67,9 +67,21 @@ To use 4GB of memory, typically necessary for booting Linux distros, add In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This produces an image which can be booted from coreboot (32-bit). Internally it works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It -can be useful for running UEFI applications, for example. +can be useful for running UEFI applications, for example with the coreboot +build in `$CBDIR`:: + + DISK=ubuntu-23.04-desktop-amd64.iso + CBDIR=~/coreboot/build + + cp $CBDIR/coreboot.rom.in coreboot.rom + cbfstool coreboot.rom add-flat-binary -f u-boot-x86-with-spl.bin \ + -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000 + + qemu-system-x86_64 -m 2G -smp 4 -bios coreboot.rom \ + -drive id=disk,file=$DISK,if=none \ + -device ahci,id=ahci \ + -device ide-hd,drive=disk,bus=ahci.0 \
-This has only been lightly tested.
CBFS access -----------
Init errors in SPL are currently ignored by this function.
Change the code to init the CPU, reporting an error if something is wrong. After that, look for the coreboot table.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v1)
arch/x86/cpu/coreboot/coreboot.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d7eedbd7436e..a0c62cce2293 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -20,7 +20,14 @@
int arch_cpu_init(void) { - int ret = get_coreboot_info(&lib_sysinfo); + int ret; + + ret = IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() : + x86_cpu_init_f(); + if (ret) + return ret; + + ret = get_coreboot_info(&lib_sysinfo); if (ret != 0) { printf("Failed to parse coreboot tables.\n"); return ret; @@ -28,8 +35,7 @@ int arch_cpu_init(void)
timestamp_init();
- return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() : - x86_cpu_init_f(); + return 0; }
int checkcpu(void)
If coreboot does not set up sysinfo for the UART, SPL currently hangs. Use the DBG2 teechnique there as well. This allows coreboot64 to boot from coreboot even if the console info is missing from sysinfo
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v1)
configs/coreboot64_defconfig | 1 + drivers/serial/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 602465175d20..a094a7c24234 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -55,4 +55,5 @@ CONFIG_SYS_64BIT_LBA=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_SPL_ACPI=y # CONFIG_GZIP is not set diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a1e089962a91..01100b6d93f3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -672,7 +672,7 @@ config COREBOOT_SERIAL config COREBOOT_SERIAL_FROM_DBG2 bool "Obtain UART from ACPI tables" depends on COREBOOT_SERIAL - default y if !SPL + default y help Select this to try to find a DBG2 record in the ACPI tables, in the event that coreboot does not provide information about the UART in the
The debug UART on modern machines uses a 32-bit wide transfer. Without this, setting debug output causes a hang or no output. It is not obvious (when enabling CONFIG_DEBUG_UART) that this is needed.
Enable 32-bit access to avoid this trap.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v1)
configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index a094a7c24234..29b68d6929c7 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 735cd6eb4c22..2961908f29cd 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -60,6 +60,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_NVME_PCI=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5
This is very annoying as it is quite slow on many machines. Also, U-Boot has an existing 'preboot' mechanism to enable this feature if desired.
Drop this code so that it is possible to choose whether to init USB or not.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v1)
arch/x86/cpu/coreboot/coreboot.c | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index a0c62cce2293..fa3daeff8229 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -82,10 +82,6 @@ static void board_final_init(void)
int last_stage_init(void) { - /* start usb so that usb keyboard can be used as input device */ - if (IS_ENABLED(CONFIG_USB_KEYBOARD)) - usb_init(); - board_final_init();
return 0;
These two builds are similar but have some different options for not good reason. Line them up to be as similar as possible.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Update the malloc size too
configs/coreboot64_defconfig | 7 +++++++ configs/coreboot_defconfig | 9 --------- 2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 29b68d6929c7..2263554a47ce 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -1,5 +1,6 @@ CONFIG_X86=y CONFIG_TEXT_BASE=0x1120000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="coreboot" @@ -18,6 +19,9 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_LOG=y +CONFIG_LOGF_LINE=y +CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_SPL_NO_BSS_LIMIT=y @@ -51,10 +55,13 @@ CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y +CONFIG_NVME_PCI=y # CONFIG_PCI_PNP is not set CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_SPL_ACPI=y +CONFIG_CMD_DHRYSTONE=y # CONFIG_GZIP is not set +CONFIG_SMBIOS_PARSER=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 2961908f29cd..790b84a87bc7 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -25,23 +25,14 @@ CONFIG_LAST_STAGE_INIT=y CONFIG_PCI_INIT_R=y CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_CMD_SOUND=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y
At least on modern machines the write-back mechanism for the frame buffer is quite slow when scrolling, since it must read the entire frame buffer and write it back.
Enable the VIDEO_COPY feature to resolve this problem.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v1)
arch/x86/dts/coreboot.dts | 1 + configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + drivers/video/coreboot.c | 12 ++++++++++++ 4 files changed, 15 insertions(+)
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index f9ff5346a79b..0eb31cae42c1 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -42,6 +42,7 @@ };
coreboot-fb { + bootph-some-ram; compatible = "coreboot-fb"; }; }; diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 2263554a47ce..e5546dadcb0a 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -60,6 +60,7 @@ CONFIG_NVME_PCI=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y +CONFIG_VIDEO_COPY=y CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_SPL_ACPI=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 790b84a87bc7..78694d635532 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -54,6 +54,7 @@ CONFIG_NVME_PCI=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y +CONFIG_VIDEO_COPY=y CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_CMD_DHRYSTONE=y # CONFIG_GZIP is not set diff --git a/drivers/video/coreboot.c b/drivers/video/coreboot.c index c586475e41ed..5b718ae3e5a5 100644 --- a/drivers/video/coreboot.c +++ b/drivers/video/coreboot.c @@ -73,6 +73,17 @@ err: return ret; }
+static int coreboot_video_bind(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + /* Set the maximum supported resolution */ + uc_plat->size = 4096 * 2160 * 4; + log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + + return 0; +} + static const struct udevice_id coreboot_video_ids[] = { { .compatible = "coreboot-fb" }, { } @@ -82,5 +93,6 @@ U_BOOT_DRIVER(coreboot_video) = { .name = "coreboot_video", .id = UCLASS_VIDEO, .of_match = coreboot_video_ids, + .bind = coreboot_video_bind, .probe = coreboot_video_probe, };
Make a note of where coreboot installed the SMBIOS tables so that we can pass this on to EFI.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add new patch
arch/x86/lib/coreboot/cb_sysinfo.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c index dfbc80c430e1..f7fd9ea5bcbb 100644 --- a/arch/x86/lib/coreboot/cb_sysinfo.c +++ b/arch/x86/lib/coreboot/cb_sysinfo.c @@ -471,6 +471,7 @@ int get_coreboot_info(struct sysinfo_t *info) return -ENOENT; gd->arch.coreboot_table = addr; gd_set_acpi_start(map_to_sysmem(info->rsdp)); + gd_set_smbios_start(info->smbios_start); gd->flags |= GD_FLG_SKIP_LL_INIT;
return 0;
Add a little more detail as to why coreboot64 is preferred for booting Linux distros.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add new patch
doc/board/coreboot/coreboot.rst | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index 88437c27740e..a32c3a864f90 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -82,6 +82,8 @@ build in `$CBDIR`:: -device ahci,id=ahci \ -device ide-hd,drive=disk,bus=ahci.0 \
+This allows booting and installing various distros, many of which are +64-bit-only, so cannot work with the 32-bit 'coreboot' build.
CBFS access -----------
Hi,
On Thu, 17 Aug 2023 at 18:27, Simon Glass sjg@chromium.org wrote:
This little series fixes various bugs and annoyances in coreboot and coreboot64.
With this both coreboot and coreboot64 start up and work reasonably well on Brya (x86 Chromebook) and U-Boot can boot common Linux distros.
Please ignore the references to coreboot64 as that is a U-Boot build, not a coreboot one.
I did not mean to send this series to the coreboot mailing list. Unfortunately I have a 'coreboot' alias in my setup now and it picked up the tags from these commits, I have renamed the alias.
Sorry for the confusion.
Regards, Simon
[..]
-
Simon Glass