Hello, I'm currently working on enabling PEG and run into some trouble. With pending patches [1] applied, I was able to activate the Nvidia GPU. The system hangs at Seabios/Grub2 with 2 GPUs enabled at the same time. As I'm using the EHCI Debug Port I don't have any Seabios console output. Is there EHCI Debug Port support available ? My first guess is some VGA IO ranges are overlapping. Any ideas whats wrong ?
Do I need to provide two VBIOS blobs ? At the moment it is only possible to provide one (using make menuconfig). The ACPI code "parses" the IGD VBIOS, do I need to add similar code for PEG ?
It looks like to best idea is to disable one GPU depending on a user setting. I would like to see a new define: PREFER_PEG_OVER_IGD If set and PEG and IGD are found, IGD is disabled. If unset and PEG and IGD are found, PEG is disabled.
Some UEFI allows to run both GPUs. Running multiple GPUs at the same time seems to be possible, but requires additional testing.
Regards, Patrick
[1] http://review.coreboot.org/#/c/11058/ http://review.coreboot.org/#/c/11059/
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On 08/11/2015 02:05 AM, Patrick Rudolph wrote:
Hello, I'm currently working on enabling PEG and run into some trouble. With pending patches [1] applied, I was able to activate the Nvidia GPU. The system hangs at Seabios/Grub2 with 2 GPUs enabled at the same time. As I'm using the EHCI Debug Port I don't have any Seabios console output. Is there EHCI Debug Port support available ? My first guess is some VGA IO ranges are overlapping. Any ideas whats wrong ?
Legacy VGA I/O ranges cannot overlap by design. All legacy VGA I/O and memory accesses will be routed to one and only one device (the "primary" display controller).
It is possible that coreboot is becoming confused as to which GPU to route legacy access to. Look in your coreboot log for lines similar to these:
found VGA at PCI: 01:00.0 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
That will give more information as to what is actually happening.
Do I need to provide two VBIOS blobs ? At the moment it is only possible to provide one (using make menuconfig). The ACPI code "parses" the IGD VBIOS, do I need to add similar code for PEG ?
Yes, you need two blobs if the GPUs require different ROMs. However, only one VBIOS is actually used -- one of the option ROMs is only used to initialize the secondary GPU, while the other initializes the primary GPU and sets up the VBIOS.
There's more to this topic to be sure, but hopefully this will point you in the right direction. I have tested multiple nVidia cards under coreboot at this point (discrete cards on AMD boards) without too many issues, but watch your overall BAR allocations as with two GPUs active you may exceed coreboot's allocator limits (coreboot does not have support for 64-bit prefetchable BARs at this time).
- -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com
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Patrick Rudolph -
Timothy Pearson