VIA EDEN ESP (C3) + Apollo CLE266(VT8623) + VT8237R + W83627HG - coreboot

7 Dec 2009


      I am working on setting up CoreBoot Compulab's CM-iVCF 
computer-on-module. It's essentially like an EPIA-MS board 
(http://www.ewayco.com/20-low-cost-embedded-epia-mini-itx-etc-boards/epia-ms-...) 
but with a WinBond super-IO. I'm aware this is rather old board, but the 
chipset combination has been popular in various embedded projects, and 
it looks like porting CoreBoot on EPIA-MS has come up on this list from 
time to time. Has anybody got this combination working with CoreBoot, 
still working on it, or have general tips on it?
Presently, my main problem seems to be that the 
northbridge/via/vt8623/raminit.h does not define a mem_controller struct 
required by the southbridge code, so the north- and southbridge code 
don't seem to be clearly delimited. My code does compile if I use the 
northbridge/via/cn400/raminit.h definition instead, but not surprisingly 
there's no output on the console. The website seems to have few pointers 
on debugging.
Chip markings on the board I'm working with:
CPU: Eden ESP 10K (133X7.5)1.05V SET BWT6E-0610
Northbridge: CLE266 0610CE
Southbridge: VT8237R 0551CD
WinBond Super-IO: W83627HG-AW
DDR memory: Hynix 515A HY5DU121622BT-J
In addition there's at least W311H clock-generator and W255H DDR2 clock 
buffer.
Here's the main() I'm using, which is a combination the EPIA-M (vt8623 + 
vt8235 + vt1211) and EPIA-N (cn400 + vt8237r + w83697hf) code:
static void main(unsigned long bist)
{
    unsigned long x;
    device_t dev;
/* Enable multifunction for northbridge. */
// Not using cn400 northbridge
//    pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
    console_init();
print_spew("In auto.c:main()\r\n");
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
    report_bist_failure(bist);
print_debug("Enabling mainboard devices\r\n");
    enable_mainboard_devices();
print_debug("Enable F-ROM Shadow RAM\r\n");
    enable_shadow_ram();
/* setup cpu */
// This doesn't appear in EPIA-M, probably northbridge specific
//    print_debug("Setup CPU Interface\r\n");
//    c3_cpu_setup(ctrl.d0f2);
//    ddr_ram_setup();
    ddr_ram_setup((const struct mem_controller *)0);
if (bist == 0) {
        print_debug("doing early_mtrr\r\n");
        early_mtrr_init();
    }
//ram_check(0, 640 * 1024);
print_spew("Leaving auto.c:main()\r\n");
}