On Sun, 29 Dec 2002, Andrew Kohlsmith wrote:
Actually that brings up a few questions I had about
the 430TX chipset
support in LinuxBIOS... The DRAM initialization seems to be utterly
mangled, with Eric's code winning out (since it seems to work. :-) --
but I have seen a few register initializations which I haven't been able
to find in my 430TX documentation.
it's a mess, due to 430tx bugs and problems and doc errors, and the fact
that the chipset is seeing so little use nowadays that almost nobody
cares. But a clean implementation would still be of interest.
Things like register 0x90 (in raminit.inc it's
called "Error Control
Register") and using eight read cycles to reset either the memory or the
controller, I'm not sure... Does anyone have any recollection of where this
type of information was found?
trial and error and error and error and ... until it worked. Then we
stopped and moved on to other things and never got back to it.
If I do a (fairly large) cleanup of the 430TX ram init
code, would it be
accepted into CVS or is it how it is for specific reasons?
If it doesn't break anything like the smartcore-p5 we'll take it.