[LinuxBIOS] [patch 0/4] AMD Geode LX support for LinuxBIOS

[Marc Jones]

Hello LinuxBIOS Community,

My name is Marc Jones and I work for the AMD embedded group. Jordan
Crouse and I have been working with Ron Minnich on a Geode LX LinuxBIOS
implementation for the AMD Norwich development platform. The Norwich
platform should be a good starting point for all current and future
Geode LX platforms.

Our implementation has been split into four patches: cpu, northbridge,
southbridge, and mainboard. All four are required to build the Norwich
platform. Ron and I expect this to break the current OLPC mainboards. We
will work on fixing then soon (Note that OLPC went from GX to LX so an
update was required regardless).

In addition to the patches you will need the Geode LX VSA binary that is
located here:

http://www.amd.com/files/connectivitysolutions/geode/geode_lx/lx_vsa.36k.bin...

You might find it helpful to use BuildROM to build the Norwich platform.
BuildROM builds LinuxBIOS, builds a payload (etherboot, filo, or
memtest), and bundles in the LX VSA to make one ROM image. Jordan Crouse
will be sending out patches and instructions for buildROM soon.

I look forward to working with you all.

Marc

[LinuxBIOS] [patch 1/4] Geode LX: CPU

[Marc Jones]

This patch adds support for the AMD Geode LX CPU.

Signed-off-by: Marc Jones

Index: LinuxBIOSv2/src/cpu/amd/model_lx/cpubug.c
===================================================================
--- LinuxBIOSv2.orig/src/cpu/amd/model_lx/cpubug.c	2007-04-30 15:25:27.000000000 -0600
+++ LinuxBIOSv2/src/cpu/amd/model_lx/cpubug.c	2007-05-01 12:09:15.000000000 -0600
@@ -1,35 +1,18 @@
+/*
+* Copyright (C) 2007 Advanced Micro Devices
+*/
+
+
 #include <console/console.h>
 #include <arch/io.h>
 #include <stdint.h>
 #include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>
-#include <cpu/amd/lxdef.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-
-
-#if 0
-void
-bug645(void){
-	msr_t msr;
-	rdmsr(CPU_ID_CONFIG);
-	msr.whatever |= ID_CONFIG_SERIAL_SET;
-	wrmsr(msr);
-}
-
-void
-bug573(void){
-	msr_t msr;
+#include <cpu/amd/lxdef.h>

-	msr = rdmsr(MC_GLD_MSR_PM);
-	msr.eax &= 0xfff3;
-	wrmsr(MC_GLD_MSR_PM);
-}
-#endif

/**************************************************************************
  *
@@ -39,36 +22,21 @@
  *	PCI cache deadlock
  *	There is also fix code in cache and PCI functions. This bug is very is pervasive.
  *
- *	Entry:
- *	Exit:
- *	Modified:
- *
  **************************************************************************/
-static void
-pcideadlock(void)
-{
+static void pcideadlock(void){
    msr_t msr;

/*
-	 * forces serialization of all load misses. Setting this bit prevents the 
-	 * DM pipe from backing up if a read request has to be held up waiting 
+	 * forces serialization of all load misses. Setting this bit prevents the
+	 * DM pipe from backing up if a read request has to be held up waiting
     * for PCI writes to complete.
    */
    msr = rdmsr(CPU_DM_CONFIG0);
-	msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
-	msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
    msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
    wrmsr(CPU_DM_CONFIG0, msr);

-	/* interlock instruction fetches to WS regions with data accesses.
-	 * This prevents an instruction fetch from going out to PCI if the 
-	 * data side is about to make a request.
-	 */
-	msr = rdmsr(CPU_IM_CONFIG);
-	msr.lo |= IM_CONFIG_LOWER_QWT_SET;
-	wrmsr(CPU_IM_CONFIG, msr);
-	
-	/* write serialize memory hole to PCI. Need to unWS when something is 
+
+	/* write serialize memory hole to PCI. Need to unWS when something is
     * shadowed regardless of cachablility.
     */
    msr.lo = 0x021212121;
@@ -78,249 +46,6 @@
    wrmsr( CPU_RCONF_E0_FF, msr);
 }

-/**************************************************************************** 
- *
- *	CPUbug784
- *
- *	Bugtool #784 + #792
- *
- *	Fix CPUID instructions for < 3.0 CPUs
- *
- *	Entry:
- *	Exit:
- *	Modified:
- *
- ****************************************************************************/
-
-void bug784(void)
-{
-	msr_t msr;
-	//static char *name = "Geode by NSC";
-
-	/* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
-	 * would do this -- the OS can figure this type of stuff out!
-	 */
-	msr = rdmsr(0x3006);
-	msr.hi = 0x646f6547;
-	wrmsr(0x3006, msr);
-
-	msr = rdmsr(0x3007);
-	msr.hi = 0x79622065;
-	msr.lo = 0x43534e20;
-	wrmsr(0x3007, msr);
-
-	msr = rdmsr(0x3002);
-	wrmsr(0x3008, msr);
-
-	/* More CPUID to match AMD better. #792*/
-	msr = rdmsr(0x3009);
-	msr.hi = 0x0C0C0A13D;
-	msr.lo = 0x00000000;
-	wrmsr(0x3009, msr);
-}
-
-/* cpubug 1398: enable MC if we KNOW we have DDR*/
-/**************************************************************************
- *
- *	CPUbugIAENG1398
- *
- *	ClearQuest #IAENG1398
- *	The MC can not be enabled with SDR memory but can for DDR. Enable for
- *	DDR here if the setup token is "Default"
- *	Add this back to core by default once 2.0 CPUs are not supported.
- *	Entry:
- *	Exit:
- *	Modified:
- *
- **************************************************************************/
-void eng1398(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(MSR_GLCP+0x17);
-	if ((msr.lo & 0xff) <= CPU_REV_2_0) {
-		msr = rdmsr(GLCP_SYS_RSTPLL);
-		if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
-			return;
-	}
-
-	/* no CMOS/NVRAM to check, so enable MC Clock Gating */
-	msr = rdmsr(MC_GLD_MSR_PM);
-	msr.lo |= 3; /* enable MC clock gating.*/
-	wrmsr(MC_GLD_MSR_PM, msr);
-}
-
-/***************************************************************************
- *
- *	CPUbugIAENG2900
- *
- *	Clear Quest IAENG00002900, VSS 118.150
- *
- *	BTB issue causes blue screen in windows, but the fix is required
- *	for all operating systems.
- *
- *	Entry:
- *	Exit:
- *	Modified:
- *
- **************************************************************************/
-void
-eng2900(void)
-{
-	msr_t msr;
-
-	printk_debug("CPU_BUG:%s\n", __FUNCTION__);
-	/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
-	msr = rdmsr(0x3003);
-	msr.hi &= 0xFFFFF7FF;
-	wrmsr(0x3003, msr);
-
-	/* change this value to zero if you need to disable this BTB SWAPSiF. */
-	if (1) { 
-
-		/* Disable enable_actions in DIAGCTL while setting up GLCP */
-		msr.hi = 0;
-		msr.lo = 0;
-		wrmsr(MSR_GLCP + 0x005f, msr);
-
-		/* Changing DBGCLKCTL register to GeodeLink */
-		msr.hi = 0;
-		msr.lo = 0;
-		wrmsr(MSR_GLCP + 0x0016, msr);
-
-		msr.hi = 0;
-		msr.lo = 2;
-		wrmsr(MSR_GLCP + 0x0016, msr);
-
-		/* The code below sets up the CPU to stall for 4 GeodeLink 
-		 * clocks when CPU is snooped.  Because setting XSTATE to 0 
-		 * overrides any other XSTATE action, the code will always 
-		 * stall for 4 GeodeLink clocks after a snoop request goes 
-		 * away even if it occured a clock or two later than a 
-		 * different snoop; the stall signal will never 'glitch high' 
-		 * for only one or two CPU clocks with this code.
-		 */
-
-		/* Send mb0 port 3 requests to upper GeodeLink diag bits 
-		   [63:32] */
-		msr.hi = 0;
-		msr.lo = 0x80338041;
-		wrmsr(MSR_GLIU0 + 0x2005, msr);
-
-		/* set5m watches request ready from mb0 to CPU (snoop) */
-		msr.hi = 0x5ad68000;
-		msr.lo = 0;
-		wrmsr(MSR_GLCP + 0x0045, msr);
-
-		/* SET4M will be high when state is idle (XSTATE=11) */
-		msr.hi = 0;
-		msr.lo = 0x0140;
-		wrmsr(MSR_GLCP + 0x0044, msr);
-
-		/* SET5n to watch for processor stalled state */
-		msr.hi = 0x2000;
-		msr.lo = 0;
-		wrmsr(MSR_GLCP + 0x004D, msr);
-
-		/* Writing action number 13: XSTATE=0 to occur when CPU is 
-		   snooped unless we're stalled */
-		msr.hi = 0;
-		msr.lo = 0x00400000;
-		wrmsr(MSR_GLCP + 0x0075, msr);
-
-		/* Writing action number 11: inc XSTATE every GeodeLink clock 
-		   unless we're idle */
-		msr.hi = 0;
-		msr.lo = 0x30000;
-		wrmsr(MSR_GLCP + 0x0073, msr);
-
-		/* Writing action number 5: STALL_CPU_PIPE when exitting idle 
-		   state or not in idle state */
-		msr.hi = 0;
-		msr.lo = 0x00430000;
-		wrmsr(MSR_GLCP + 0x006D, msr);
-
-		/* Writing DIAGCTL Register to enable the stall action and to 
-		   let set5m watch the upper GeodeLink diag bits. */
-		msr.hi = 0;
-		msr.lo = 0x80004000;
-		wrmsr(MSR_GLCP + 0x005f, msr);
-	}
-}
-
-void bug118253(void)
-{
-	/* GLPCI PIO Post Control shouldn't be enabled */
-	msr_t msr;
-
-	msr = rdmsr(GLPCI_SPARE);
-	msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
-	wrmsr(GLPCI_SPARE, msr);
-}
-
-void bug118339(void)
-{
-	/* per AMD, do this always */
-	msr_t msr = {0,0};
-	int msrnum;
-
-	/* Disable enable_actions in DIAGCTL while setting up GLCP */
-	wrmsr(MSR_GLCP + 0x005f, msr);
-
-	/*  SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
-	msrnum =  MSR_GLCP + 0x042;
-	/* 	msr.hi =  2d6b8000h */;
-	msr.hi =  0x596b8000;
-	msr.lo =  0x00000a00;
-	wrmsr(msrnum, msr);
-
-	/*  SET3M fires if MBUS changed and VG pri is odd */
-	msrnum =  MSR_GLCP + 0x043;
-	msr.hi =  0x596b8040;
-	msr.lo = 0;
-	wrmsr(msrnum, msr);
-
-	/*  Put VG request data on lower diag bus */
-	msrnum =  MSR_GLIU0 + 0x2005;
-	msr.hi = 0;
-	msr.lo =  0x80338041;
-	wrmsr(msrnum, msr);
-
-	/*  Increment Y state if SET3M if true */
-	msrnum =  MSR_GLCP + 0x074;
-	msr.hi = 0;
-	msr.lo =  0x0000c000;
-	wrmsr(msrnum, msr);
-
-	/*  Set up MBUS action to PRI=3 read of MBIU */
-	msrnum =  MSR_GLCP + 0x020;
-	msr.hi =  0x0000d863;
-	msr.lo =  0x20002000;
-	wrmsr(msrnum, msr);
-
-	/*  Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
-	msrnum =  MSR_GLCP + 0x071;
-	msr.hi = 0;
-	msr.lo =  0x00000c00;
-	wrmsr(msrnum, msr);
-
-	/* Writing DIAGCTL */
-	msrnum =  MSR_GLCP + 0x005f;
-	msr.hi = 0;
-	msr.lo =  0x80004000;
-	wrmsr(msrnum, msr);
-
-	/*  Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
-	/*  As per Todd Roberts in PBz1094 and PBz1095 */
-	/*  Moved from CPUREG to CPUBUG per Tom Sylla */
-	msrnum =  0x04C000042;		/*  GLCP SETMCTL Register */;
-	msr = rdmsr(msrnum);
-	msr.hi |= 8;			/*  Bit 35 = MCP_IN */
-	wrmsr(msrnum, msr);
-}
-
-
-
 /****************************************************************************/
 /***/
 /**	DisableMemoryReorder*/
@@ -331,62 +56,18 @@
 /**	 This is safe to do here and not in MC init since there is nothing*/
 /**	 to maintain coherency with and the cache is not enabled yet.*/
 /***/
-/***/
-/**	Entry:*/
-/**	Exit:*/
-/**	Modified:*/
-/***/
 /****************************************************************************/
-void disablememoryreadorder(void)
-{	
+static void disablememoryreadorder(void){
    msr_t msr;
-	msr = rdmsr(MC_CF8F_DATA);

+	msr = rdmsr(MC_CF8F_DATA);
    msr.hi |=  CF8F_UPPER_REORDER_DIS_SET;
    wrmsr(MC_CF8F_DATA, msr);
 }

-void
-cpubug(void)
-{
-#if 0 //GX3: any CPU bugs to fix here? :)
-	msr_t msr;
-	int rev;
-
-	msr = rdmsr(GLCP_CHIP_REVID);
-
-	rev = msr.lo & 0xff;
-	if (rev < 0x20) {
-		printk_err("%s: rev < 0x20! bailing!\n");
-		return;
-	}
-	printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
-	switch(rev)
-	{
-		case 0x20:
-			pcideadlock();
-			eng1398();
-			/* cs 5530 bug; ignore 
-			bug752();
-			*/
-			break;
-		case 0x21:
-			pcideadlock();
-			eng1398();
-			eng2900();
-			bug118339();
-			break;
-		case 0x22:
-		case 0x30: 
-			break;
-		default:
-			printk_err("unknown rev %x, bailing\n", rev);
-			return;
-	}
-	bug784();
-	bug118253();
+/* For cpu version C3. Should be the only released version */
+void cpubug(void) {
+	pcideadlock();
    disablememoryreadorder();
    printk_debug("Done cpubug fixes \n");
-#endif
-
 }
Index: LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c
===================================================================
--- LinuxBIOSv2.orig/src/cpu/amd/model_lx/cpureginit.c	2007-04-30 15:25:27.000000000 -0600
+++ LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c	2007-05-01 12:09:15.000000000 -0600
@@ -1,76 +1,223 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/

-/* ***************************************************************************/
-/* **/
-/* *	BIST */
-/* **/
-/* *	GX2 BISTs need to be run before BTB or caches are enabled.*/
-/* *	BIST result left in registers on failure to be checked with FS2.*/
-/* **/
-/* ***************************************************************************/
-static void
-BIST(void){
-	int msrnum;
+/**************************************************************************
+;*
+;*	SetDelayControl
+;*
+;*************************************************************************/
+void SetDelayControl(void){
+	unsigned int msrnum, glspeed;
+	unsigned char spdbyte0, spdbyte1;
    msr_t msr;

-	/* DM*/
-	msrnum = CPU_DM_CONFIG0;
-	msr = rdmsr(msrnum);
-	msr.lo |=  DM_CONFIG0_LOWER_DCDIS_SET;
-	wrmsr(msrnum, msr);
-	
-	msr.lo =  0x00000003F;
-	msr.hi =  0x000000000;
-	msrnum = CPU_DM_BIST;
-	wrmsr(msrnum, msr);
+	glspeed = GeodeLinkSpeed();
+
+	/* fix delay controls for DM and IM arrays */
+	msrnum = CPU_BC_MSS_ARRAY_CTL0;
+	msr.hi = 0;
+	msr.lo = 0x2814D352;
+	wrmsr(msrnum,msr);

-	outb(POST_CPU_DM_BIST_FAILURE, 0x80);				/* 0x29*/
-	msr = rdmsr(msrnum);						/* read back for pass fail*/
-	msr.lo &= 0x0F3FF0000;
-	if (msr.lo != 0xfeff0000)
-		goto BISTFail;
- 
-	msrnum = CPU_DM_CONFIG0;
+	msrnum = CPU_BC_MSS_ARRAY_CTL1;
+	msr.hi = 0;
+	msr.lo = 0x1068334D;
+	wrmsr(msrnum,msr);
+
+	msrnum = CPU_BC_MSS_ARRAY_CTL2;
+	msr.hi = 0x00000106;
+	msr.lo = 0x83104104;
+	wrmsr(msrnum,msr);
+
+	msrnum = GLCP_FIFOCTL;
    msr = rdmsr(msrnum);
-	msr.lo &=  ~ DM_CONFIG0_LOWER_DCDIS_SET;
-	wrmsr(msrnum, msr);
+	msr.hi = 0x00000005;
+	wrmsr(msrnum,msr);

-	/* FPU*/
-	msr.lo =  0x000000131;
+	/* Enable setting */
+	msrnum = CPU_BC_MSS_ARRAY_CTL_ENA;
    msr.hi = 0;
-	msrnum = CPU_FP_UROM_BIST;
-	wrmsr(msrnum, msr);
+	msr.lo = 0x00000001;
+	wrmsr(msrnum,msr);

-	outb(POST_CPU_FPU_BIST_FAILURE, 0x80);				/* 0x89*/
-	inb(0x80);									/*  IO delay*/
-	msr = rdmsr(msrnum);							/* read back for pass fail*/
-	while ((msr.lo&0x884) != 0x884)
-		msr = rdmsr(msrnum);					/*  Endless loop if BIST is broken*/
-	if ((msr.lo&0x642) != 0x642)
-		goto BISTFail;

-	msr.lo = msr.hi = 0;				/*  clear FPU BIST bits*/
-	msrnum = CPU_FP_UROM_BIST;
-	wrmsr(msrnum, msr);
+	/* Debug Delay Control Setup Check
+	Leave it alone if it has been setup. FS2 or something is here.*/
+	msrnum = GLCP_DELAY_CONTROLS;
+	msr = rdmsr(msrnum);
+	if (msr.lo & ~(0x7C0)){
+		return;
+	}

-	/* BTB*/
-	msr.lo =  0x000000303;
-	msr.hi =  0x000000000;
-	msrnum = CPU_PF_BTBRMA_BIST;
-	wrmsr(msrnum, msr);
+	/*
+	; Delay Controls based on DIMM loading. UGH!
+	; # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
+	; Note - We only support module width of 64.
+	*/
+	spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
+	if (spdbyte0 !=0xFF){
+		spdbyte0 = (unsigned char) 64/spdbyte0 * (unsigned char) (spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS));
+	}
+	else{
+		spdbyte0=0;
+	}
+
+	spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH);
+	if (spdbyte1 !=0xFF){
+		spdbyte1 = (unsigned char) 64/spdbyte1 * (unsigned char) (spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS));
+	}
+	else{
+		spdbyte1=0;
+	}

-	outb(POST_CPU_BTB_BIST_FAILURE	, 0x80);				/* 0x8A*/
-	msr = rdmsr(msrnum);							/* read back for pass fail*/
-	if ((msr.lo & 0x3030) != 0x3030)
-		goto BISTFail;

-	return;

-BISTFail:
-	print_err("BIST failed!\n");
-	while(1);
+/* The current thinking. Subject to change...
+
+;								   "FUTURE ROBUSTNESS" PROPOSAL
+;								   ----------------------------
+;		DIMM	 Max MBUS					   MC 0x2000001A bits 26:24
+;DIMMs	devices	 Frequency	 MCP 0x4C00000F Setting		 vvv
+;-----	-------	 ---------	 ----------------------	 ----------
+;1		 4		 400MHz		 0x82*100FF 0x56960004		  4
+;1		 8		 400MHz		 0x82*100AA 0x56960004		  4
+;1		 16		 400MHz		 0x82*10055 0x56960004		  4
+;
+;2		 4,4	 400MHz		 0x82710000 0x56960004		  4
+;2		 8,8	 400MHz		 0xC27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
+;
+;2		16,4	 >333		 0xB27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
+;2		16,8	 >333		 0xB27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
+;2		16,16	 >333		 0xB2710000 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
+;
+;1		 4		 <=333MHz	 0x83*100FF 0x56960004		  3
+;1		 8		 <=333MHz	 0x83*100AA 0x56960004		  3
+;1		 16		 <=333MHz	 0x83*100AA 0x56960004		  3
+;
+;2		 4,4	 <=333MHz	 0x837100A5 0x56960004		  3
+;2		 8,8	 <=333MHz	 0x937100A5 0x56960004		  3
+;
+;2		16,4	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
+;2		16,8	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
+;2		16,16	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
+;=========================================================================
+;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
+;	 but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
+;	 Bits 54:52 should always be set to '111'.
+
+;No VTT termination
+;-------------------------------------
+;ADDR/CTL have 22 ohm series R
+;DQ/DQM/DQS have 33 ohm series R
+;
+;		DIMM	 Max MBUS
+;DIMMs	devices	 Frequency	 MCP 0x4C00000F Setting
+;-----	-------	 ---------	 ----------------------
+;1		 4		 400MHz		 0xF2F100FF 0x56960004		  4			The MC changes improve Salsa.
+;1		 8		 400MHz		 0xF2F100FF 0x56960004		  4			Delay controls no real change,
+;1		 4		 <=333MHz	 0xF2F100FF 0x56960004		  3			just fixing typo in left side.
+;1		 8		 <=333MHz	 0xF2F100FF 0x56960004		  3
+;1		 16		 <=333MHz	 0xF2F100FF 0x56960004		  3
+*/
+	msr.hi = msr.lo = 0;
+
+	if (spdbyte0 == 0 || spdbyte1 == 0){
+		/* one dimm solution */
+		if (spdbyte1 == 0){
+			msr.hi |= 0x000800000;
+		}
+		spdbyte0 += spdbyte1;
+		if (spdbyte0 > 8){
+			/* large dimm */
+			if (glspeed < 334){
+				msr.hi |= 0x0837100AA;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x082710055;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else if (spdbyte0 > 4){
+			/* medium dimm */
+			if (glspeed < 334){
+				msr.hi |= 0x0837100AA;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0827100AA;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else{
+			/* small dimm */
+			if (glspeed < 334){
+				msr.hi |= 0x0837100FF;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0827100FF;
+				msr.lo |= 0x056960004;
+			}
+		}
+	}
+	else{
+		/* two dimm solution */
+		spdbyte0 += spdbyte1;
+		if (spdbyte0 > 24){
+			/* huge dimms */
+			if (glspeed < 334){
+				msr.hi |= 0x0B37100A5;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0B2710000;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else if (spdbyte0 > 16){
+			/* large dimms */
+			if (glspeed < 334){
+				msr.hi |= 0x0B37100A5;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0B27100A5;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else if (spdbyte0 >= 8){
+			/* medium dimms */
+			if (glspeed < 334){
+				msr.hi |= 0x0937100A5;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x0C27100A5;
+				msr.lo |= 0x056960004;
+			}
+		}
+		else{
+			/* small dimms */
+			if (glspeed < 334){
+				msr.hi |= 0x0837100A5;
+				msr.lo |= 0x056960004;
+			}
+			else{
+				msr.hi |= 0x082710000;
+				msr.lo |= 0x056960004;
+			}
+		}
+	}
+	wrmsr(GLCP_DELAY_CONTROLS,msr);
+	return;
 }
+
 /* ***************************************************************************/
 /* *	cpuRegInit*/
 /* ***************************************************************************/
@@ -78,174 +225,79 @@
 cpuRegInit (void){
    int msrnum;
    msr_t msr;
-	
-	//GX3 suspend: what is desired?

-	/*  Enable Suspend on Halt*/
-	/*msrnum = CPU_XC_CONFIG;
+	/* Castle 2.0 BTM periodic sync period. */
+	/*	[40:37] 1 sync record per 256 bytes */
+	msrnum = CPU_PF_CONF;
    msr = rdmsr(msrnum);
-	msr.lo |=  XC_CONFIG_SUSP_ON_HLT;
-	wrmsr(msrnum, msr);*/
+	msr.hi |= (0x8 << 5);
+	wrmsr(msrnum, msr);

-	/*  ENable SUSP and allow TSC to run in Suspend */
-	/*  to keep speed detection happy*/
-	/*msrnum = CPU_BC_CONF_0;
-	msr = rdmsr(msrnum);
-	msr.lo |=  TSC_SUSP_SET | SUSP_EN_SET;
-	wrmsr(msrnum, msr);*/
-
-	/*  Setup throttling to proper mode if it is ever enabled.*/
-	msrnum = 0x04C00001E;
-	msr.hi =  0x000000000;
-	msr.lo =  0x00000603C;
-	wrmsr(msrnum, msr);		// GX3 OK +/-
-
-
-/*  Only do this if we are building for 5535*/
-/* */
-/*  FooGlue Setup*/
-/* */
-#if 0
-	/*  Enable CIS mode B in FooGlue*/
-	msrnum = MSR_FG + 0x10;
+	/*
+	; Castle performance setting.
+	; Enable Quack for fewer re-RAS on the MC
+	*/
+	msrnum = GLIU0_ARB;
    msr = rdmsr(msrnum);
-	msr.lo &= ~3;
-	msr.lo |= 2;			/*  ModeB*/
+	msr.hi &= ~ARB_UPPER_DACK_EN_SET;
+	msr.hi |= ARB_UPPER_QUACK_EN_SET;
    wrmsr(msrnum, msr);
-#endif
-
-/* */
-/*  Disable DOT PLL. Graphics init will enable it if needed.*/
-/* */

-// GX3: Disable DOT PLL? No. Lets tick.
-
-/*	msrnum = GLCP_DOTPLL;
+	msrnum = GLIU1_ARB;
    msr = rdmsr(msrnum);
-	msr.lo |= DOTPPL_LOWER_PD_SET;
-	wrmsr(msrnum, msr); */
+	msr.hi &= ~ARB_UPPER_DACK_EN_SET;
+	msr.hi |= ARB_UPPER_QUACK_EN_SET;
+	wrmsr(msrnum, msr);

-/* */
-/*  Enable RSDC*/
-/* */
-	msrnum = 0x1301 ;
+	/*	GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
+	msrnum = GLIU1_PORT_ACTIVE;
    msr = rdmsr(msrnum);
-	msr.lo |=  0x08;
-	wrmsr(msrnum, msr);		//GX3 OK
-
-
-/* */
-/*  BIST*/
-/* */
-	/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
-	{
-//		BIST();
-	}
-
+	msr.lo &= ~0x880;
+	wrmsr(msrnum,msr);

-/* */
-/*  Enable BTB*/
-/* */
-	/*  I hate to put this check here but it doesn't really work in cpubug.asm*/
+	/* Set the Delay Control in GLCP */
+	SetDelayControl();

-//GX3: BTB is enabled by default
-
-/*	msrnum = MSR_GLCP+0x17;
+	/* Enable RSDC */
+	msrnum = CPU_AC_SMM_CTL;
    msr = rdmsr(msrnum);
-	if (msr.lo >= CPU_REV_2_1){
-		msrnum = CPU_PF_BTB_CONF;
-		msr = rdmsr(msrnum);
-		msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
-		wrmsr(msrnum, msr);
-	}
-
-	*/
-
-/* */
-/*  FPU impercise exceptions bit*/
-/* */
-	/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
-
-
-
-// GX3: FPU impercise exceptions bit - what's that?
-/*	{
-		msrnum = CPU_FPU_MSR_MODE;
-		msr = rdmsr(msrnum);
-		msr.lo |= FPU_IE_SET;
-		wrmsr(msrnum, msr);
-	}
-
-	*/
-
-#if 0
-	/* */
-	/*  Cache Overides*/
-	/* */
-	/* This code disables the data cache.  Don't execute this
-	 * unless you're testing something.
-	 */ 
-	/*  Allow NVRam to override DM Setup*/
-	/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
-	{
-
-		msrnum = CPU_DM_CONFIG0;
-		msr = rdmsr(msrnum);
-		msr.lo |=  DM_CONFIG0_LOWER_DCDIS_SET;
-		wrmsr(msrnum, msr);
-	}
-	/* This code disables the instruction cache.  Don't execute
-	 * this unless you're testing something.
-	*/ 
-	/*  Allow NVRam to override IM Setup*/
-	/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
-	{
-		msrnum = CPU_IM_CONFIG;
-		msr = rdmsr(msrnum);
-		msr.lo |=  IM_CONFIG_LOWER_ICD_SET;
-		wrmsr(msrnum, msr);
-	}
-#endif
-}
+	msr.lo |= SMM_INST_EN_SET;
+	wrmsr(msrnum,msr);

+	/* FPU imprecise exceptions bit */
+	msrnum = CPU_FPU_MSR_MODE;
+	msr = rdmsr(msrnum);
+	msr.lo |= FPU_IE_SET;
+	wrmsr(msrnum,msr);

-/* ***************************************************************************/
-/* **/
-/* *	MTestPinCheckBX*/
-/* **/
-/* *	Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/
-/* *  This version is called when there isn't a stack available*/
-/* **/
-/* ***************************************************************************/
-static void
-MTestPinCheckBX (void){
-	int msrnum;
-	msr_t msr;
-
-	/*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/
-			/* return ; */
-	/* } */
-
-	/*  Turn on MTEST*/
-	msrnum = MC_CFCLK_DBUG;
+	/* Power Savers (Do after BIST) */
+	/* Enable Suspend on HLT & PAUSE instructions*/
+	msrnum = CPU_XC_CONFIG;
    msr = rdmsr(msrnum);
-	msr.hi |=  CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET;
-	wrmsr(msrnum, msr);
+	msr.lo |= XC_CONFIG_SUSP_ON_HLT |  XC_CONFIG_SUSP_ON_PAUSE;
+	wrmsr(msrnum,msr);

-	msrnum = GLCP_SYS_RSTPLL			/*  Get SDR/DDR mode from GLCP*/;
+	/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
+	msrnum = CPU_BC_CONF_0;
    msr = rdmsr(msrnum);
-	msr.lo >>=  RSTPPL_LOWER_SDRMODE_SHIFT;
-	if (msr.lo & 1) {
-		msrnum = MC_CFCLK_DBUG;			/*  Turn on SDR MTEST stuff*/
-		msr = rdmsr(msrnum);
-		msr.lo |=  CFCLK_LOWER_SDCLK_SET;
-		msr.hi |=  CFCLK_UPPER_MTST_DQS_EN_SET;
-		wrmsr(msrnum, msr);
-	}
-
-	/*  Lock the cache down here.*/
-	__asm__("wbinvd\n");
+	msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
+	msr.lo &= 0x0F0FFFFFF;
+	msr.lo |= 0x002000000;	 /* PBZ213: Set PAUSEDLY = 2 */
+	wrmsr(msrnum,msr);
+
+	/* Disable the debug clock to save power.*/
+	/* NOTE: leave it enabled for fs2 debug */
+/*	msrnum = GLCP_DBGCLKCTL;
+	msr.hi = 0;
+	msr.lo = 0;
+	wrmsr(msrnum,msr);
+*/

+	/* Setup throttling delays to proper mode if it is ever enabled. */
+	msrnum = GLCP_TH_OD;
+	msr.hi = 0;
+	msr.lo = 0x00000603C;
+	wrmsr(msrnum,msr);
 }
Index: LinuxBIOSv2/src/cpu/amd/model_lx/syspreinit.c
===================================================================
--- LinuxBIOSv2.orig/src/cpu/amd/model_lx/syspreinit.c	2007-04-30 15:25:27.000000000 -0600
+++ LinuxBIOSv2/src/cpu/amd/model_lx/syspreinit.c	2007-05-01 12:09:15.000000000 -0600
@@ -1,3 +1,10 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
+
+
 /* ***************************************************************************/
 /* **/
 /* *	StartTimer1*/
@@ -17,6 +24,8 @@
 SystemPreInit(void){

/* they want a jump ... */
-	__asm__("jmp .+2\ninvd\njmp.+2\n");
+#ifndef USE_DCACHE_RAM
+	__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
+#endif
    StartTimer1();
 }
Index: LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c
===================================================================
--- LinuxBIOSv2.orig/src/cpu/amd/model_lx/vsmsetup.c	2007-04-30 15:25:27.000000000 -0600
+++ LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c	2007-05-01 12:09:15.000000000 -0600
@@ -17,62 +17,65 @@
 /* vsmsetup.c derived from vgabios.c. Derived from: */

/*------------------------------------------------------------ -*- C -*-
- *  2 Kernel Monte a.k.a. Linux loading Linux on x86
+ *	2 Kernel Monte a.k.a. Linux loading Linux on x86
  *
- *  Erik Arjan Hendriks 
+ *	Erik Arjan Hendriks 
  *
- *  This version is a derivative of the original two kernel monte
- *  which is (C) 2000 Scyld.
+ *	This version is a derivative of the original two kernel monte
+ *	which is (C) 2000 Scyld.
  *
- *  Copyright (C) 2000 Scyld Computing Corporation
+ *	Copyright (C) 2000 Scyld Computing Corporation
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
  *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
+ *	This program is distributed in the hope that it will be useful,
+ *	but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *	GNU General Public License for more details.
  *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *	You should have received a copy of the GNU General Public License
+ *	along with this program; if not, write to the Free Software
+ *	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  *
  * Portions related to the alpha architecture are:
  *
- *  Copyright(C) 2001 University of California.  LA-CC Number 01-67.
- *  This software has been authored by an employee or employees of the
- *  University of California, operator of the Los Alamos National
- *  Laboratory under Contract No.  W-7405-ENG-36 with the U.S.
- *  Department of Energy.  The U.S. Government has rights to use,
- *  reproduce, and distribute this software. If the software is
- *  modified to produce derivative works, such modified software should
- *  be clearly marked, so as not to confuse it with the version
- *  available from LANL.
- *
- *  This software may be used and distributed according to the terms
- *  of the GNU General Public License, incorporated herein by
- *  reference to http://www.gnu.org/licenses/gpl.html.
- *
- *  This software is provided by the author(s) "as is" and any express
- *  or implied warranties, including, but not limited to, the implied
- *  warranties of merchantability and fitness for a particular purpose
- *  are disclaimed.  In no event shall the author(s) be liable for any
- *  direct, indirect, incidental, special, exemplary, or consequential
- *  damages (including, but not limited to, procurement of substitute
- *  goods or services; loss of use, data, or profits; or business
- *  interruption) however caused and on any theory of liability,
- *  whether in contract, strict liability, or tort (including
- *  negligence or otherwise) arising in any way out of the use of this
- *  software, even if advised of the possibility of such damage.
+ *	Copyright(C) 2001 University of California.	 LA-CC Number 01-67.
+ *	This software has been authored by an employee or employees of the
+ *	University of California, operator of the Los Alamos National
+ *	Laboratory under Contract No.  W-7405-ENG-36 with the U.S.
+ *	Department of Energy.  The U.S. Government has rights to use,
+ *	reproduce, and distribute this software. If the software is
+ *	modified to produce derivative works, such modified software should
+ *	be clearly marked, so as not to confuse it with the version
+ *	available from LANL.
+ *
+ *	This software may be used and distributed according to the terms
+ *	of the GNU General Public License, incorporated herein by
+ *	reference to http://www.gnu.org/licenses/gpl.html.
+ *
+ *	This software is provided by the author(s) "as is" and any express
+ *	or implied warranties, including, but not limited to, the implied
+ *	warranties of merchantability and fitness for a particular purpose
+ *	are disclaimed.	 In no event shall the author(s) be liable for any
+ *	direct, indirect, incidental, special, exemplary, or consequential
+ *	damages (including, but not limited to, procurement of substitute
+ *	goods or services; loss of use, data, or profits; or business
+ *	interruption) however caused and on any theory of liability,
+ *	whether in contract, strict liability, or tort (including
+ *	negligence or otherwise) arising in any way out of the use of this
+ *	software, even if advised of the possibility of such damage.
  *
  *  $Id: vsmsetup.c,v 1.8 2006/09/08 12:47:57 andrei Exp $
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
  *--------------------------------------------------------------------*/

-/* Modified to be a self sufficient plug in so that it can be used 
-   without reliance on other parts of core Linuxbios 
+/* Modified to be a self sufficient plug in so that it can be used
+   without reliance on other parts of core Linuxbios
    (C) 2005 [e-mail]

Used initially for epia-m where there are problems getting the bios
@@ -85,7 +88,7 @@
    /* pointer to original gdt */
    "gdtarg:			\n"
    "	.word	gdt_limit	\n"
-	"	.long	gdt	       	\n"		
+	"	.long	gdt	       	\n"

/* compute the table limit */
    "__mygdt_limit = __mygdt_end - __mygdt - 1	\n"
@@ -105,7 +108,7 @@

/* selgdt 0x10, flat code segment */
    "	.word	0xffff, 0x0000	       	\n"
-	"	.byte	0x00, 0x9b, 0xcf, 0x00	\n"	
+	"	.byte	0x00, 0x9b, 0xcf, 0x00	\n"

/* selgdt 0x18, flat data segment */
    "	.word	0xffff, 0x0000	       	\n"
@@ -115,7 +118,7 @@
    "	.word	0x0000, 0x0000	       	\n"
    "	.byte	0x00, 0x00, 0x00, 0x00	\n"

-        /* selgdt 0x28 16-bit 64k code at 0x00000000 */
+		/* selgdt 0x28 16-bit 64k code at 0x00000000 */
    "	.word	0xffff, 0x0000	       	\n"
    "	.byte	0, 0x9a, 0, 0	       	\n"

@@ -135,14 +138,14 @@
     "	.word 0		\n"
 );

-/* The address arguments to this function are PHYSICAL ADDRESSES */ 
+/* The address arguments to this function are PHYSICAL ADDRESSES */
 static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
 {
    uint16_t entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4;
    uint16_t entryLo = (VSA2_ENTRY_POINT & 0xffff);

__asm__ __volatile__ (
-		// paranoia -- does ecx get saved? not sure. This is 
+		// paranoia -- does ecx get saved? not sure. This is
    	// the easiest safe thing to do.
    	"	pushal			\n"
    	/* save the stack */
@@ -153,7 +156,7 @@
    	/* get devfn into %%ecx */
    	"	movl    %%esp, %%ebp	\n"
 #if 0
-		/* I'm not happy about that pushal followed by esp-relative references. 
+		/* I'm not happy about that pushal followed by esp-relative references.
    	  * just do hard-codes for now
    	  */
    	"	movl    8(%%ebp), %%ecx	\n"
@@ -165,14 +168,14 @@
    	/* load 'our' gdt */
    	"	lgdt	%%cs:__mygdtaddr	\n"

-		/*  This configures CS properly for real mode. */
+		/*	This configures CS properly for real mode. */
    	"	ljmp	$0x28, $__rms_16bit\n"
    	"__rms_16bit:		  	\n"
    	"	.code16			\n"
    	/* 16 bit code from here on... */

/* Load the segment registers w/ properly configured segment
-		 * descriptors.  They will retain these configurations (limits,
+		 * descriptors.	 They will retain these configurations (limits,
    	 * writability, etc.) once protected mode is turned off. */
    	"	mov	$0x30, %%ax	\n"
    	"	mov	%%ax, %%ds       	\n"
@@ -190,8 +193,8 @@
    	"	ljmp	$0,  $__rms_real\n"
    	"__rms_real:			\n"

-		/* put the stack at the end of page zero. 
-		 * that way we can easily share it between real and protected, 
+		/* put the stack at the end of page zero.
+		 * that way we can easily share it between real and protected,
    	 * since the 16-bit ESP at segment 0 will work for any case. */
    	/* Setup a stack */
    	"	mov	$0x0, %%ax	\n"
@@ -218,7 +221,7 @@
    	/* call the VSA2 entry point address */
    	"	lcall	%2, %3\n"

-		/* if we got here, just about done. 
+		/* if we got here, just about done.
    	 * Need to get back to protected mode */
    	"	movl	%%cr0, %%eax	\n"
    	"	orl	$0x0000001, %%eax\n" /* PE = 1 */
@@ -295,38 +298,40 @@
    unsigned char *buf;
    unsigned int size = SMM_SIZE*1024;
    int i;
-	unsigned long ilen, olen;	
-	
+	unsigned long ilen, olen;
+
    printk_err("do_vsmbios\n");
    /* clear vsm bios data area */
    for (i = 0x400; i < 0x500; i++) {
-		*(unsigned char *) i = 0;
+		*(volatile unsigned char *) i = 0;
    }

/* declare rom address here - keep any config data out of the way
     * of core LXB stuff */

-	/* this is the base of rom on the GX2 at present. At some point, this has to be 
-	  * much better parameterized 
+	/* this is the base of rom on the LX at present. At some point, this has to be
+	  * much better parameterized
      */
    //rom = 0xfff80000;
    //rom = 0xfffc0000;
    /* the VSA starts at the base of rom - 64 */
-	//rom = ((unsigned long) 0) - (ROM_SIZE  + 64*1024);
-	
-	rom = 0xfffc8000;
+	//rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
+
+	//rom = 0xfffc8000;

+	//VSA is cat onto the end after LB builds
+	rom = ((unsigned long) 0) - (ROM_SIZE + 36 * 1024);
    buf = (unsigned char *) VSA2_BUFFER;
    olen = unrv2b((uint8_t *)rom, buf, &ilen);
    printk_debug("buf ilen %d olen%d\n", ilen, olen);
    printk_debug("buf %p *buf %d buf[256k] %d\n",
-		     buf, buf[0], buf[SMM_SIZE*1024]);
+			 buf, buf[0], buf[SMM_SIZE*1024]);
    printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",
-		     buf[0x20] ,buf[0x21] ,buf[0x22],buf[0x23]);
+			 buf[0x20] ,buf[0x21] ,buf[0x22],buf[0x23]);
    /* check for post code at start of vsainit.bin. If you don't see it,
       don't bother. */
    if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
-	    (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
+		(buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
    	printk_err("do_vsmbios: no vsainit.bin signature, skipping!\n");
    	return;
    }
@@ -351,32 +356,32 @@
 }

-// we had hoped to avoid this. 
-// this is a stub IDT only. It's main purpose is to ignore calls 
-// to the BIOS. 
+// we had hoped to avoid this.
+// this is a stub IDT only. It's main purpose is to ignore calls
+// to the BIOS.
 // no longer. Dammit. We have to respond to these.
 struct realidt {
    unsigned short offset, cs;
-}; 
+};

// from a handy writeup that andrey found.

-// handler. 
-// There are some assumptions we can make here. 
-// First, the Top Of Stack (TOS) is located on the top of page zero. 
-// we can share this stack between real and protected mode. 
+// handler.
+// There are some assumptions we can make here.
+// First, the Top Of Stack (TOS) is located on the top of page zero.
+// we can share this stack between real and protected mode.
 // that simplifies a lot of things ...
-// we'll just push all the registers on the stack as longwords, 
-// and pop to protected mode. 
-// second, since this only ever runs as part of linuxbios, 
+// we'll just push all the registers on the stack as longwords,
+// and pop to protected mode.
+// second, since this only ever runs as part of linuxbios,
 // we know all the segment register values -- so we don't save any.
-// keep the handler that calls things small. It can do a call to 
+// keep the handler that calls things small. It can do a call to
 // more complex code in linuxbios itself. This helps a lot as we don't
 // have to do address fixup in this little stub, and calls are absolute
 // so the handler is relocatable.
 void handler(void)
 {
-	__asm__ __volatile__ ( 
+	__asm__ __volatile__ (
    	"	.code16		\n"
    	"idthandle:		\n"
    	"	pushal		\n"
@@ -389,7 +394,7 @@

void debughandler(void)
 {
-	__asm__ __volatile__ ( 
+	__asm__ __volatile__ (
    	"	.code16		\n"
    	"debughandle:		\n"
    	"	pushw	%cx	\n"
@@ -405,9 +410,9 @@

// Calling conventions. The first C function is called with this stuff
 // on the stack. They look like value parameters, but note that if you
-// modify them they will go back to the INTx function modified. 
+// modify them they will go back to the INTx function modified.
 // the C function will call the biosint function with these as
-// REFERENCE parameters. In this way, we can easily get 
+// REFERENCE parameters. In this way, we can easily get
 // returns back to the INTx caller (i.e. vgabios)
 void callbiosint(void)
 {
@@ -419,7 +424,7 @@
    	"	push	%fs	\n"
    	"	push	%gs	\n"
    	// clean up the int #. To save space we put it in the lower
-		// byte. But the top 24 bits are junk. 
+		// byte. But the top 24 bits are junk.
    	"	andl	$0xff, %eax\n"
    	// this push does two things:
    	// - put the INT # on the stack as a parameter
@@ -448,7 +453,7 @@
    	"	.code16			\n"
    	/* 16 bit code from here on... */
    	/* Load the segment registers w/ properly configured segment
-		 * descriptors.  They will retain these configurations (limits,
+		 * descriptors.	 They will retain these configurations (limits,
    	 * writability, etc.) once protected mode is turned off. */
    	"	mov	$0x30, %ax	\n"
    	"	mov	%ax, %ds	\n"
@@ -456,7 +461,7 @@
    	"	mov	%ax, %fs	\n"
    	"	mov	%ax, %gs	\n"
    	"	mov	%ax, %ss	\n"
-		
+
    	/* Turn off protection (bit 0 in CR0) */
    	"	movl	%cr0, %eax		\n"
    	"	andl	$0xFFFFFFFE, %eax	\n"
@@ -468,9 +473,9 @@

/* Setup a stack
    	 * FixME: where is esp? */
-		/* no need for a fix here. The esp is shared from 32-bit and 16-bit mode. 
-		  * you have to hack on the ss, but the esp remains the same across 
-		  * modes. 
+		/* no need for a fix here. The esp is shared from 32-bit and 16-bit mode.
+		  * you have to hack on the ss, but the esp remains the same across
+		  * modes.
    	  */
    	"	mov	$0x0, %ax       \n"
    	"	mov	%ax, %ss	\n"
@@ -504,47 +509,47 @@
 }

enum {
-	PCIBIOS = 0x1a, 
+	PCIBIOS = 0x1a,
    MEMSIZE = 0x12
 };

int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
-	    unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
-	    unsigned long *pecx, unsigned long *peax, unsigned long *pflags);
+		unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+		unsigned long *pecx, unsigned long *peax, unsigned long *pflags);

int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
    	unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
    	unsigned long *pecx, unsigned long *peax, unsigned long *pflags
-        );
+		);

int biosint(unsigned long intnumber,
-	    unsigned long gsfs, unsigned long dses,
-	    unsigned long edi, unsigned long esi,
-	    unsigned long ebp, unsigned long esp, 
-	    unsigned long ebx, unsigned long edx, 
-	    unsigned long ecx, unsigned long eax, 
-	    unsigned long cs_ip, unsigned short stackflags)
+		unsigned long gsfs, unsigned long dses,
+		unsigned long edi, unsigned long esi,
+		unsigned long ebp, unsigned long esp,
+		unsigned long ebx, unsigned long edx,
+		unsigned long ecx, unsigned long eax,
+		unsigned long cs_ip, unsigned short stackflags)
 {
-	unsigned long ip; 
-	unsigned long cs; 
+	unsigned long ip;
+	unsigned long cs;
    unsigned long flags;
    int ret = -1;

ip = cs_ip & 0xffff;
    cs = cs_ip >> 16;
    flags = stackflags;
-	
+
    printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
-		      eax, ebx, ecx, edx);
+	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
+			  eax, ebx, ecx, edx);
    printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
-		     ebp, esp, edi, esi);
+			 ebp, esp, edi, esi);
    printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
-		     ip, cs, flags);
+			 ip, cs, flags);
    printk_debug("biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n",
-		     gsfs >> 16, gsfs & 0xffff, dses >> 16, dses & 0xffff);
+			 gsfs >> 16, gsfs & 0xffff, dses >> 16, dses & 0xffff);

-	// cases in a good compiler are just as good as your own tables. 
+	// cases in a good compiler are just as good as your own tables.
    switch (intnumber) {
    case 0 ... 15:
    	// These are not BIOS service, but the CPU-generated exceptions
@@ -561,23 +566,23 @@
    	// "longjmp"
    	//vga_exit();
    	break;
-		
+
    case PCIBIOS:
-		ret = pcibios( &edi, &esi, &ebp, &esp, 
-			       &ebx, &edx, &ecx, &eax, &flags);
+		ret = pcibios( &edi, &esi, &ebp, &esp,
+				   &ebx, &edx, &ecx, &eax, &flags);
    	break;
-	case MEMSIZE: 
-		// who cares. 
+	case MEMSIZE:
+		// who cares.
    	eax = 128 * 1024;
    	ret = 0;
    	break;
    case 0x15:
-		ret=handleint21( &edi, &esi, &ebp, &esp, 
+		ret=handleint21( &edi, &esi, &ebp, &esp,
    			&ebx, &edx, &ecx, &eax, &flags);
    	break;
    default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", 
-			    intnumber);
+		printk_info("BIOSINT: Unsupport int #0x%x\n",
+				intnumber);
    	break;
    }
    if (ret)
@@ -586,10 +591,10 @@
    	flags &= ~1;
    stackflags = flags;
    return ret;
-} 
+}

-void setup_realmode_idt(void) 
+void setup_realmode_idt(void)
 {
    extern unsigned char idthandle, end_idthandle;
    extern unsigned char debughandle, end_debughandle;
@@ -598,14 +603,14 @@
    struct realidt *idts = (struct realidt *) 0;
    int codesize = &end_idthandle - &idthandle;
    unsigned char *intbyte, *codeptr;
-	
+
    // for each int, we create a customized little handler
-	// that just pushes %ax, puts the int # in %al, 
-	// then calls the common interrupt handler. 
-	// this necessitated because intel didn't know much about 
+	// that just pushes %ax, puts the int # in %al,
+	// then calls the common interrupt handler.
+	// this necessitated because intel didn't know much about
    // architecture when they did the 8086 (it shows)
    // (hmm do they know anymore even now :-)
-	// obviously you can see I don't really care about memory 
+	// obviously you can see I don't really care about memory
    // efficiency. If I did I would probe back through the stack
    // and get it that way. But that's really disgusting.
    for (i = 0; i < 256; i++) {
@@ -616,11 +621,11 @@
    	intbyte = codeptr + 3;
    	*intbyte = i;
    }
-	
+
    // fixed entry points
-	
+
    // VGA BIOSes tend to hardcode f000:f065 as the previous handler of
-	// int10. 
+	// int10.
    // calling convention here is the same as INTs, we can reuse
    // the int entry code.
    codeptr = (unsigned char*) 0xff065;
@@ -649,15 +654,15 @@
 };

// errors go in AH. Just set these up so that word assigns
-// will work. KISS. 
+// will work. KISS.
 enum {
    PCIBIOS_NODEV = 0x8600,
    PCIBIOS_BADREG = 0x8700
 };

int
-pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, 
-	unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, 
+pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+	unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
    unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
 {
    unsigned long edi = *pedi;
@@ -675,7 +680,7 @@
    short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */
    unsigned char bus;
    device_t dev;
-	
+
    switch(func) {
    case  CHECK:
    	*pedx = 0x4350;
@@ -697,7 +702,7 @@
    		unsigned short busdevfn;
    		*peax = 0;
    		// busnum is an unsigned char;
-			// devfn is an int, so we mask it off. 
+			// devfn is an int, so we mask it off.
    		busdevfn = (dev->bus->secondary << 8)
    			| (dev->path.u.pci.devfn & 0xff);
    		printk_debug("0x%x: return 0x%x\n", func, busdevfn);
@@ -720,7 +725,7 @@
    	unsigned short word;
    	unsigned char byte;
    	unsigned char reg;
-		
+
    	devfn = *pebx & 0xff;
    	bus = *pebx >> 8;
    	reg = *pedi;
@@ -757,11 +762,11 @@
    		pci_write_config32(dev, reg, dword);
    		break;
    	}
-		
-		if (retval) 
+
+		if (retval)
    		retval = PCIBIOS_BADREG;
    	printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
-			     func, bus, devfn, reg, *pecx);
+				 func, bus, devfn, reg, *pecx);
    	*peax = 0;
    	retval = 0;
    }
@@ -770,9 +775,9 @@
    	printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
    	break;
    }
-	
+
    return retval;
-} 
+}

int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
    	unsigned long *esp, unsigned long *ebx, unsigned long *edx,
@@ -801,8 +806,8 @@
    case 0x5f02:
    	*eax=0x5f;
    	*ebx= (*ebx & 0xffff0000) | 2;
-		*ecx= (*ecx & 0xffff0000) | 0x401;  // PAL + crt only 
-		*edx= (*edx & 0xffff0000) | 0;  // TV Layout - default
+		*ecx= (*ecx & 0xffff0000) | 0x401;	// PAL + crt only
+		*edx= (*edx & 0xffff0000) | 0;	// TV Layout - default
    	res=0;
    	break;
    case 0x5f0f:
Index: LinuxBIOSv2/src/include/cpu/amd/geode_post_code.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/include/cpu/amd/geode_post_code.h	2007-05-01 12:09:15.000000000 -0600
@@ -0,0 +1,196 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/
+/* standard AMD post definitions -- might as well use them. */
+#define POST_Output_Port				(0x080)	/*	port to write post codes to*/
+
+#define POST_preSioInit					(0x000)	/* geode.asm*/
+#define POST_clockInit					(0x001)	/* geode.asm*/
+#define POST_CPURegInit					(0x002)	/* geode.asm*/
+#define POST_UNREAL						(0x003)	/* geode.asm*/
+#define POST_CPUMemRegInit				(0x004)	/* geode.asm*/
+#define POST_CPUTest					(0x005)	/* geode.asm*/
+#define POST_memSetup					(0x006)	/* geode.asm*/
+#define POST_memSetUpStack				(0x007)	/* geode.asm*/
+#define POST_memTest					(0x008)	/* geode.asm*/
+#define POST_shadowRom					(0x009)	/* geode.asm*/
+#define POST_memRAMoptimize				(0x00A)	/* geode.asm*/
+#define POST_cacheInit					(0x00B)	/* geode.asm*/
+#define POST_northBridgeInit			(0x00C)	/* geode.asm*/
+#define POST_chipsetInit				(0x00D)	/* geode.asm*/
+#define POST_sioTest					(0x00E)	/* geode.asm*/
+#define POST_pcATjunk					(0x00F)	/* geode.asm*/
+
+
+#define POST_intTable					(0x010)	/* geode.asm*/
+#define POST_memInfo					(0x011)	/* geode.asm*/
+#define POST_romCopy					(0x012)	/* geode.asm*/
+#define POST_PLLCheck					(0x013)	/* geode.asm*/
+#define POST_keyboardInit				(0x014)	/* geode.asm*/
+#define POST_cpuCacheOff				(0x015)	/* geode.asm*/
+#define POST_BDAInit					(0x016)	/* geode.asm*/
+#define POST_pciScan					(0x017)	/* geode.asm*/
+#define POST_optionRomInit				(0x018)	/* geode.asm*/
+#define POST_ResetLimits				(0x019)	/* geode.asm*/
+#define POST_summary_screen				(0x01A)	/* geode.asm*/
+#define POST_Boot						(0x01B)	/* geode.asm*/
+#define POST_SystemPreInit				(0x01C)	/* geode.asm*/
+#define POST_ClearRebootFlag			(0x01D)	/* geode.asm*/
+#define POST_GLIUInit					(0x01E)	/* geode.asm*/
+#define POST_BootFailed					(0x01F)	/* geode.asm*/
+
+
+#define POST_CPU_ID						(0x020)	/* cpucpuid.asm*/
+#define POST_COUNTERBROKEN				(0x021)	/* pllinit.asm*/
+#define POST_DIFF_DIMMS					(0x022)	/* pllinit.asm*/
+#define POST_WIGGLE_MEM_LINES			(0x023)	/* pllinit.asm*/
+#define POST_NO_GLIU_DESC				(0x024)	/* pllinit.asm*/
+#define POST_CPU_LCD_CHECK				(0x025)	/* pllinit.asm*/
+#define POST_CPU_LCD_PASS				(0x026)	/* pllinit.asm*/
+#define POST_CPU_LCD_FAIL				(0x027)	/* pllinit.asm*/
+#define POST_CPU_STEPPING				(0x028)	/* cpucpuid.asm*/
+#define POST_CPU_DM_BIST_FAILURE		(0x029)	/* gx2reg.asm*/
+#define POST_CPU_FLAGS					(0x02A)	/* cpucpuid.asm*/
+#define POST_CHIPSET_ID					(0x02b)	/* chipset.asm*/
+#define POST_CHIPSET_ID_PASS			(0x02c)	/* chipset.asm*/
+#define POST_CHIPSET_ID_FAIL			(0x02d)	/* chipset.asm*/
+#define POST_CPU_ID_GOOD				(0x02E)	/* cpucpuid.asm*/
+#define POST_CPU_ID_FAIL				(0x02F)	/* cpucpuid.asm*/
+
+
+
+/*	PCI config*/
+#define P80_PCICFG					(0x030)	/*	pcispace.asm*/
+
+
+/*	PCI io*/
+#define P80_PCIIO					(0x040)	/*	pcispace.asm*/
+
+
+/*	PCI memory*/
+#define P80_PCIMEM					(0x050)	/*	pcispace.asm*/
+
+
+/*	SIO*/
+#define P80_SIO						(0x060)		/*	*sio.asm*/
+
+/*	Memory Setp*/
+#define P80_MEM_SETUP				(0x070)	/* docboot meminit*/
+#define POST_MEM_SETUP				(0x070)	/* memsize.asm*/
+#define ERROR_32BIT_DIMMS			(0x071)	/* memsize.asm*/
+#define POST_MEM_SETUP2				(0x072)	/* memsize.asm*/
+#define POST_MEM_SETUP3				(0x073)	/* memsize.asm*/
+#define POST_MEM_SETUP4				(0x074)	/* memsize.asm*/
+#define POST_MEM_SETUP5				(0x075)	/* memsize.asm*/
+#define POST_MEM_ENABLE				(0x076)	/* memsize.asm*/
+#define ERROR_NO_DIMMS				(0x077)	/* memsize.asm*/
+#define ERROR_DIFF_DIMMS			(0x078)	/* memsize.asm*/
+#define ERROR_BAD_LATENCY			(0x079)	/* memsize.asm*/
+#define ERROR_SET_PAGE				(0x07a)	/* memsize.asm*/
+#define ERROR_DENSITY_DIMM			(0x07b)	/* memsize.asm*/
+#define ERROR_UNSUPPORTED_DIMM		(0x07c)	/* memsize.asm*/
+#define ERROR_BANK_SET				(0x07d)	/* memsize.asm*/
+#define POST_MEM_SETUP_GOOD			(0x07E)	/* memsize.asm*/
+#define POST_MEM_SETUP_FAIL			(0x07F)	/* memsize.asm*/
+
+
+#define POST_UserPreInit				(0x080)	/* geode.asm*/
+#define POST_UserPostInit				(0x081)	/* geode.asm*/
+#define POST_Equipment_check			(0x082)	/* geode.asm*/
+#define POST_InitNVRAMBX				(0x083)	/* geode.asm*/
+#define POST_NoPIRTable					(0x084)	/* pci.asm*/
+#define POST_ChipsetFingerPrintPass		(0x085)	/*	prechipsetinit*/
+#define POST_ChipsetFingerPrintFail		(0x086)	/*	prechipsetinit*/
+#define POST_CPU_IM_TAG_BIST_FAILURE	(0x087)	/*	gx2reg.asm*/
+#define POST_CPU_IM_DATA_BIST_FAILURE	(0x088)	/*	gx2reg.asm*/
+#define POST_CPU_FPU_BIST_FAILURE		(0x089)	/*	gx2reg.asm*/
+#define POST_CPU_BTB_BIST_FAILURE		(0x08a)	/*	gx2reg.asm*/
+#define POST_CPU_EX_BIST_FAILURE		(0x08b)	/*	gx2reg.asm*/
+#define POST_Chipset_PI_Test_Fail			(0x08c)	/*	prechipsetinit*/
+#define POST_Chipset_SMBus_SDA_Test_Fail	(0x08d)	/*	prechipsetinit*/
+#define POST_BIT_CLK_Fail				(0x08e)	/*	Hawk geode.asm override*/
+
+
+#define POST_STACK_SETUP				(0x090)	/* memstack.asm*/
+#define POST_CPU_PF_BIST_FAILURE		(0x091)	/*	gx2reg.asm*/
+#define POST_CPU_L2_BIST_FAILURE		(0x092)	/*	gx2reg.asm*/
+#define POST_CPU_GLCP_BIST_FAILURE		(0x093)	/*	gx2reg.asm*/
+#define POST_CPU_DF_BIST_FAILURE		(0x094)	/*	gx2reg.asm*/
+#define POST_CPU_VG_BIST_FAILURE		(0x095)	/*	gx2reg.asm*/
+#define POST_CPU_VIP_BIST_FAILURE		(0x096)	/*	gx2reg.asm*/
+#define POST_STACK_SETUP_PASS			(0x09E)	/* memstack.asm*/
+#define POST_STACK_SETUP_FAIL			(0x09F)	/* memstack.asm*/
+
+
+#define POST_PLL_INIT					(0x0A0)	/* pllinit.asm*/
+#define POST_PLL_MANUAL					(0x0A1)	/* pllinit.asm*/
+#define POST_PLL_STRAP					(0x0A2)	/* pllinit.asm*/
+#define POST_PLL_RESET_FAIL				(0x0A3)	/* pllinit.asm*/
+#define POST_PLL_PCI_FAIL				(0x0A4)	/* pllinit.asm*/
+#define POST_PLL_MEM_FAIL				(0x0A5)	/* pllinit.asm*/
+#define POST_PLL_CPU_VER_FAIL			(0x0A6)	/* pllinit.asm*/
+
+
+#define POST_MEM_TESTMEM			(0x0B0)	/* memtest.asm*/
+#define POST_MEM_TESTMEM1			(0x0B1)	/* memtest.asm*/
+#define POST_MEM_TESTMEM2			(0x0B2)	/* memtest.asm*/
+#define POST_MEM_TESTMEM3			(0x0B3)	/* memtest.asm*/
+#define POST_MEM_TESTMEM4			(0x0B4)	/* memtest.asm*/
+#define POST_MEM_TESTMEM_PASS		(0x0BE)	/* memtest.asm*/
+#define POST_MEM_TESTMEM_FAIL		(0x0BF)	/* memtest.asm*/
+
+
+#define POST_SECUROM_SECBOOT_START		(0x0C0)	/* secstart.asm*/
+#define POST_SECUROM_BOOTSRCSETUP		(0x0C1)	/* secstart.asm*/
+#define POST_SECUROM_REMAP_FAIL			(0x0C2)	/* secstart.asm*/
+#define POST_SECUROM_BOOTSRCSETUP_FAIL	(0x0C3)	/* secstart.asm*/
+#define POST_SECUROM_DCACHESETUP		(0x0C4)	/* secstart.asm*/
+#define POST_SECUROM_DCACHESETUP_FAIL	(0x0C5)	/* secstart.asm*/
+#define POST_SECUROM_ICACHESETUP		(0x0C6)	/* secstart.asm*/
+#define POST_SECUROM_DESCRIPTORSETUP	(0x0C7)	/* secstart.asm*/
+#define POST_SECUROM_DCACHESETUPBIOS	(0x0C8)	/* secstart.asm*/
+#define POST_SECUROM_PLATFORMSETUP		(0x0C9)	/* secstart.asm*/
+#define POST_SECUROM_SIGCHECKBIOS		(0x0CA)	/* secstart.asm*/
+#define POST_SECUROM_ICACHESETUPBIOS	(0x0CB)	/* secstart.asm*/
+#define POST_SECUROM_PASS				(0x0CC)	/* secstart.asm*/
+#define POST_SECUROM_FAIL				(0x0CD)	/* secstart.asm*/
+
+#define POST_RCONFInitError				(0x0CE)	/* cache.asm*/
+#define POST_CacheInitError				(0x0CF)	/* cache.asm*/
+
+
+#define POST_ROM_PREUNCOMPRESS			(0x0D0)	/* rominit.asm*/
+#define POST_ROM_UNCOMPRESS				(0x0D1)	/* rominit.asm*/
+#define POST_ROM_SMM_INIT				(0x0D2)	/* rominit.asm*/
+#define POST_ROM_VID_BIOS				(0x0D3)	/* rominit.asm*/
+#define POST_ROM_LCDINIT				(0x0D4)	/* rominit.asm*/
+#define POST_ROM_SPLASH					(0x0D5)	/* rominit.asm*/
+#define POST_ROM_HDDINIT				(0x0D6)	/* rominit.asm*/
+#define POST_ROM_SYS_INIT				(0x0D7)	/* rominit.asm*/
+#define POST_ROM_DMM_INIT				(0x0D8)	/* rominit.asm*/
+#define POST_ROM_TVINIT					(0x0D9)	/* rominit.asm*/
+#define POST_ROM_POSTUNCOMPRESS			(0x0DE)
+
+
+#define P80_CHIPSET_INIT				(0x0E0)	/* chipset.asm*/
+#define POST_PreChipsetInit				(0x0E1)	/* geode.asm*/
+#define POST_LateChipsetInit			(0x0E2)	/* geode.asm*/
+#define POST_NORTHB_INIT				(0x0E8)	/* northb.asm*/
+
+
+#define POST_INTR_SEG_JUMP				(0x0F0)	/* vector.asm*/
Index: LinuxBIOSv2/src/include/cpu/amd/lxdef.h
===================================================================
--- LinuxBIOSv2.orig/src/include/cpu/amd/lxdef.h	2007-04-30 15:25:28.000000000 -0600
+++ LinuxBIOSv2/src/include/cpu/amd/lxdef.h	2007-05-01 12:09:15.000000000 -0600
@@ -1,41 +1,25 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
 #ifndef CPU_AMD_LXDEF_H
 #define CPU_AMD_LXDEF_H
-#define	CPU_ID_1_X							0x540		/* Stepping ID 1.x*/
-#define	CPU_ID_2_0							0x551		/* Stepping ID 2.0*/
-#define	CPU_ID_2_1							0x552		/* Stepping ID 2.1*/
-#define	CPU_ID_2_2							0x553		/* Stepping ID 2.2*/
-
-#define	CPU_REV_1_0							0x011
-#define	CPU_REV_1_1							0x012
-#define	CPU_REV_1_2							0x013
-#define	CPU_REV_1_3							0x014
-#define	CPU_REV_2_0							0x020
-#define	CPU_REV_2_1							0x021
-#define	CPU_REV_2_2							0x022
-#define	CPU_REV_3_0							0x030
-/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
-#define	GLCP_CLK_DIS_DELAY	0x4c000008
-#define	GLCP_PMCLKDISABLE	0x4c000009
-#define	GLCP_CHIP_REVID		0x4c000017
-
-/* GLCP_SYS_RSTPLL, Upper 32 bits */
-#define	GLCP_SYS_RSTPLL_MDIV_SHIFT   9
-#define	GLCP_SYS_RSTPLL_VDIV_SHIFT   6
-#define	GLCP_SYS_RSTPLL_FBDIV_SHIFT  0
-
-/* GLCP_SYS_RSTPLL, Lower 32 bits */
-#define	GLCP_SYS_RSTPLL_SWFLAGS_SHIFT	26
-#define	GLCP_SYS_RSTPLL_SWFLAGS_MASK 	(0x3f << 26)
-
-#define	GLCP_SYS_RSTPLL_LOCKWAIT	24
-#define	GLCP_SYS_RSTPLL_HOLDCOUNT	16
-#define	GLCP_SYS_RSTPLL_BYPASS		15
-#define	GLCP_SYS_RSTPLL_PD		14
-#define	GLCP_SYS_RSTPLL_RESETPLL	13
-#define	GLCP_SYS_RSTPLL_DDRMODE		10
-#define	GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE   9
-#define	GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE  8
-#define	GLCP_SYS_RSTPLL_CHIP_RESET	    0
+
+#define CPU_ID_1_X						0x00000560		/* Stepping ID 1.x CPUbug fix to change it to 5A0*/
+#define CPU_ID_2_0						0x000005A1
+#define CPU_ID_3_0						0x000005A2
+
+#define CPU_REV_1_0						0x010
+#define CPU_REV_1_1						0x011
+#define CPU_REV_2_0						0x020
+#define CPU_REV_2_1						0x021
+#define CPU_REV_2_2						0x022
+#define CPU_REV_C_0						0x030
+#define CPU_REV_C_1						0x031
+#define CPU_REV_C_2						0x032			/* 3.2 part was never produced ...*/
+#define CPU_REV_C_3						0x033
+

/* MSR routing as follows*/
 /* MSB = 1 means not for CPU*/
@@ -43,80 +27,57 @@
 /* next3 bits next port if through an GLIU*/
 /* etc...*/

-/*Redcloud as follows.*/
-/* GLIU0*/
-/*	port0 - GLIU0*/
-/*	port1 - MC*/
-/*	port2 - GLIU1*/
-/*	port3 - CPU*/
-/*	port4 - VG*/
-/*	port5 - GP*/
-/*	port6 - DF*/
-
-/* GLIU1*/
-/*	port1 - GLIU0*/
-/*	port3 - GLCP*/
-/*	port4 - PCI*/
-/*	port5 - FG*/
-
-
-/*          start GX3 def,  differences are marked with GX3 comment      */
-
-#define	GL0_GLIU0			0
-#define	GL0_MC				1
-#define	GL0_GLIU1			2
-#define	GL0_CPU				3
-#define	GL0_VG				4
-#define	GL0_GP				5
-//#define	GL0_DF				6		//GX3 no such thing as VP port
-
-#define	GL1_GLIU0			1
-//GX3 VP port
-#define	GL1_DF				2
-#define	GL1_GLCP			3
-#define	GL1_PCI				4
-#define GL1_VIP				5
-#define GL1_AES				6
-
-#define	MSR_GLIU0			(GL0_GLIU0 << 29) + (1 << 28)	/* 1000xxxx - To get on GeodeLink one bit has to be set */
-#define	MSR_MC				(GL0_MC		<< 29)	/* 2000xxxx */
-#define	MSR_GLIU1			(GL0_GLIU1	<< 29)	/* 4000xxxx */
-#define	MSR_CPU				(GL0_CPU	<< 32)	/* 0000xxxx - this is not used for BIOS */	//GX3
-#define	MSR_VG				(GL0_VG		<< 29)	/* 8000xxxx */
-#define	MSR_GP				(GL0_GP		<< 29)	/* A000xxxx */
-//#define	MSR_DF				(GL0_DF		<< 29)	/* C000xxxx */  //GX3 no such thing
-
-#define	MSR_GLCP			(GL1_GLCP << 26) + MSR_GLIU1	/* 4C00xxxx */
-#define	MSR_PCI				(GL1_PCI << 26) + MSR_GLIU1	/* 5000xxxx */
-//#define	MSR_FG				(GL1_FG << 26) + MSR_GLIU1	/* 5400xxxx */		//GX3: no such thing
-#define MSR_VIP				((GL1_VIP << 26) + MSR_GLIU1)	/* 5400xxxx */
-#define MSR_AES				((GL1_AES << 26) + MSR_GLIU1)	/* 5800xxxx */
-/* South Bridge*/
-#define SB_PORT	2			/* port of the SouthBridge */
-#define	MSR_SB				((SB_PORT << 23) + MSR_PCI)	/* 5100xxxx - address to the SouthBridge*/
-#define	SB_SHIFT			20							/* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/
-
-
-/**/
-/*GeodeLink Interface Unit 0 (GLIU0) port0*/
-/**/
-
-#define	GLIU0_GLD_MSR_CAP			(MSR_GLIU0 + 0x2000)
-#define	GLIU0_GLD_MSR_PM			(MSR_GLIU0 + 0x2004)
-
-#define	GLIU0_DESC_BASE				(MSR_GLIU0 + 0x20)
-#define	GLIU0_CAP					(MSR_GLIU0 + 0x86)
-#define	GLIU0_GLD_MSR_COH			(MSR_GLIU0 + 0x80)
-
-
-/**/
-/* Memory Controller GLIU0 port 1*/
-/**/
-#define	MC_GLD_MSR_CAP			(MSR_MC + 0x2000)
-#define	MC_GLD_MSR_PM			(MSR_MC + 0x2004)
+/* GLIU0 ports */
+#define GL0_GLIU0		0
+#define GL0_MC			1
+#define GL0_GLIU1		2
+#define GL0_CPU			3
+#define GL0_VG			4
+#define GL0_GP			5
+
+/* GLIU1 ports */
+#define GL1_GLIU0		1
+#define GL1_DF			2
+#define GL1_GLCP		3
+#define GL1_PCI			4
+#define GL1_VIP			5
+#define GL1_AES			6
+
+
+#define MSR_GLIU0		(GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx, To get on GeodeLink one bit has to be set */
+#define MSR_MC			(GL0_MC		<< 29)	/* 2000xxxx */
+#define MSR_GLIU1		(GL0_GLIU1	<< 29)	/* 4000xxxx */
+#define MSR_CPU			(GL0_CPU	<< 29)	/* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/
+#define MSR_VG			(GL0_VG		<< 29)	/* 8000xxxx */
+#define MSR_GP			(GL0_GP		<< 29)	/* A000xxxx */
+
+#define MSR_DF			((GL1_DF << 26) + MSR_GLIU1)		/* 4800xxxx */
+#define MSR_GLCP		((GL1_GLCP << 26) + MSR_GLIU1)		/* 4C00xxxx */
+#define MSR_PCI			((GL1_PCI << 26) + MSR_GLIU1)		/* 5000xxxx */
+#define MSR_VIP			((GL1_VIP << 26) + MSR_GLIU1)		/* 5400xxxx */
+#define MSR_AES			((GL1_AES << 26) + MSR_GLIU1)		/* 5800xxxx */
+#define MSR_FG			MSR_GLCP
+
+/*GeodeLink Interface Unit 0 (GLIU0) port0 */
+
+#define GLIU0_GLD_MSR_CAP		(MSR_GLIU0 + 0x2000)
+#define GLIU0_GLD_MSR_ERROR		(MSR_GLIU0 + 0x2003)
+#define GLIU0_GLD_MSR_PM		(MSR_GLIU0 + 0x2004)
+
+#define GLIU0_DESC_BASE			(MSR_GLIU0 + 0x20)
+#define GLIU0_CAP				(MSR_GLIU0 + 0x86)
+#define GLIU0_GLD_MSR_COH		(MSR_GLIU0 + 0x80)
+#define GLIU0_ARB				(MSR_GLIU0 + 0x82)
+#define		ARB_UPPER_QUACK_EN_SET			(1 << 31)
+#define		ARB_UPPER_DACK_EN_SET			(1 << 28)
+

-#define	MC_CF07_DATA			(MSR_MC + 0x18)
+/* Memory Controller GLIU0 port 1 */

+#define MC_GLD_MSR_CAP		(MSR_MC + 0x2000)
+#define MC_GLD_MSR_PM		(MSR_MC + 0x2004)
+
+#define MC_CF07_DATA		(MSR_MC + 0x18)
 #define		CF07_UPPER_D1_SZ_SHIFT				28
 #define		CF07_UPPER_D1_MB_SHIFT				24
 #define		CF07_UPPER_D1_CB_SHIFT				20
@@ -126,7 +87,7 @@
 #define		CF07_UPPER_D0_CB_SHIFT				4
 #define		CF07_UPPER_D0_PSZ_SHIFT				0

-#define		CF07_LOWER_REF_INT_SHIFT				8
+#define		CF07_LOWER_REF_INT_SHIFT			8
 #define		CF07_LOWER_LOAD_MODE_DDR_SET		(1 << 28)
 #define		CF07_LOWER_LOAD_MODE_DLL_RESET		(1 << 27)
 #define		CF07_LOWER_EMR_QFC_SET				(1 << 26)
@@ -135,366 +96,417 @@
 #define		CF07_LOWER_PROG_DRAM_SET			(1 << 0)

-#define	MC_CF8F_DATA			(MSR_MC + 0x19)
-
-#define		CF8F_UPPER_XOR_BS_SHIFT				19
-#define		CF8F_UPPER_XOR_MB0_SHIFT			18
-#define		CF8F_UPPER_XOR_BA1_SHIFT			17
-#define		CF8F_UPPER_XOR_BA0_SHIFT			16
+#define MC_CF8F_DATA		(MSR_MC + 0x19)
+#define		CF8F_UPPER_XOR_BS_SHIFT			19
+#define		CF8F_UPPER_XOR_MB0_SHIFT		18
+#define		CF8F_UPPER_XOR_BA1_SHIFT		17
+#define		CF8F_UPPER_XOR_BA0_SHIFT		16
 #define		CF8F_UPPER_REORDER_DIS_SET		(1 << 8)
-#define		CF8F_UPPER_REG_DIMM_SHIFT			4
-#define		CF8F_LOWER_CAS_LAT_SHIFT			28
-#define		CF8F_LOWER_REF2ACT_SHIFT			24
-#define		CF8F_LOWER_ACT2PRE_SHIFT			20
-#define		CF8F_LOWER_PRE2ACT_SHIFT			16
-#define		CF8F_LOWER_ACT2CMD_SHIFT			12
-#define		CF8F_LOWER_ACT2ACT_SHIFT			8
-#define		CF8F_UPPER_32BIT_SET				(1 << 5)
+#define		CF8F_LOWER_CAS_LAT_SHIFT		28
+#define		CF8F_LOWER_ACT2ACTREF_SHIFT		24
+#define		CF8F_LOWER_ACT2PRE_SHIFT		20
+#define		CF8F_LOWER_PRE2ACT_SHIFT		16
+#define		CF8F_LOWER_ACT2CMD_SHIFT		12
+#define		CF8F_LOWER_ACT2ACT_SHIFT		8
 #define		CF8F_UPPER_HOI_LOI_SET			(1 << 1)

-#define	MC_CF1017_DATA			(MSR_MC + 0x1A)
-
+#define MC_CF1017_DATA		(MSR_MC + 0x1A)
+#define		CF1017_LOWER_WR_TO_RD_SHIFT			28
+#define		CF1017_LOWER_RD_TMG_CTL_SHIFT		24
+#define		CF1017_LOWER_REF2ACT_SHIFT			16
 #define		CF1017_LOWER_PM1_UP_DLY_SET			(1 << 8)
 #define		CF1017_LOWER_WR2DAT_SHIFT			0

-#define	MC_CFCLK_DBUG			(MSR_MC + 0x1D)
+#define MC_CFCLK_DBUG		(MSR_MC + 0x1D)

-#define		CFCLK_UPPER_MTST_B2B_DIS_SET			(1 << 2)
-#define		CFCLK_UPPER_MTST_DQS_EN_SET			(1 << 1)
-#define		CFCLK_UPPER_MTEST_EN_SET				(1 << 0)
+#define		CFCLK_UPPER_MTST_B2B_DIS_SET		(1 << 2)
+#define		CFCLK_UPPER_MTST_RBEX_EN_SET		(1 << 1)
+#define		CFCLK_UPPER_MTEST_EN_SET			(1 << 0)

+#define		CFCLK_LOWER_FORCE_PRE_SET			(1 << 16)
+#define		CFCLK_LOWER_TRISTATE_DIS_SET		(1 << 12)
 #define		CFCLK_LOWER_MASK_CKE_SET1			(1 << 9)
 #define		CFCLK_LOWER_MASK_CKE_SET0			(1 << 8)
 #define		CFCLK_LOWER_SDCLK_SET				(0x0F << 0)

-#define	MC_CF_RDSYNC			(MSR_MC	+ 0x1F)
+#define MC_CF_RDSYNC		(MSR_MC + 0x1F)
+#define MC_CF_PMCTR			(MSR_MC + 0x20)
+
+
+/* GLIU1 GLIU0 port2 */
+
+#define GLIU1_GLD_MSR_CAP		(MSR_GLIU1 + 0x2000)
+#define GLIU1_GLD_MSR_ERROR		(MSR_GLIU1 + 0x2003)
+#define GLIU1_GLD_MSR_PM		(MSR_GLIU1 + 0x2004)
+
+#define GLIU1_GLD_MSR_COH		(MSR_GLIU1 + 0x80)
+#define GLIU1_PORT_ACTIVE		(MSR_GLIU1 + 0x81)
+#define GLIU1_ARB				(MSR_GLIU1 + 0x82)
+
+
+
+/* CPU	; does not need routing instructions since we are executing there. */
+
+#define CPU_GLD_MSR_CAP					0x2000
+#define CPU_GLD_MSR_CONFIG				0x2001
+#define CPU_GLD_MSR_PM					0x2004
+
+#define CPU_GLD_MSR_DIAG				0x2005
+#define		DIAG_SEL1_MODE_SHIFT			16
+#define		DIAG_SEL1_SET					(1 << 31)
+#define		DIAG_SEL0__MODE_SHIFT			0
+#define		DIAG_SET0_SET					(1 << 15)

+#define CPU_PF_CONF						0x1100
+#define		RETURN_STACK_ENABLE_SET			(1 << 4)
+#define		PF_CONF_CC_L1					(1 << 0)
+#define CPU_PF_INVD						0x1102
+#define		PF_RS_INVD_SET					(1 << 1)
+#define		PF_CC_INVD_SET					(1 << 0)
+#define CPU_PF_BIST						0x1140

-/**/
-/* GLIU1 GLIU0 port2*/
-/**/
-#define	GLIU1_GLD_MSR_CAP			(MSR_GLIU1 + 0x2000)
-#define	GLIU1_GLD_MSR_PM			(MSR_GLIU1 + 0x2004)
-
-#define	GLIU1_GLD_MSR_COH			(MSR_GLIU1 + 0x80)
-
-
-/**/
-/* CPU	; does not need routing instructions since we are executing there.*/
-/**/
-#define	CPU_GLD_MSR_CAP						0x2000
-#define	CPU_GLD_MSR_CONFIG					0x2001
-#define	CPU_GLD_MSR_PM						0x2004
-
-#define	CPU_GLD_MSR_DIAG					0x2005
-#define		DIAG_SEL1_MODE_SHIFT				16
-#define		DIAG_SEL1_SET						(1 << 31)
-#define		DIAG_SEL0__MODE_SHIFT				0
-#define		DIAG_SET0_SET						(1 << 15)
-
-#define	CPU_PF_BTB_CONF						0x1100
-#define		BTB_ENABLE_SET						(1 << 0)
-#define		RETURN_STACK_ENABLE_SET				(1 << 4)
-#define	CPU_PF_BTBRMA_BIST					0x110C
-
-#define	CPU_XC_CONFIG						0x1210
-#define		XC_CONFIG_SUSP_ON_HLT				(1 << 0)
-#define	CPU_ID_CONFIG						0x1250
-#define		ID_CONFIG_SERIAL_SET				(1 << 0)
+#define CPU_XC_CONFIG					0x1210
+#define		XC_CONFIG_SUSP_ON_HLT			(1 << 0)
+#define		XC_CONFIG_SUSP_ON_PAUSE			(1 << 1)

-#define	CPU_AC_MSR							0x1301
-#define	CPU_EX_BIST							0x1428
+#define CPU_ID_CONFIG					0x1250
+#define		ID_CONFIG_SERIAL_SET			(1 << 0)
+
+#define CPU_AC_MSR						0x1301
+
+/* SMM*/
+#define CPU_AC_SMM_CTL					0x1301
+#define		SMM_NMI_EN_SET					(1 << 0)
+#define		SMM_SUSP_EN_SET					(1 << 1)
+#define		NEST_SMI_EN_SET					(1 << 2)
+#define		SMM_INST_EN_SET					(1 << 3)
+#define		INTL_SMI_EN_SET					(1 << 4)
+#define		EXTL_SMI_EN_SET					(1 << 5)
+
+#define CPU_EX_BIST						0x1428

/*IM*/
-#define	CPU_IM_CONFIG							0x1700
-#define		IM_CONFIG_LOWER_ICD_SET					(1 << 8)
-#define		IM_CONFIG_LOWER_QWT_SET					(1 << 20)
-#define	CPU_IC_INDEX							0x1710
-#define	CPU_IC_DATA								0x1711
-#define	CPU_IC_TAG								0x1712
-#define	CPU_IC_TAG_I							0x1713
-#define	CPU_ITB_INDEX							0x1720
-#define	CPU_ITB_LRU								0x1721
-#define	CPU_ITB_ENTRY							0x1722
-#define	CPU_ITB_ENTRY_I							0x1723
-#define	CPU_IM_BIST_TAG							0x1730
-#define	CPU_IM_BIST_DATA						0x1731
-
-
-/*  ----- GX3 OK  ----  */
-
-/* various CPU MSRs */
-#define CPU_DM_CONFIG0 0x1800
-#define	DM_CONFIG0_UPPER_WSREQ_SHIFT  12
-#define	DM_CONFIG0_LOWER_DCDIS_SET		(1<<8)
-#define	DM_CONFIG0_LOWER_WBINVD_SET	(1<<5)
-#define	DM_CONFIG0_LOWER_MISSER_SET		(1<<1)
-
-#define CPU_DM_CONFIG1							0x1801
-
-#define CPU_DM_PFLOCK							0x1804
-
-/* configuration MSRs */
-#define	CPU_RCONF_DEFAULT						0x1808
-#define		RCONF_DEFAULT_UPPER_ROMRC_SHIFT				24
-#define		RCONF_DEFAULT_UPPER_ROMBASE_SHIFT			4
-#define		RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT			0
-#define		RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT			28
-#define		RCONF_DEFAULT_LOWER_SYSTOP_SHIFT			8
-#define		RCONF_DEFAULT_LOWER_SYSRC_SHIFT				0
-
-
-#define	CPU_RCONF_BYPASS						0x180A
-#define	CPU_RCONF_A0_BF							0x180B
-#define	CPU_RCONF_C0_DF							0x180C
-#define	CPU_RCONF_E0_FF							0x180D
-
-/* ------------------------ */
-
-/*  ----- GX3 OK  ----  */
-
-#define	CPU_RCONF_SMM							0x180E
-#define		RCONF_SMM_UPPER_SMMTOP_SHIFT			12
-#define		RCONF_SMM_UPPER_RCSMM_SHIFT				0
-#define		RCONF_SMM_LOWER_SMMBASE_SHIFT			12
-#define		RCONF_SMM_LOWER_RCNORM_SHIFT			0
-#define		RCONF_SMM_LOWER_EN_SET					(1<<8)
-
-/* ------------------------ */
-
-
-#define	CPU_RCONF_DMM							0x180F
-#define		RCONF_DMM_UPPER_DMMTOP_SHIFT			12
-#define		RCONF_DMM_UPPER_RCDMM_SHIFT				0
-#define		RCONF_DMM_LOWER_DMMBASE_SHIFT			12
-#define		RCONF_DMM_LOWER_RCNORM_SHIFT			0
-#define		RCONF_DMM_LOWER_EN_SET					(1<<8)
-
-
-
-/*  ----- GX3 OK  ----  */
-
-#define	CPU_RCONF0							0x1810
-#define	CPU_RCONF1							0x1811
-#define	CPU_RCONF2							0x1812
-#define	CPU_RCONF3							0x1813
-#define	CPU_RCONF4							0x1814
-#define	CPU_RCONF5							0x1815
-#define	CPU_RCONF6							0x1816
-#define	CPU_RCONF7							0x1817
-
-/* ------------------------ */
-
-/*  ----- GX3 OK  ----  */
-
-#define	CPU_CR1_MSR							0x1881
-#define	CPU_CR2_MSR							0x1882
-#define	CPU_CR3_MSR							0x1883
-#define	CPU_CR4_MSR							0x1884
-
-/* ------------------------ */
-
-/*  ----- GX3 OK  ----  */
-
-#define	CPU_DC_INDEX						0x1890
-#define	CPU_DC_DATA							0x1891
-#define	CPU_DC_TAG							0x1892
-#define	CPU_DC_TAG_I						0x1893
-#define	CPU_SNOOP							0x1894
-#define	CPU_DTB_INDEX						0x1898
-#define	CPU_DTB_LRU							0x1899
-#define	CPU_DTB_ENTRY						0x189A
-#define	CPU_DTB_ENTRY_I						0x189B
-
-/* ------------------------ */
-
-#define	CPU_L2TB_INDEX						0x189C
-#define	CPU_L2TB_LRU						0x189D
-#define	CPU_L2TB_ENTRY						0x189E
-#define	CPU_L2TB_ENTRY_I					0x189F
-#define	CPU_DM_BIST							0x18C0
-		/* SMM*/
-#define	CPU_AC_SMM_CTL						0x1301
-#define		SMM_NMI_EN_SET					(1<<0)
-#define		SMM_SUSP_EN_SET					(1<<1)
-#define		NEST_SMI_EN_SET					(1<<2)
-#define		SMM_INST_EN_SET					(1<<3)
-#define		INTL_SMI_EN_SET					(1<<4)
-#define		EXTL_SMI_EN_SET					(1<<5)
-	
-#define	CPU_FPU_MSR_MODE					0x1A00
-#define		FPU_IE_SET						(1<<0)
-	
-#define	CPU_FP_UROM_BIST					0x1A03
-	
-#define	CPU_BC_CONF_0						0x1900
-#define		TSC_SUSP_SET				 (1<<5)
-#define		SUSP_EN_SET				 (1<<12)
-	
-/* L2 cache*/
-
-#define	L2_CONFIG_MSR						0x1920
-#define	L2_STATUS_MSR						0x1921
-#define	L2_BIST_MSR						0x1926
-
-
-
-	
-	/**/
-	/*	VG GLIU0 port4*/
-	/**/
-	
-#define	VG_GLD_MSR_CAP				(MSR_VG + 0x2000)
-#define	VG_GLD_MSR_CONFIG			(MSR_VG + 0x2001)
-#define	VG_GLD_MSR_PM				(MSR_VG + 0x2004)
-
-#define	GP_GLD_MSR_CAP				(MSR_GP + 0x2000)
-#define	GP_GLD_MSR_CONFIG			(MSR_GP + 0x2001)
-#define	GP_GLD_MSR_PM				(MSR_GP + 0x2004)
+#define CPU_IM_CONFIG						0x1700
+#define		IM_CONFIG_LOWER_SERIAL_SET			(1 << 2)
+#define		IM_CONFIG_LOWER_L0WE_SET			(1 << 6)
+#define		IM_CONFIG_LOWER_ICD_SET				(1 << 8)
+#define		IM_CONFIG_LOWER_EBE_SET				(1 << 10)
+#define		IM_CONFIG_LOWER_ABSE_SET			(1 << 11)
+#define		IM_CONFIG_LOWER_QWT_SET				(1 << 20)
+#define CPU_IC_INDEX						0x1710
+#define CPU_IC_DATA							0x1711
+#define CPU_IC_TAG							0x1712
+#define CPU_IC_TAG_I						0x1713
+#define CPU_ITB_INDEX						0x1720
+#define CPU_ITB_LRU							0x1721
+#define CPU_ITB_ENTRY						0x1722
+#define CPU_ITB_ENTRY_I						0x1723
+#define CPU_IM_BIST_TAG						0x1730
+#define CPU_IM_BIST_DATA					0x1731
+
+
+/*DM MSR MAP*/
+#define CPU_DM_CONFIG0						0x1800
+#define		DM_CONFIG0_UPPER_WSREQ_SHIFT		12
+#define		DM_CONFIG0_LOWER_EVCTONRPL_SET		(1 << 14)
+#define		DM_CONFIG0_LOWER_WBINVD_SET			(1 << 5)
+#define		DM_CONFIG0_LOWER_DCDIS_SET			(1 << 8)
+#define		DM_CONFIG0_LOWER_MISSER_SET			(1 << 1)
+
+#define CPU_RCONF_DEFAULT					0x1808
+#define		RCONF_DEFAULT_UPPER_ROMRC_SHIFT			24
+#define		RCONF_DEFAULT_UPPER_ROMBASE_SHIFT		4
+#define		RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT		0
+#define		RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT		28
+#define		RCONF_DEFAULT_LOWER_SYSTOP_SHIFT		8
+#define		RCONF_DEFAULT_LOWER_SYSRC_SHIFT			0
+
+#define CPU_RCONF_BYPASS					0x180A
+#define CPU_RCONF_A0_BF						0x180B
+#define CPU_RCONF_C0_DF						0x180C
+#define CPU_RCONF_E0_FF						0x180D
+
+#define CPU_RCONF_SMM						0x180E
+#define		RCONF_SMM_UPPER_SMMTOP_SHIFT		12
+#define		RCONF_SMM_UPPER_RCSMM_SHIFT			0
+#define		RCONF_SMM_LOWER_SMMBASE_SHIFT		12
+#define		RCONF_SMM_LOWER_RCNORM_SHIFT		0
+#define		RCONF_SMM_LOWER_EN_SET				(1 << 8)
+
+#define CPU_RCONF_DMM						0x180F
+#define		RCONF_DMM_UPPER_DMMTOP_SHIFT		12
+#define		RCONF_DMM_UPPER_RCDMM_SHIFT			0
+#define		RCONF_DMM_LOWER_DMMBASE_SHIFT		12
+#define		RCONF_DMM_LOWER_RCNORM_SHIFT		0
+#define		RCONF_DMM_LOWER_EN_SET				(1 << 8)
+
+#define CPU_RCONF0							0x1810
+#define CPU_RCONF1							0x1811
+#define CPU_RCONF2							0x1812
+#define CPU_RCONF3							0x1813
+#define CPU_RCONF4							0x1814
+#define CPU_RCONF5							0x1815
+#define CPU_RCONF6							0x1816
+#define CPU_RCONF7							0x1817
+#define CPU_CR1_MSR							0x1881
+#define CPU_CR2_MSR							0x1882
+#define CPU_CR3_MSR							0x1883
+#define CPU_CR4_MSR							0x1884
+#define CPU_DC_INDEX						0x1890
+#define CPU_DC_DATA							0x1891
+#define CPU_DC_TAG							0x1892
+#define CPU_DC_TAG_I						0x1893
+#define CPU_SNOOP							0x1894
+#define CPU_DTB_INDEX						0x1898
+#define CPU_DTB_LRU							0x1899
+#define CPU_DTB_ENTRY						0x189A
+#define CPU_DTB_ENTRY_I						0x189B
+#define CPU_L2TB_INDEX						0x189C
+#define CPU_L2TB_LRU						0x189D
+#define CPU_L2TB_ENTRY						0x189E
+#define CPU_L2TB_ENTRY_I					0x189F
+#define CPU_DM_BIST							0x18C0
+
+#define CPU_BC_CONF_0						0x1900
+#define		TSC_SUSP_SET						(1 << 5)
+#define		SUSP_EN_SET							(1 << 12)
+
+#define CPU_BC_CONF_1						0x1901
+#define CPU_BC_MSR_LOCK						0x1908
+#define CPU_BC_L2_CONF						0x1920
+#define		BC_L2_ENABLE_SET					(1 << 0)
+#define		BC_L2_ALLOC_ENABLE_SET				(1 << 1)
+#define		BC_L2_DM_ALLOC_ENABLE_SET			(1 << 2)
+#define		BC_L2_IM_ALLOC_ENABLE_SET			(1 << 3)
+#define		BC_L2_INVALIDATE_SET				(1 << 4)
+#define CPU_BC_L2_STATUS					0x1921
+#define CPU_BC_L2_INDEX						0x1922
+#define CPU_BC_L2_DATA						0x1923
+#define CPU_BC_L2_TAG						0x1924
+#define CPU_BC_L2_TAG_AUTOINC				0x1925
+#define CPU_BC_L2_BIST						0x1926
+#define		BC_L2_BIST_TAG_ENABLE_SET			(1 << 0)
+#define		BC_L2_BIST_TAG_DRT_EN_SET			(1 << 1)
+#define		BC_L2_BIST_DATA_ENABLE_SET			(1 << 2)
+#define		BC_L2_BIST_DATA_DRT_EN_SET			(1 << 3)
+#define		BC_L2_BIST_MRU_ENABLE_SET			(1 << 4)
+#define		BC_L2_BIST_MRU_DRT_EN_SET			(1 << 5)
+#define CPU_BC_PMODE_MSR					0x1930
+#define CPU_BC_MSS_ARRAY_CTL_ENA			0x1980
+#define CPU_BC_MSS_ARRAY_CTL0				0x1981
+#define CPU_BC_MSS_ARRAY_CTL1				0x1982
+#define CPU_BC_MSS_ARRAY_CTL2				0x1983
+
+#define CPU_FPU_MSR_MODE					0x1A00
+#define		FPU_IE_SET							(1 << 0)
+
+#define CPU_FP_UROM_BIST					0x1A03
+
+#define CPU_CPUID0							0x3000
+#define CPU_CPUID1							0x3001
+#define CPU_CPUID2							0x3002
+#define CPU_CPUID3							0x3003
+#define CPU_CPUID4							0x3004
+#define CPU_CPUID5							0x3005
+#define CPU_CPUID6							0x3006
+#define CPU_CPUID7							0x3007
+#define CPU_CPUID8							0x3008
+#define CPU_CPUID9							0x3009
+#define CPU_CPUIDA							0x300A
+#define CPU_CPUIDB							0x300B
+#define CPU_CPUIDC							0x300C
+#define CPU_CPUIDD							0x300D
+#define CPU_CPUIDE							0x300E
+#define CPU_CPUIDF							0x300F
+#define CPU_CPUID10							0x3010
+#define CPU_CPUID11							0x3011
+#define CPU_CPUID12							0x3012
+#define CPU_CPUID13							0x3013
+
+
+
+
+/*	VG GLIU0 port4*/
+
+
+#define VG_GLD_MSR_CAP			(MSR_VG + 0x2000)
+#define VG_GLD_MSR_CONFIG		(MSR_VG + 0x2001)
+#define VG_GLD_MSR_PM			(MSR_VG + 0x2004)
+#define VG_BIST					(MSR_VG + 0x2010)
+
+
+
+/*	GP GLIU0 port5*/
+
+
+#define GP_GLD_MSR_CAP			(MSR_GP + 0x2000)
+#define GP_GLD_MSR_CONFIG		(MSR_GP + 0x2001)
+#define GP_GLD_MSR_PM			(MSR_GP + 0x2004)

-/**/
 /*	DF GLIU0 port6*/
-/**/
-/*
-#define	DF_GLD_MSR_CAP					(MSR_DF + 0x2000)
-#define	DF_GLD_MSR_MASTER_CONF			(MSR_DF + 0x2001)
-#define		DF_LOWER_LCD_SHIFT				6
-#define	DF_GLD_MSR_PM					(MSR_DF + 0x2004)

-*/

-/**/
+#define DF_GLD_MSR_CAP			(MSR_DF + 0x2000)
+#define DF_GLD_MSR_MASTER_CONF	(MSR_DF + 0x2001)
+#define		DF_LOWER_LCD_SHIFT			6
+#define DF_GLD_MSR_PM			(MSR_DF + 0x2004)
+#define DF_BIST					(MSR_DF + 0x2005)
+
+
+
 /* GeodeLink Control Processor GLIU1 port3*/
-/**/
-#define	GLCP_GLD_MSR_CAP			(MSR_GLCP + 0x2000)
-#define	GLCP_GLD_MSR_CONF			(MSR_GLCP + 0x2001)
-#define	GLCP_GLD_MSR_PM				(MSR_GLCP + 0x2004)
-
-#define	GLCP_DELAY_CONTROLS			(MSR_GLCP + 0x0F)
-
-#define	GLCP_SYS_RSTPLL				(MSR_GLCP +0x14	/* R/W*/)
-#define		RSTPLL_UPPER_MDIV_SHIFT				9
-#define		RSTPLL_UPPER_VDIV_SHIFT				6
-#define		RSTPLL_UPPER_FBDIV_SHIFT			0
-	
+
+#define GLCP_GLD_MSR_CAP		(MSR_GLCP + 0x2000)
+#define GLCP_GLD_MSR_CONF		(MSR_GLCP + 0x2001)
+#define GLCP_GLD_MSR_SMI		(MSR_GLCP + 0x2002)
+#define GLCP_GLD_MSR_ERROR		(MSR_GLCP + 0x2003)
+#define GLCP_GLD_MSR_PM			(MSR_GLCP + 0x2004)
+
+#define GLCP_DELAY_CONTROLS		(MSR_GLCP + 0x0F)
+#define GLCP_SYS_RSTPLL			(MSR_GLCP + 0x14)	/* R/W */
+#define		RSTPLL_UPPER_GLMULT_SHIFT			7
+#define		RSTPLL_UPPER_GLDIV_SHIFT			6
+#define		RSTPLL_UPPER_CPUMULT_SHIFT			1
+#define		RSTPLL_UPPER_CPUDIV_SHIFT			0
 #define		RSTPLL_LOWER_SWFLAGS_SHIFT			26
-#define		RSTPLL_LOWER_SWFLAGS_MASK			(0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
+#define		RSTPLL_LOWER_SWFLAGS_MASK			(0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
+#define		RSTPPL_LOWER_HOLD_COUNT_SHIFT		16
+#define		RSTPPL_LOWER_COREBYPASS_SHIFT		12
+#define		RSTPPL_LOWER_GLBYPASS_SHIFT			11
+#define		RSTPPL_LOWER_PCISPEED_SHIFT			7
+#define		RSTPPL_LOWER_BOOTSTRAP_SHIFT		1
+#define		RSTPLL_LOWER_BOOTSTRAP_MASK			(0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT)
+
+#define		RSTPPL_LOWER_GLLOCK_SET				(1 << 25)
+#define		RSTPPL_LOWER_CORELOCK_SET			(1 << 24)
+#define		RSTPPL_LOWER_LOCKWAIT_SET			(1 << 15)
+#define		RSTPPL_LOWER_CLPD_SET				(1 << 14)
+#define		RSTPPL_LOWER_COREPD_SET				(1 << 13)
+#define		RSTPPL_LOWER_MBBYPASS_SET			(1 << 12)
+#define		RSTPPL_LOWER_COREBYPASS_SET			(1 << 11)
+#define		RSTPPL_LOWER_LPFEN_SET				(1 << 10)
+#define		RSTPPL_LOWER_CPU_SEMI_SYNC_SET		(1 << 9)
+#define		RSTPPL_LOWER_PCI_SEMI_SYNC_SET		(1 << 8)
+#define		RSTPPL_LOWER_CHIP_RESET_SET		(1 << 0)
+
+#define GLCP_DOWSER				(MSR_GLCP + 0x0E)
+#define GLCP_DBGCLKCTL			(MSR_GLCP + 0x16)
+#define GLCP_REVID				(MSR_GLCP + 0x17)
+#define GLCP_TH_OD				(MSR_GLCP + 0x1E)
+#define GLCP_FIFOCTL			(MSR_GLCP + 0x5E)
+#define GLCP_BIST				GLCP_FIFOCTL
+
+#define MSR_INIT				(MSR_GLCP + 0x33)
+
+
+/*	GLIU1 port 4*/
+
+#define GLPCI_GLD_MSR_CAP		(MSR_PCI + 0x2000)
+#define GLPCI_GLD_MSR_CONFIG	(MSR_PCI + 0x2001)
+#define GLPCI_GLD_MSR_PM		(MSR_PCI + 0x2004)
+
+#define GLPCI_CTRL		(MSR_PCI + 0x2010)
+#define GLPCI_CTRL_UPPER_FTH_SHIFT				28
+#define GLPCI_CTRL_UPPER_RTH_SHIFT				24
+#define GLPCI_CTRL_UPPER_SBRTH_SHIFT			20
+#define GLPCI_CTRL_UPPER_RTL_SHIFT				17
+#define GLPCI_CTRL_UPPER_DTL_SHIFT				14
+#define GLPCI_CTRL_UPPER_WTO_SHIFT				11
+#define GLPCI_CTRL_UPPER_SLTO_SHIFT				10
+#define GLPCI_CTRL_UPPER_ILTO_SHIFT				8
+#define GLPCI_CTRL_UPPER_LAT_SHIFT				3
+
+#define GLPCI_CTRL_LOWER_IRFT_SHIFT				18
+#define GLPCI_CTRL_LOWER_IRFC_SHIFT				16
+#define GLPCI_CTRL_LOWER_ER_SET					(1 << 11)
+#define GLPCI_CTRL_LOWER_LDE_SET				(1 << 9)
+#define GLPCI_CTRL_LOWER_OWC_SET				(1 << 4)
+#define GLPCI_CTRL_LOWER_IWC_SET				(1 << 3)
+#define GLPCI_CTRL_LOWER_PCD_SET				(1 << 2)
+#define GLPCI_CTRL_LOWER_ME_SET					(1 << 0)
+
+#define GLPCI_ARB		(MSR_PCI + 0x2011)
+#define GLPCI_ARB_UPPER_CR_SHIFT			28
+#define GLPCI_ARB_UPPER_R2_SHIFT			24
+#define GLPCI_ARB_UPPER_R1_SHIFT			20
+#define GLPCI_ARB_UPPER_R0_SHIFT			16
+#define GLPCI_ARB_UPPER_CH_SHIFT			12
+#define GLPCI_ARB_UPPER_H2_SHIFT			8
+#define GLPCI_ARB_UPPER_H1_SHIFT			4
+#define GLPCI_ARB_UPPER_H0_SHIFT			0
+
+#define GLPCI_ARB_LOWER_COV_SET				(1 << 23)
+#define GLPCI_ARB_LOWER_VO2_SET				(1 << 22)
+#define GLPCI_ARB_LOWER_OV1_SET				(1 << 21)
+#define GLPCI_ARB_LOWER_OV0_SET				(1 << 20)
+#define GLPCI_ARB_LOWER_MSK2_SET			(1 << 18)
+#define GLPCI_ARB_LOWER_MSK1_SET			(1 << 17)
+#define GLPCI_ARB_LOWER_MSK0_SET			(1 << 16)
+#define GLPCI_ARB_LOWER_CPRE_SET			(1 << 11)
+#define GLPCI_ARB_LOWER_PRE2_SET			(1 << 10)
+#define GLPCI_ARB_LOWER_PRE1_SET			(1 << 9)
+#define GLPCI_ARB_LOWER_PRE0_SET			(1 << 8)
+#define GLPCI_ARB_LOWER_BM1_SET				(1 << 7)
+#define GLPCI_ARB_LOWER_BM0_SET				(1 << 6)
+#define GLPCI_ARB_LOWER_EA_SET				(1 << 2)
+#define GLPCI_ARB_LOWER_BMD_SET				(1 << 1)
+#define GLPCI_ARB_LOWER_PARK_SET			(1 << 0)
+
+#define GLPCI_REN		(MSR_PCI + 0x2014)
+#define GLPCI_A0_BF		(MSR_PCI + 0x2015)
+#define GLPCI_C0_DF		(MSR_PCI + 0x2016)
+#define GLPCI_E0_FF		(MSR_PCI + 0x2017)
+#define GLPCI_RC0		(MSR_PCI + 0x2018)
+#define GLPCI_RC1		(MSR_PCI + 0x2019)
+#define GLPCI_RC2		(MSR_PCI + 0x201A)
+#define GLPCI_RC3		(MSR_PCI + 0x201B)
+#define GLPCI_RC4		(MSR_PCI + 0x201C)
+#define		GLPCI_RC_UPPER_TOP_SHIFT		12
+#define		GLPCI_RC_LOWER_BASE_SHIFT		12
+#define		GLPCI_RC_LOWER_EN_SET			(1 << 8)
+#define		GLPCI_RC_LOWER_PF_SET			(1 << 5)
+#define		GLPCI_RC_LOWER_WC_SET			(1 << 4)
+#define		GLPCI_RC_LOWER_WP_SET			(1 << 2)
+#define		GLPCI_RC_LOWER_CD_SET			(1 << 0)
+
+#define GLPCI_ExtMSR	(MSR_PCI + 0x201E)
+
+#define GLPCI_SPARE		(MSR_PCI + 0x201F)
+#define		GLPCI_SPARE_LOWER_AILTO_SET			(1 << 6)
+#define		GLPCI_SPARE_LOWER_PPD_SET			(1 << 5)
+#define		GLPCI_SPARE_LOWER_PPC_SET			(1 << 4)
+#define		GLPCI_SPARE_LOWER_MPC_SET			(1 << 3)
+#define		GLPCI_SPARE_LOWER_MME_SET			(1 << 2)
+#define		GLPCI_SPARE_LOWER_NSE_SET			(1 << 1)
+#define		GLPCI_SPARE_LOWER_SUPO_SET			(1 << 0)
+
+
+
+/* VIP GLIU1 port 5*/
+
+#define VIP_GLD_MSR_CAP			(MSR_VIP + 0x2000)
+#define VIP_GLD_MSR_CONFIG		(MSR_VIP + 0x2001)
+#define VIP_GLD_MSR_PM			(MSR_VIP + 0x2004)
+#define VIP_BIST				(MSR_VIP + 0x2005)
+
+/* AES GLIU1 port 6*/
+
+#define AES_GLD_MSR_CAP			(MSR_AES + 0x2000)
+#define AES_GLD_MSR_CONFIG		(MSR_AES + 0x2001)
+#define AES_GLD_MSR_PM			(MSR_AES + 0x2004)
+#define AES_CONTROL				(MSR_AES + 0x2006)
+
+
+/* from MC spec */
+#define MIN_MOD_BANKS		1
+#define MAX_MOD_BANKS		2
+#define MIN_DEV_BANKS		2
+#define MAX_DEV_BANKS		4
+#define MAX_COL_ADDR		17

-#define		RSTPPL_LOWER_HOLD_COUNT_SHIFT			16
-#define		RSTPPL_LOWER_BYPASS_SHIFT			15
-#define		RSTPPL_LOWER_TST_SHIFT				11
-#define		RSTPPL_LOWER_SDRMODE_SHIFT		 10
-#define		RSTPPL_LOWER_BOOTSTRAP_SHIFT		 4
-
-#define		RSTPPL_LOWER_LOCK_SET				(1<<25)
-#define		RSTPPL_LOWER_LOCKWAIT_SET			(1<<24)
-#define		RSTPPL_LOWER_BYPASS_SET				(1<<15)
-#define		RSTPPL_LOWER_PD_SET					(1<<14)
-#define		RSTPPL_LOWER_PLL_RESET_SET			(1<<13)
-#define		RSTPPL_LOWER_SDRMODE_SET		 (1<<10)
-#define		RSTPPL_LOWER_CPU_SEMI_SYNC_SET		 (1<<9)
-#define		RSTPPL_LOWER_PCI_SEMI_SYNC_SET		 (1<<8)
-#define		RSTPPL_LOWER_CHIP_RESET_SET		 (1<<0)
-
-#define	GLCP_DOTPLL				(MSR_GLCP + 0x15	/* R/W*/)
-#define		DOTPPL_LOWER_PD_SET				 (1<<14)
-
-
-/**/
-/*  GLIU1 port 4*/
-/**/
-#define	GLPCI_GLD_MSR_CAP			(MSR_PCI + 0x2000)
-#define	GLPCI_GLD_MSR_CONFIG			(MSR_PCI + 0x2001)
-#define	GLPCI_GLD_MSR_PM				(MSR_PCI + 0x2004)
-
-#define	GLPCI_CTRL			(MSR_PCI + 0x2010)
-#define	GLPCI_CTRL_UPPER_FTH_SHIFT				28
-#define	GLPCI_CTRL_UPPER_RTH_SHIFT				24
-#define	GLPCI_CTRL_UPPER_SBRTH_SHIFT				20
-#define	GLPCI_CTRL_UPPER_DTL_SHIFT				14
-#define	GLPCI_CTRL_UPPER_WTO_SHIFT				11
-#define	GLPCI_CTRL_UPPER_LAT_SHIFT				3
-#define	GLPCI_CTRL_UPPER_ILTO_SHIFT				8
-#define	GLPCI_CTRL_LOWER_IRFT_SHIFT				18
-#define	GLPCI_CTRL_LOWER_IRFC_SHIFT				16
-#define	GLPCI_CTRL_LOWER_ER_SET					(1<<11)
-#define	GLPCI_CTRL_LOWER_LDE_SET					(1<<9)
-#define	GLPCI_CTRL_LOWER_OWC_SET					(1<<4)
-#define	GLPCI_CTRL_LOWER_IWC_SET					(1<<3)
-#define	GLPCI_CTRL_LOWER_PCD_SET					(1<<2)
-#define	GLPCI_CTRL_LOWER_ME_SET					(1<<0)
-
-#define	GLPCI_ARB			(MSR_PCI + 0x2011)
-#define	GLPCI_ARB_UPPER_CR_SHIFT				 	(28)
-#define	GLPCI_ARB_UPPER_R2_SHIFT				 	(24)
-#define	GLPCI_ARB_UPPER_R1_SHIFT				 	(20)
-#define	GLPCI_ARB_UPPER_R0_SHIFT				 	(16)
-#define	GLPCI_ARB_UPPER_CH_SHIFT				 	(12)
-#define	GLPCI_ARB_UPPER_H2_SHIFT				 	(8)
-#define	GLPCI_ARB_UPPER_H1_SHIFT				 	(4)
-#define	GLPCI_ARB_UPPER_H0_SHIFT				 	(0)
-#define	GLPCI_ARB_LOWER_COV_SET						(1<<23)
-#define	GLPCI_ARB_LOWER_MSK2_SET				 	(1<<18)
-#define	GLPCI_ARB_LOWER_MSK1_SET				 	(1<<17)
-#define	GLPCI_ARB_LOWER_MSK0_SET				 	(1<<16)
-#define	GLPCI_ARB_LOWER_CPRE_SET					(1<<11)
-#define	GLPCI_ARB_LOWER_PRE2_SET					(1<<10)
-#define	GLPCI_ARB_LOWER_PRE1_SET					(1<<9)
-#define	GLPCI_ARB_LOWER_PRE0_SET					(1<<8)
-#define	GLPCI_ARB_LOWER_BM1_SET						(1<<7)
-#define	GLPCI_ARB_LOWER_BM0_SET						(1<<6)
-#define	GLPCI_ARB_LOWER_PARK_SET					(1<<0)
-
-#define	GLPCI_REN			(MSR_PCI + 0x2014)
-#define	GLPCI_A0_BF			(MSR_PCI + 0x2015)
-#define	GLPCI_C0_DF			(MSR_PCI + 0x2016)
-#define	GLPCI_E0_FF			(MSR_PCI + 0x2017)
-#define	GLPCI_RC0			(MSR_PCI + 0x2018)
-#define	GLPCI_RC1			(MSR_PCI + 0x2019)
-#define	GLPCI_RC2			(MSR_PCI + 0x201A)
-#define	GLPCI_RC3			(MSR_PCI + 0x201B)
-#define	GLPCI_RC4			(MSR_PCI + 0x201C)
-#define		GLPCI_RC_UPPER_TOP_SHIFT				12
-#define		GLPCI_RC_LOWER_BASE_SHIFT			12
-#define		GLPCI_RC_LOWER_EN_SET				(1<<8)
-#define		GLPCI_RC_LOWER_PF_SET				(1<<5)
-#define		GLPCI_RC_LOWER_WC_SET				(1<<4)
-#define		GLPCI_RC_LOWER_WP_SET				(1<<2)
-#define		GLPCI_RC_LOWER_CD_SET				(1<<0)
-#define	GLPCI_EXT_MSR			(MSR_PCI + 0x201E)
-#define	GLPCI_SPARE			(MSR_PCI + 0x201F)
-#define		GLPCI_SPARE_LOWER_AILTO_SET					(1<<6)
-#define		GLPCI_SPARE_LOWER_PPD_SET					(1<<5)
-#define		GLPCI_SPARE_LOWER_PPC_SET					(1<<4)
-#define		GLPCI_SPARE_LOWER_MPC_SET					(1<<3)
-#define		GLPCI_SPARE_LOWER_MME_SET					(1<<2)
-#define		GLPCI_SPARE_LOWER_NSE_SET					(1<<1)
-#define		GLPCI_SPARE_LOWER_SUPO_SET					(1<<0)
-
-
-/**/
-/* FooGlue GLIU1 port 5*/
-/**/
-/*	GX3 not needed?
-#define	FG_GLD_MSR_CAP			(MSR_FG + 0x2000)
-#define	FG_GLD_MSR_PM			(MSR_FG + 0x2004)
-*/
-/*  VIP GLIU1 port 5*/
-/* */
-#define VIP_GLD_MSR_CAP		(MSR_VIP + 0x2000)
-#define VIP_GLD_MSR_CONFIG	(MSR_VIP + 0x2001)
-#define VIP_GLD_MSR_PM		(MSR_VIP + 0x2004)
-#define VIP_BIST			(MSR_VIP + 0x2005)
-/* */
-/*  AES GLIU1 port 6*/
-/* */
-#define AES_GLD_MSR_CAP		(MSR_AES + 0x2000)
-#define AES_GLD_MSR_CONFIG	(MSR_AES + 0x2001)
-#define AES_GLD_MSR_PM		(MSR_AES + 0x2004)
-#define AES_CONTROL			(MSR_AES + 0x2006)
-/* more fun stuff */
+/* GLIU typedefs */
 #define BM			1	/*  Base Mask - map power of 2 size aligned region*/
 #define BMO			2	/*  BM with an offset*/
 #define R				3	/*  Range - 4k range minimum*/
@@ -515,10 +527,10 @@

#define MSR_GL0	(GL1_GLIU0 << 29)

+
+/* Platform stuff but unlikely to change */
 /*  Set up desc addresses from 20 - 3f*/
 /*  This is chip specific!*/
-
-/* ----------   GX3 OK   --------------  */
 #define MSR_GLIU0_BASE1			(MSR_GLIU0 + 0x20)		/*  BM*/
 #define MSR_GLIU0_BASE2			(MSR_GLIU0 + 0x21)		/*  BM*/
 #define MSR_GLIU0_BASE3			(MSR_GLIU0 + 0x22)		/*  BM*/
@@ -585,656 +597,13 @@
 #define GLIU1_IOD_SC_1			(MSR_GLIU1 + 0xE4)
 #define GLIU1_IOD_SC_2			(MSR_GLIU1 + 0xE5)
 #define GLIU1_IOD_SC_3			(MSR_GLIU1 + 0xE6)
-
-/* ------------------------  */
-
 #define MSR_GLIU1_FPU_TRAP		(GLIU1_IOD_SC_0)	/*  FooGlue F0 for FPU*/

+/* ------------------------  */

-/* definitions that are "once you are mostly up, start VSA" type things */
-#define SMM_OFFSET	(0x40400000)
-#define SMM_SIZE		(256)
-#define DMM_OFFSET	(0x0C0000000)
-#define DMM_SIZE		(128)
-#define FB_OFFSET		(0x41000000)
-#define PCI_MEM_TOP	(0x0EFFFFFFF)	 // Top of PCI mem allocation region
-#define PCI_IO_TOP		(0x0EFFF)		 // Top of PCI I/O allocation region
-#define END_OPTIONROM_SPACE	(0x0DFFF)		 // E0000 is reserved for SystemROMs.
-
-
-#define CS5535_IDSEL	(0x02000000)	 // IDSEL = AD25, device #15
-#define CHIPSET_DEV_NUM	(15)
-#define IDSEL_BASE	(11)			 // bit 11 = device 1
-
-
-/* standard AMD post definitions -- might as well use them. */
-#define POST_Output_Port				(0x080)	/*  port to write post codes to*/
-
-#define POST_preSioInit					(0x000)	/* geode.asm*/
-#define POST_clockInit					(0x001)	/* geode.asm*/
-#define POST_CPURegInit					(0x002)	/* geode.asm*/
-#define POST_UNREAL					(0x003)	/* geode.asm*/
-#define POST_CPUMemRegInit				(0x004)	/* geode.asm*/
-#define POST_CPUTest					(0x005)	/* geode.asm*/
-#define POST_memSetup					(0x006)	/* geode.asm*/
-#define POST_memSetUpStack				(0x007)	/* geode.asm*/
-#define POST_memTest					(0x008)	/* geode.asm*/
-#define POST_shadowRom				(0x009)	/* geode.asm*/
-#define POST_memRAMoptimize			(0x00A)	/* geode.asm*/
-#define POST_cacheInit					(0x00B)	/* geode.asm*/
-#define POST_northBridgeInit				(0x00C)	/* geode.asm*/
-#define POST_chipsetInit					(0x00D)	/* geode.asm*/
-#define POST_sioTest					(0x00E)	/* geode.asm*/
-#define POST_pcATjunk					(0x00F)	/* geode.asm*/
-
-
-#define POST_intTable					(0x010)	/* geode.asm*/
-#define POST_memInfo					(0x011)	/* geode.asm*/
-#define POST_romCopy					(0x012)	/* geode.asm*/
-#define POST_PLLCheck					(0x013)	/* geode.asm*/
-#define POST_keyboardInit				(0x014)	/* geode.asm*/
-#define POST_cpuCacheOff				(0x015)	/* geode.asm*/
-#define POST_BDAInit					(0x016)	/* geode.asm*/
-#define POST_pciScan					(0x017)	/* geode.asm*/
-#define POST_optionRomInit				(0x018)	/* geode.asm*/
-#define POST_ResetLimits				(0x019)	/* geode.asm*/
-#define POST_summary_screen			(0x01A)	/* geode.asm*/
-#define POST_Boot						(0x01B)	/* geode.asm*/
-#define POST_SystemPreInit				(0x01C)	/* geode.asm*/
-#define POST_ClearRebootFlag				(0x01D)	/* geode.asm*/
-#define POST_GLIUInit					(0x01E)	/* geode.asm*/
-#define POST_BootFailed					(0x01F)	/* geode.asm*/
-
-
-#define POST_CPU_ID					(0x020)	/* cpucpuid.asm*/
-#define POST_COUNTERBROKEN			(0x021)	/* pllinit.asm*/
-#define POST_DIFF_DIMMS				(0x022)	/* pllinit.asm*/
-#define POST_WIGGLE_MEM_LINES			(0x023)	/* pllinit.asm*/
-#define POST_NO_GLIU_DESC				(0x024)	/* pllinit.asm*/
-#define POST_CPU_LCD_CHECK			(0x025)	/* pllinit.asm*/
-#define POST_CPU_LCD_PASS				(0x026)	/* pllinit.asm*/
-#define POST_CPU_LCD_FAIL				(0x027)	/* pllinit.asm*/
-#define POST_CPU_STEPPING				(0x028)	/* cpucpuid.asm*/
-#define POST_CPU_DM_BIST_FAILURE		(0x029)	/* gx2reg.asm*/
-#define POST_CPU_FLAGS				(0x02A)	/* cpucpuid.asm*/
-#define POST_CHIPSET_ID				(0x02b)	/* chipset.asm*/
-#define POST_CHIPSET_ID_PASS			(0x02c)	/* chipset.asm*/
-#define POST_CHIPSET_ID_FAIL			(0x02d)	/* chipset.asm*/
-#define POST_CPU_ID_GOOD				(0x02E)	/* cpucpuid.asm*/
-#define POST_CPU_ID_FAIL				(0x02F)	/* cpucpuid.asm*/
-
-
-
-/*  PCI config*/
-#define P80_PCICFG						(0x030)	/*  pcispace.asm*/
-
-
-/*  PCI io*/
-#define P80_PCIIO						(0x040)	/*  pcispace.asm*/
-
-
-/*  PCI memory*/
-#define P80_PCIMEM					(0x050)	/*  pcispace.asm*/
-
-
-/*  SIO*/
-#define P80_SIO						(0x060)		/*  *sio.asm*/
-
-/*  Memory Setp*/
-#define P80_MEM_SETUP					(0x070)	/* docboot meminit*/
-#define POST_MEM_SETUP				(0x070)	/* memsize.asm*/
-#define ERROR_32BIT_DIMMS				(0x071)	/* memsize.asm*/
-#define POST_MEM_SETUP2				(0x072)	/* memsize.asm*/
-#define POST_MEM_SETUP3				(0x073)	/* memsize.asm*/
-#define POST_MEM_SETUP4				(0x074)	/* memsize.asm*/
-#define POST_MEM_SETUP5				(0x075)	/* memsize.asm*/
-#define POST_MEM_ENABLE				(0x076)	/* memsize.asm*/
-#define ERROR_NO_DIMMS				(0x077)	/* memsize.asm*/
-#define ERROR_DIFF_DIMMS				(0x078)	/* memsize.asm*/
-#define ERROR_BAD_LATENCY				(0x079)	/* memsize.asm*/
-#define ERROR_SET_PAGE				(0x07a)	/* memsize.asm*/
-#define ERROR_DENSITY_DIMM			(0x07b)	/* memsize.asm*/
-#define ERROR_UNSUPPORTED_DIMM		(0x07c)	/* memsize.asm*/
-#define ERROR_BANK_SET				(0x07d)	/* memsize.asm*/
-#define POST_MEM_SETUP_GOOD			(0x07E)	/* memsize.asm*/
-#define POST_MEM_SETUP_FAIL			(0x07F)	/* memsize.asm*/
-
-
-#define POST_UserPreInit					(0x080)	/* geode.asm*/
-#define POST_UserPostInit				(0x081)	/* geode.asm*/
-#define POST_Equipment_check			(0x082)	/* geode.asm*/
-#define POST_InitNVRAMBX				(0x083)	/* geode.asm*/
-#define POST_NoPIRTable				(0x084)	/* pci.asm*/
-#define POST_ChipsetFingerPrintPass		(0x085)	/*  prechipsetinit*/
-#define POST_ChipsetFingerPrintFail		(0x086)	/*  prechipsetinit*/
-#define POST_CPU_IM_TAG_BIST_FAILURE	(0x087)	/*  gx2reg.asm*/
-#define POST_CPU_IM_DATA_BIST_FAILURE	(0x088)	/*  gx2reg.asm*/
-#define POST_CPU_FPU_BIST_FAILURE		(0x089)	/*  gx2reg.asm*/
-#define POST_CPU_BTB_BIST_FAILURE		(0x08a)	/*  gx2reg.asm*/
-#define POST_CPU_EX_BIST_FAILURE		(0x08b)	/*  gx2reg.asm*/
-#define POST_Chipset_PI_Test_Fail			(0x08c)	/*  prechipsetinit*/
-#define POST_Chipset_SMBus_SDA_Test_Fail	(0x08d)	/*  prechipsetinit*/
-#define POST_BIT_CLK_Fail				(0x08e)	/*  Hawk geode.asm override*/
-
-
-#define POST_STACK_SETUP				(0x090)	/* memstack.asm*/
-#define POST_CPU_PF_BIST_FAILURE		(0x091)	/*  gx2reg.asm*/
-#define POST_CPU_L2_BIST_FAILURE		(0x092)	/*  gx2reg.asm*/
-#define POST_CPU_GLCP_BIST_FAILURE		(0x093)	/*  gx2reg.asm*/
-#define POST_CPU_DF_BIST_FAILURE		(0x094)	/*  gx2reg.asm*/
-#define POST_CPU_VG_BIST_FAILURE		(0x095)	/*  gx2reg.asm*/
-#define POST_CPU_VIP_BIST_FAILURE		(0x096)	/*  gx2reg.asm*/
-#define POST_STACK_SETUP_PASS			(0x09E)	/* memstack.asm*/
-#define POST_STACK_SETUP_FAIL			(0x09F)	/* memstack.asm*/
-
-
-#define POST_PLL_INIT					(0x0A0)	/* pllinit.asm*/
-#define POST_PLL_MANUAL				(0x0A1)	/* pllinit.asm*/
-#define POST_PLL_STRAP					(0x0A2)	/* pllinit.asm*/
-#define POST_PLL_RESET_FAIL			(0x0A3)	/* pllinit.asm*/
-#define POST_PLL_PCI_FAIL				(0x0A4)	/* pllinit.asm*/
-#define POST_PLL_MEM_FAIL				(0x0A5)	/* pllinit.asm*/
-#define POST_PLL_CPU_VER_FAIL			(0x0A6)	/* pllinit.asm*/
-
-
-#define POST_MEM_TESTMEM				(0x0B0)	/* memtest.asm*/
-#define POST_MEM_TESTMEM1			(0x0B1)	/* memtest.asm*/
-#define POST_MEM_TESTMEM2			(0x0B2)	/* memtest.asm*/
-#define POST_MEM_TESTMEM3			(0x0B3)	/* memtest.asm*/
-#define POST_MEM_TESTMEM4			(0x0B4)	/* memtest.asm*/
-#define POST_MEM_TESTMEM_PASS		(0x0BE)	/* memtest.asm*/
-#define POST_MEM_TESTMEM_FAIL		(0x0BF)	/* memtest.asm*/
-
-
-#define POST_SECUROM_SECBOOT_START        (0x0C0)	/* secstart.asm*/
-#define POST_SECUROM_BOOTSRCSETUP         (0x0C1)	/* secstart.asm*/
-#define POST_SECUROM_REMAP_FAIL          	 (0x0C2)	/* secstart.asm*/
-#define POST_SECUROM_BOOTSRCSETUP_FAIL    (0x0C3)	/* secstart.asm*/
-#define POST_SECUROM_DCACHESETUP          (0x0C4)	/* secstart.asm*/
-#define POST_SECUROM_DCACHESETUP_FAIL     (0x0C5)	/* secstart.asm*/
-#define POST_SECUROM_ICACHESETUP          (0x0C6)	/* secstart.asm*/
-#define POST_SECUROM_DESCRIPTORSETUP      (0x0C7)	/* secstart.asm*/
-#define POST_SECUROM_DCACHESETUPBIOS      (0x0C8)	/* secstart.asm*/
-#define POST_SECUROM_PLATFORMSETUP        (0x0C9)	/* secstart.asm*/
-#define POST_SECUROM_SIGCHECKBIOS         (0x0CA)	/* secstart.asm*/
-#define POST_SECUROM_ICACHESETUPBIOS      (0x0CB)	/* secstart.asm*/
-#define POST_SECUROM_PASS				  (0x0CC)	/* secstart.asm*/
-#define POST_SECUROM_FAIL				  (0x0CD)	/* secstart.asm*/
-
-#define POST_RCONFInitError				(0x0CE)	/* cache.asm*/
-#define POST_CacheInitError				(0x0CF)	/* cache.asm*/
-
-
-#define POST_ROM_PREUNCOMPRESS			(0x0D0)	/* rominit.asm*/
-#define POST_ROM_UNCOMPRESS				(0x0D1)	/* rominit.asm*/
-#define POST_ROM_SMM_INIT				(0x0D2)	/* rominit.asm*/
-#define POST_ROM_VID_BIOS				(0x0D3)	/* rominit.asm*/
-#define POST_ROM_LCDINIT				(0x0D4)	/* rominit.asm*/
-#define POST_ROM_SPLASH					(0x0D5)	/* rominit.asm*/
-#define POST_ROM_HDDINIT				(0x0D6)	/* rominit.asm*/
-#define POST_ROM_SYS_INIT				(0x0D7)	/* rominit.asm*/
-#define POST_ROM_DMM_INIT				(0x0D8)	/* rominit.asm*/
-#define POST_ROM_TVINIT					(0x0D9)	/* rominit.asm*/
-#define POST_ROM_POSTUNCOMPRESS			(0x0DE)
-
-
-#define P80_CHIPSET_INIT				(0x0E0)	/* chipset.asm*/
-#define POST_PreChipsetInit				(0x0E1)	/* geode.asm*/
-#define POST_LateChipsetInit			(0x0E2)	/* geode.asm*/
-#define POST_NORTHB_INIT				(0x0E8)	/* northb.asm*/
-
-
-#define POST_INTR_SEG_JUMP				(0x0F0)	/* vector.asm*/
-
-
-/* I don't mind if somebody decides this needs to be in a seperate file. I don't see much point
-  * in it, either. 
-  * RGM 
-  */
-#define Cx5535_ID	 (	0x002A100B)
-#define Cx5536_ID	 (	0x208F1022)
-
-/* Cs5535 as follows. */
-/*  SB_GLIU*/
-/* 	port0 - GLIU*/
-/* 	port1 - GLPCI*/
-/* 	port2 - USB Controller #2*/
-/* 	port3 - ATA-5 Controller*/
-/* 	port4 - MDD*/
-/* 	port5 - AC97*/
-/* 	port6 - USB Controller #1*/
-/* 	port7 - GLCP*/
-
-
-/*  SouthBridge Equates*/
-/*  MSR_SB and SB_SHIFT are located in CPU.inc*/
-#define MSR_SB_GLIU	 ((9 << 14) + MSR_SB)		/* 51024xxx or 510*xxxx	- fake out just like GL0 on CPU. */
-#define MSR_SB_GLPCI	 (MSR_SB)			/* 5100xxxx - don't go to the GLIU */
-#define MSR_SB_USB2	 ((2 << SB_SHIFT) + MSR_SB)	/* 5120xxxx */
-#define MSR_SB_ATA	 ((3 << SB_SHIFT) + MSR_SB)	/* 5130xxxx */
-#define MSR_SB_MDD	 ((4 << SB_SHIFT) + MSR_SB)	/* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
-#define MSR_SB_AC97	 ((5 << SB_SHIFT) + MSR_SB)	/* 5150xxxx */
-#define MSR_SB_USB1	 ((6 << SB_SHIFT) + MSR_SB)	/* 5160xxxx */
-#define MSR_SB_GLCP	 ((7 << SB_SHIFT) + MSR_SB)	/* 5170xxxx */
-
-/* */
-/* GLIU*/
-/* */
-#define GLIU_SB_GLD_MSR_CAP		 (	MSR_SB_GLIU + 0x00)
-#define GLIU_SB_GLD_MSR_CONF	 (	MSR_SB_GLIU + 0x01)
-#define GLIU_SB_GLD_MSR_PM		 (	MSR_SB_GLIU + 0x04)
-
-/* */
-/*  USB1*/
-/* */
-#define USB1_SB_GLD_MSR_CAP		 (	MSR_SB_USB1 + 0x00)
-#define USB1_SB_GLD_MSR_CONF	 (	MSR_SB_USB1 + 0x01)
-#define USB1_SB_GLD_MSR_PM		 (	MSR_SB_USB1 + 0x04)
-/* */
-/*  USB2*/
-/* */
-#define USB2_SB_GLD_MSR_CAP		 (	MSR_SB_USB2 + 0x00)
-#define USB2_SB_GLD_MSR_CONF	 (	MSR_SB_USB2 + 0x01)
-#define USB2_SB_GLD_MSR_PM		 (	MSR_SB_USB2 + 0x04)
-
-
-/* */
-/*  ATA*/
-/* */
-#define ATA_SB_GLD_MSR_CAP		 (	MSR_SB_ATA + 0x00)
-#define ATA_SB_GLD_MSR_CONF		 (	MSR_SB_ATA + 0x01)
-#define ATA_SB_GLD_MSR_ERR		 (	MSR_SB_ATA + 0x03)
-#define ATA_SB_GLD_MSR_PM		 (	MSR_SB_ATA + 0x04)
-
-/* */
-/*  AC97*/
-/* */
-#define AC97_SB_GLD_MSR_CAP		 (	MSR_SB_AC97 + 0x00)
-#define AC97_SB_GLD_MSR_CONF	 (	MSR_SB_AC97 + 0x01)
-#define AC97_SB_GLD_MSR_PM		 (	MSR_SB_AC97 + 0x04)
-
-/* */
-/*  GLPCI*/
-/* */
-#define GLPCI_SB_GLD_MSR_CAP	 (	MSR_SB_GLPCI + 0x00)
-#define GLPCI_SB_GLD_MSR_CONF	 (	MSR_SB_GLPCI + 0x01)
-#define GLPCI_SB_GLD_MSR_PM		 (	MSR_SB_GLPCI + 0x04)
-#define GLPCI_SB_CTRL			 (	MSR_SB_GLPCI + 0x10)
-#define 	GLPCI_CRTL_PPIDE_SET	 (	1 << 17)
-/* */
-/*  GLCP*/
-/* */
-#define GLCP_SB_GLD_MSR_CAP		 (	MSR_SB_GLCP + 0x00)
-#define GLCP_SB_GLD_MSR_CONF	 (	MSR_SB_GLCP + 0x01)
-#define GLCP_SB_GLD_MSR_PM		 (	MSR_SB_GLCP + 0x04)
-
-/* 	*/
-/*  MDD*/
-/* */
-
-#define MDD_SMBUS		(0x6000)
-#define MDD_GPIO		(0x6100)
-#define MDD_MFGPT		(0x6200)
-#define MDD_FLASH_BAR_0	(0x6400)
-#define MDD_FLASH_BAR_1	(0x6500)
-#define MDD_FLASH_BAR_2	(0x6600)
-#define MDD_FLASH_BAR_3	(0x6700)
-
-#define MDD_ACPI_BASE	(0x9C00)
-#define MDD_PM			(0x9D00)
-
-
-// # FIXME
-#define GPIO_BASE		MDD_GPIO
-#define ACPI_BASE		MDD_ACPI_BASE
-#define	PMLogic_BASE	MDD_PM
-
-
-#define MDD_SB_GLD_MSR_CAP		 (	MSR_SB_MDD + 0x00)
-#define MDD_SB_GLD_MSR_CONF		 (	MSR_SB_MDD + 0x01)
-#define MDD_SB_GLD_MSR_PM		 (	MSR_SB_MDD + 0x04)
-#define LBAR_EN			 (		0x01)
-#define IO_MASK			 (		0x1f)
-#define MEM_MASK		 (		0x0FFFFF)
-#define MDD_LBAR_IRQ	 (		MSR_SB_MDD + 0x08)
-#define MDD_LBAR_KEL1	 (		MSR_SB_MDD + 0x09)
-#define MDD_LBAR_KEL2	 (		MSR_SB_MDD + 0x0A)
-#define MDD_LBAR_SMB	 (		MSR_SB_MDD + 0x0B)
-#define MDD_LBAR_GPIO	 (		MSR_SB_MDD + 0x0C)
-#define MDD_LBAR_MFGPT	 (		MSR_SB_MDD + 0x0D)
-#define MDD_LBAR_ACPI	 (		MSR_SB_MDD + 0x0E)
-#define MDD_LBAR_PMS	 (		MSR_SB_MDD + 0x0F)
-
-#define MDD_LBAR_FLSH0	 (		MSR_SB_MDD + 0x010)
-#define MDD_LBAR_FLSH1	 (		MSR_SB_MDD + 0x011)
-#define MDD_LBAR_FLSH2	 (		MSR_SB_MDD + 0x012)
-#define MDD_LBAR_FLSH3	 (		MSR_SB_MDD + 0x013)
-#define MDD_LEG_IO		 (		MSR_SB_MDD + 0x014)
-#define MDD_PIN_OPT		 (		MSR_SB_MDD + 0x015)
-#define MDD_SOFT_IRQ	 (		MSR_SB_MDD + 0x016)
-#define MDD_SOFT_RESET	 (		MSR_SB_MDD + 0x017)
-#define MDD_NORF_CNTRL	 (		MSR_SB_MDD + 0x018)
-#define MDD_NORF_T01	 (		MSR_SB_MDD + 0x019)
-#define MDD_NORF_T23	 (		MSR_SB_MDD + 0x01A)
-#define MDD_NANDF_DATA	 (		MSR_SB_MDD + 0x01B)
-#define MDD_NADF_CNTL	 (		MSR_SB_MDD + 0x01C)
-#define MDD_AC_DMA		 (		MSR_SB_MDD + 0x01E)
-#define MDD_KEL_CNTRL	 (		MSR_SB_MDD + 0x01F)
-
-#define MDD_IRQM_YLOW	 (		MSR_SB_MDD + 0x020)
-#define MDD_IRQM_YHIGH	 (		MSR_SB_MDD + 0x021)
-#define MDD_IRQM_ZLOW	 (		MSR_SB_MDD + 0x022)
-#define MDD_IRQM_ZHIGH	 (		MSR_SB_MDD + 0x023)
-#define MDD_IRQM_PRIM	 (		MSR_SB_MDD + 0x024)
-#define MDD_IRQM_LPC	 (		MSR_SB_MDD + 0x025)
-#define MDD_IRQM_LXIRR	 (		MSR_SB_MDD + 0x026)
-#define MDD_IRQM_HXIRR	 (		MSR_SB_MDD + 0x027)
-
-#define MDD_MFGPT_IRQ	 (		MSR_SB_MDD + 0x028)
-#define MDD_MFGPT_NR	 (		MSR_SB_MDD + 0x029)
-#define MDD_MFGPT_RES0	 (		MSR_SB_MDD + 0x02A)
-#define MDD_MFGPT_RES1	 (		MSR_SB_MDD + 0x02B)
-
-#define MDD_FLOP_S3F2	 (		MSR_SB_MDD + 0x030)
-#define MDD_FLOP_S3F7	 (		MSR_SB_MDD + 0x031)
-#define MDD_FLOP_S372	 (		MSR_SB_MDD + 0x032)
-#define MDD_FLOP_S377	 (		MSR_SB_MDD + 0x033)
-
-#define MDD_PIC_S		 (		MSR_SB_MDD + 0x034)
-#define MDD_PIT_S		 (		MSR_SB_MDD + 0x036)
-#define MDD_PIT_CNTRL	 (		MSR_SB_MDD + 0x037)
-
-#define MDD_UART1_MOD	 (		MSR_SB_MDD + 0x038)
-#define MDD_UART1_DON	 (		MSR_SB_MDD + 0x039)
-#define MDD_UART1_CONF	 (		MSR_SB_MDD + 0x03A)
-#define MDD_UART2_MOD	 (		MSR_SB_MDD + 0x03C)
-#define MDD_UART2_DON	 (		MSR_SB_MDD + 0x03D)
-#define MDD_UART2_CONF	 (		MSR_SB_MDD + 0x03E)
-
-#define MDD_DMA_MAP		 (		MSR_SB_MDD + 0x040)
-#define MDD_DMA_SHAD1		 (		MSR_SB_MDD + 0x041)
-#define MDD_DMA_SHAD2		 (		MSR_SB_MDD + 0x042)
-#define MDD_DMA_SHAD3		 (		MSR_SB_MDD + 0x043)
-#define MDD_DMA_SHAD4		 (		MSR_SB_MDD + 0x044)
-#define MDD_DMA_SHAD5		 (		MSR_SB_MDD + 0x045)
-#define MDD_DMA_SHAD6		 (		MSR_SB_MDD + 0x046)
-#define MDD_DMA_SHAD7		 (		MSR_SB_MDD + 0x047)
-#define MDD_DMA_SHAD8		 (		MSR_SB_MDD + 0x048)
-#define MDD_DMA_SHAD9		 (		MSR_SB_MDD + 0x049)
-
-#define MDD_LPC_EADDR	 (		MSR_SB_MDD + 0x04C)
-#define MDD_LPC_ESTAT	 (		MSR_SB_MDD + 0x04D)
-#define MDD_LPC_SIRQ	 (		MSR_SB_MDD + 0x04E)
-#define MDD_LPC_RES		 (		MSR_SB_MDD + 0x04F)
-
-#define MDD_PML_TMR		 (		MSR_SB_MDD + 0x050)
-#define MDD_RTC_RAM_LO_CK	 (		MSR_SB_MDD + 0x054)
-#define MDD_RTC_DOMA_IND	 (		MSR_SB_MDD + 0x055)
-#define MDD_RTC_MONA_IND	 (		MSR_SB_MDD + 0x056)
-#define MDD_RTC_CENTURY_OFFSET	 (		MSR_SB_MDD + 0x057)
-
-/* ***********************************************************/
-/*  LBUS Device Equates - */
-/* ***********************************************************/
-
-/* */
-/*  SMBus*/
-/* */
-
-#define SMBUS_SMBSDA		 (		SMBUS_BASE + 0x00)
-#define SMBUS_SMBST			 (		SMBUS_BASE + 0x01)
-#define 	SMBST_SLVSTP_SET	 (		1 << 7)
-#define 	SMBST_SDAST_SET		 (		1 << 6)
-#define 	SMBST_BER_SET		 (		1 << 5)
-#define 	SMBST_NEGACK_SET	 (		1 << 4)
-#define 	SMBST_STASTR_SET	 (		1 << 3)
-#define 	SMBST_NMATCH_SET	 (		1 << 2)
-#define 	SMBST_MASTER_SET	 (		1 << 1)
-#define 	SMBST_XMIT_SET		 (		1 << 0)
-#define SMBUS_SMBCST		 (		SMBUS_BASE + 0x02)
-#define 	SMBCST_TGSCL_SET	 (		1 << 5)
-#define 	SMBCST_TSDA_SET		 (		1 << 4)
-#define 	SMBCST_GCMTCH_SET	 (		1 << 3)
-#define 	SMBCST_MATCH_SET	 (		1 << 2)
-#define 	SMBCST_BB_SET		 (		1 << 1)
-#define 	SMBCST_BUSY_SET		 (		1 << 0)
-#define SMBUS_SMBCTL1		 (		SMBUS_BASE + 0x03)
-#define 	SMBCTL1_STASTRE_SET	 (		1 << 7)
-#define 	SMBCTL1_NMINTE_SET	 (		1 << 6)
-#define 	SMBCTL1_GCMEN_SET	 (		1 << 5)
-#define 	SMBCTL1_RECACK_SET	 (		1 << 4)
-#define 	SMBCTL1_DMAEN_SET	 (		1 << 3)
-#define 	SMBCTL1_INTEN_SET	 (		1 << 2)
-#define 	SMBCTL1_STOP_SET	 (		1 << 1)
-#define 	SMBCTL1_START_SET	 (		1 << 0)
-#define SMBUS_SMBADDR		 (		SMBUS_BASE + 0x04)
-#define 	SMBADDR_SAEN_SET	 (		1 << 7)
-#define SMBUS_SMBCTL2		 (		SMBUS_BASE + 0x05)
-#define 	SMBCTL2_SCLFRQ_SHIFT	 (		1 << 1)
-#define 	SMBCTL2_ENABLE_SET		 (		1 << 0)
-
-/* */
-/*  GPIO*/
-/* */
-
-#define GPIOL_0_SET		 (		1 << 0)
-#define GPIOL_1_SET		 (		1 << 1)
-#define GPIOL_2_SET		 (		1 << 2)
-#define GPIOL_3_SET		 (		1 << 3)
-#define GPIOL_4_SET		 (		1 << 4)
-#define GPIOL_5_SET		 (		1 << 5)
-#define GPIOL_6_SET		 (		1 << 6)
-#define GPIOL_7_SET		 (		1 << 7)
-#define GPIOL_8_SET		 (		1 << 8)
-#define GPIOL_9_SET		 (		1 << 9)
-#define GPIOL_10_SET	 (		1 << 10)
-#define GPIOL_11_SET	 (		1 << 11)
-#define GPIOL_12_SET	 (		1 << 12)
-#define GPIOL_13_SET	 (		1 << 13)
-#define GPIOL_14_SET	 (		1 << 14)
-#define GPIOL_15_SET	 (		1 << 15)
-
-#define GPIOL_0_CLEAR	 (		1 << 16)
-#define GPIOL_1_CLEAR	 (		1 << 17)
-#define GPIOL_2_CLEAR	 (		1 << 18)
-#define GPIOL_3_CLEAR	 (		1 << 19)
-#define GPIOL_4_CLEAR	 (		1 << 20)
-#define GPIOL_5_CLEAR	 (		1 << 21)
-#define GPIOL_6_CLEAR	 (		1 << 22)
-#define GPIOL_7_CLEAR	 (		1 << 23)
-#define GPIOL_8_CLEAR	 (		1 << 24)
-#define GPIOL_9_CLEAR	 (		1 << 25)
-#define GPIOL_10_CLEAR	 (		1 << 26)
-#define GPIOL_11_CLEAR	 (		1 << 27)
-#define GPIOL_12_CLEAR	 (		1 << 28)
-#define GPIOL_13_CLEAR	 (		1 << 29)
-#define GPIOL_14_CLEAR	 (		1 << 30)
-#define GPIOL_15_CLEAR	 (		1 << 31)
-
-#define GPIOH_16_SET	 (		1 << 0)
-#define GPIOH_17_SET	 (		1 << 1)
-#define GPIOH_18_SET	 (		1 << 2)
-#define GPIOH_19_SET	 (		1 << 3)
-#define GPIOH_20_SET	 (		1 << 4)
-#define GPIOH_21_SET	 (		1 << 5)
-#define GPIOH_22_SET	 (		1 << 6)
-#define GPIOH_23_SET	 (		1 << 7)
-#define GPIOH_24_SET	 (		1 << 8)
-#define GPIOH_25_SET	 (		1 << 9)
-#define GPIOH_26_SET	 (		1 << 10)
-#define GPIOH_27_SET	 (		1 << 11)
-#define GPIOH_28_SET	 (		1 << 12)
-#define GPIOH_29_SET	 (		1 << 13)
-#define GPIOH_30_SET	 (		1 << 14)
-#define GPIOH_31_SET	 (		1 << 15)
-
-#define GPIOH_16_CLEAR	 (		1 << 16)
-#define GPIOH_17_CLEAR	 (		1 << 17)
-#define GPIOH_18_CLEAR	 (		1 << 18)
-#define GPIOH_19_CLEAR	 (		1 << 19)
-#define GPIOH_20_CLEAR	 (		1 << 20)
-#define GPIOH_21_CLEAR	 (		1 << 21)
-#define GPIOH_22_CLEAR	 (		1 << 22)
-#define GPIOH_23_CLEAR	 (		1 << 23)
-#define GPIOH_24_CLEAR	 (		1 << 24)
-#define GPIOH_25_CLEAR	 (		1 << 25)
-#define GPIOH_26_CLEAR	 (		1 << 26)
-#define GPIOH_27_CLEAR	 (		1 << 27)
-#define GPIOH_28_CLEAR	 (		1 << 28)
-#define GPIOH_29_CLEAR	 (		1 << 29)
-#define GPIOH_30_CLEAR	 (		1 << 30)
-#define GPIOH_31_CLEAR	 (		1 << 31)
-
-
-/*  GPIO LOW Bank Bit Registers*/
-#define GPIOL_OUTPUT_VALUE		 (		GPIO_BASE + 0x00)
-#define GPIOL_OUTPUT_ENABLE		 (		GPIO_BASE + 0x04)
-#define GPIOL_OUT_OPENDRAIN		 (		GPIO_BASE + 0x08)
-#define GPIOL_OUTPUT_INVERT_ENABLE	 (	GPIO_BASE + 0x0C)
-#define GPIOL_OUT_AUX1_SELECT	 (		GPIO_BASE + 0x10)
-#define GPIOL_OUT_AUX2_SELECT	 (		GPIO_BASE + 0x14)
-#define GPIOL_PULLUP_ENABLE		 (		GPIO_BASE + 0x18)
-#define GPIOL_PULLDOWN_ENABLE	 (		GPIO_BASE + 0x1C)
-#define GPIOL_INPUT_ENABLE		 (		GPIO_BASE + 0x20)
-#define GPIOL_INPUT_INVERT_ENABLE	 (	GPIO_BASE + 0x24)
-#define GPIOL_IN_FILTER_ENABLE	 (		GPIO_BASE + 0x28)
-#define GPIOL_IN_EVENTCOUNT_ENABLE	 (	GPIO_BASE + 0x2C)
-#define GPIOL_READ_BACK			 (		GPIO_BASE + 0x30)
-#define GPIOL_IN_AUX1_SELECT	 (		GPIO_BASE + 0x34)
-#define GPIOL_EVENTS_ENABLE		 (		GPIO_BASE + 0x38)
-#define GPIOL_LOCK_ENABLE		 (		GPIO_BASE + 0x3C)
-#define GPIOL_IN_POSEDGE_ENABLE	 (		GPIO_BASE + 0x40)
-#define GPIOL_IN_NEGEDGE_ENABLE	 (		GPIO_BASE + 0x44)
-#define GPIOL_IN_POSEDGE_STATUS	 (		GPIO_BASE + 0x48)
-#define GPIOL_IN_NEGEDGE_STATUS	 (		GPIO_BASE + 0x4C)
-
-/*  GPIO  High Bank Bit Registers*/
-#define GPIOH_OUTPUT_VALUE		 (		GPIO_BASE + 0x80)
-#define GPIOH_OUTPUT_ENABLE		 (		GPIO_BASE + 0x84)
-#define GPIOH_OUT_OPENDRAIN		 (		GPIO_BASE + 0x88)
-#define GPIOH_OUTPUT_INVERT_ENABLE	 (	GPIO_BASE + 0x8C)
-#define GPIOH_OUT_AUX1_SELECT	 (		GPIO_BASE + 0x90)
-#define GPIOH_OUT_AUX2_SELECT	 (		GPIO_BASE + 0x94)
-#define GPIOH_PULLUP_ENABLE		 (		GPIO_BASE + 0x98)
-#define GPIOH_PULLDOWN_ENABLE	 (		GPIO_BASE + 0x9C)
-#define GPIOH_INPUT_ENABLE		 (		GPIO_BASE + 0x0A0)
-#define GPIOH_INPUT_INVERT_ENABLE	 (	GPIO_BASE + 0x0A4)
-#define GPIOH_IN_FILTER_ENABLE	 (		GPIO_BASE + 0x0A8)
-#define GPIOH_IN_EVENTCOUNT_ENABLE	 (	GPIO_BASE + 0x0AC)
-#define GPIOH_READ_BACK			 (		GPIO_BASE + 0x0B0)
-#define GPIOH_IN_AUX1_SELECT	 (		GPIO_BASE + 0x0B4)
-#define GPIOH_EVENTS_ENABLE		 (		GPIO_BASE + 0x0B8)
-#define GPIOH_LOCK_ENABLE		 (		GPIO_BASE + 0x0BC)
-#define GPIOH_IN_POSEDGE_ENABLE	 (		GPIO_BASE + 0x0C0)
-#define GPIOH_IN_NEGEDGE_ENABLE	 (		GPIO_BASE + 0x0C4)
-#define GPIOH_IN_POSEDGE_STATUS	 (		GPIO_BASE + 0x0C8)
-#define GPIOH_IN_NEGEDGE_STATUS	 (		GPIO_BASE + 0x0CC)
-
-/*  Input Conditioning Function Registers*/
-#define GPIO_00_FILTER_AMOUNT	 (		GPIO_BASE + 0x50)
-#define GPIO_00_FILTER_COUNT	 (		GPIO_BASE + 0x52)
-#define GPIO_00_EVENT_COUNT		 (		GPIO_BASE + 0x54)
-#define GPIO_00_EVENTCOMPARE_VALUE	 (	GPIO_BASE + 0x56)
-#define GPIO_01_FILTER_AMOUNT	 (		GPIO_BASE + 0x58)
-#define GPIO_01_FILTER_COUNT	 (		GPIO_BASE + 0x5A)
-#define GPIO_01_EVENT_COUNT		 (		GPIO_BASE + 0x5C)
-#define GPIO_01_EVENTCOMPARE_VALUE	 (	GPIO_BASE + 0x5E)
-#define GPIO_02_FILTER_AMOUNT	 (		GPIO_BASE + 0x60)
-#define GPIO_02_FILTER_COUNT	 (		GPIO_BASE + 0x62)
-#define GPIO_02_EVENT_COUNT		 (		GPIO_BASE + 0x64)
-#define GPIO_02_EVENTCOMPARE_VALUE	 (	GPIO_BASE + 0x66)
-#define GPIO_03_FILTER_AMOUNT	 (		GPIO_BASE + 0x68)
-#define GPIO_03_FILTER_COUNT	 (		GPIO_BASE + 0x6A)
-#define GPIO_03_EVENT_COUNT		 (		GPIO_BASE + 0x6C)
-#define GPIO_03_EVENTCOMPARE_VALUE	 (	GPIO_BASE + 0x6E)
-#define GPIO_04_FILTER_AMOUNT	 (		GPIO_BASE + 0x70)
-#define GPIO_04_FILTER_COUNT	 (		GPIO_BASE + 0x72)
-#define GPIO_04_EVENT_COUNT		 (		GPIO_BASE + 0x74)
-#define GPIO_04_EVENTCOMPARE_VALUE	 (	GPIO_BASE + 0x76)
-#define GPIO_05_FILTER_AMOUNT	 (		GPIO_BASE + 0x78)
-#define GPIO_05_FILTER_COUNT	 (		GPIO_BASE + 0x7A)
-#define GPIO_05_EVENT_COUNT		 (		GPIO_BASE + 0x7C)
-#define GPIO_05_EVENTCOMPARE_VALUE	 (	GPIO_BASE + 0x7E)
-#define GPIO_06_FILTER_AMOUNT	 (		GPIO_BASE + 0x0D0)
-#define GPIO_06_FILTER_COUNT	 (		GPIO_BASE + 0x0D2)
-#define GPIO_06_EVENT_COUNT		 (		GPIO_BASE + 0x0D4)
-#define GPIO_06_EVENTCOMPARE_VALUE	 (	GPIO_BASE + 0x0D6)
-#define GPIO_07_FILTER_AMOUNT	 (		GPIO_BASE + 0x0D8)
-#define GPIO_07_FILTER_COUNT	 (		GPIO_BASE + 0x0DA)
-#define GPIO_07_EVENT_COUNT		 (		GPIO_BASE + 0x0DC)
-#define GPIO_07_EVENTCOMPARE_VALUE	 (	GPIO_BASE + 0x0DE)
-
-/*  R/W GPIO Interrupt &PME Mapper Registers*/
-#define GPIO_MAPPER_X		 (		GPIO_BASE + 0x0E0)
-#define GPIO_MAPPER_Y		 (		GPIO_BASE + 0x0E4)
-#define GPIO_MAPPER_Z		 (		GPIO_BASE + 0x0E8)
-#define GPIO_MAPPER_W		 (		GPIO_BASE + 0x0EC)
-#define GPIO_FE_SELECT_0	 (		GPIO_BASE + 0x0F0)
-#define GPIO_FE_SELECT_1	 (		GPIO_BASE + 0x0F1)
-#define GPIO_FE_SELECT_2	 (		GPIO_BASE + 0x0F2)
-#define GPIO_FE_SELECT_3	 (		GPIO_BASE + 0x0F3)
-#define GPIO_FE_SELECT_4	 (		GPIO_BASE + 0x0F4)
-#define GPIO_FE_SELECT_5	 (		GPIO_BASE + 0x0F5)
-#define GPIO_FE_SELECT_6	 (		GPIO_BASE + 0x0F6)
-#define GPIO_FE_SELECT_7	 (		GPIO_BASE + 0x0F7)
-
-/*  Event Counter Decrement Registers*/
-#define GPIOL_IN_EVENT_DECREMENT	 (	GPIO_BASE + 0x0F8)
-#define GPIOH_IN_EVENT_DECREMENT	 (	GPIO_BASE + 0x0FC)
-
-/*  This is for 286reset compatibility. 0xCange to mat0xc 5535 virtualized stuff.*/
-#define FUNC0		 (	0x90)
-
-
-/*  sworley, PMC register*/
-#define PM_SSD		 (	PMLogic_BASE + 0x00)
-#define PM_SCXA		 (	PMLogic_BASE + 0x04)
-#define PM_SCYA		 (	PMLogic_BASE + 0x08)
-#define PM_SODA		 (	PMLogic_BASE + 0x0C)
-#define PM_SCLK		 (	PMLogic_BASE + 0x10)
-#define PM_SED		 (	PMLogic_BASE + 0x14)
-#define PM_SCXD		 (	PMLogic_BASE + 0x18)
-#define PM_SCYD		 (	PMLogic_BASE + 0x1C)
-#define PM_SIDD		 (	PMLogic_BASE + 0x20)
-#define PM_WKD		 (	PMLogic_BASE + 0x30)
-#define PM_WKXD		 (	PMLogic_BASE + 0x34)
-#define PM_RD		 (	PMLogic_BASE + 0x38)
-#define PM_WKXA		 ( PMLogic_BASE + 0x3C)
-#define PM_FSD		 (	PMLogic_BASE + 0x40)
-#define PM_TSD		 (	PMLogic_BASE + 0x44)
-#define PM_PSD		 ( PMLogic_BASE + 0x48)
-#define PM_NWKD		 (	PMLogic_BASE + 0x4C)
-#define PM_AWKD		 (	PMLogic_BASE + 0x50)
-#define PM_SSC		 (	PMLogic_BASE + 0x54)
-
-
-/* FLASH device macros */
-#define FLASH_TYPE_NONE	0	/* No flash device installed */
-#define FLASH_TYPE_NAND 1	/* NAND device */
-#define FLASH_TYPE_NOR	2	/* NOR device */
-
-#define FLASH_IF_MEM	1	/* Memory or memory-mapped I/O interface for Flash device */
-#define FLASH_IF_IO	2	/* I/O interface for Flash device */
-
-/* Flash Memory Mask values */
-#define FLASH_MEM_DEFAULT	0x00000000
-#define FLASH_MEM_4K		0xFFFFF000
-#define FLASH_MEM_8K		0xFFFFE000
-#define FLASH_MEM_16K		0xFFFFC000
-#define FLASH_MEM_128K		0xFFFE0000
-#define FLASH_MEM_512K		0xFFFC0000
-#define FLASH_MEM_4M		0xFFC00000
-#define FLASH_MEM_8M		0xFF800000
-#define FLASH_MEM_16M		0xFF000000
-
-/* Flash IO Mask values */
-#define FLASH_IO_DEFAULT	0x00000000
-#define FLASH_IO_16B		0x0000FFF0
-#define FLASH_IO_32B		0x0000FFE0
-#define FLASH_IO_64B		0x0000FFC0
-#define FLASH_IO_128B		0x0000FF80
-#define FLASH_IO_256B		0x0000FF00
+#define SMM_OFFSET	0x80400000	/* above 2GB */
+#define SMM_SIZE	128			/* changed SMM_SIZE from 256 KB to 128 KB */

-#endif /* CPU_AMD_LXDEF_H */
+#endif
Index: LinuxBIOSv2/src/include/cpu/amd/vr.h
===================================================================
--- LinuxBIOSv2.orig/src/include/cpu/amd/vr.h	2007-04-30 15:25:28.000000000 -0600
+++ LinuxBIOSv2/src/include/cpu/amd/vr.h	2007-05-01 12:09:15.000000000 -0600
@@ -1,67 +1,56 @@
-/* <LIC_AMD_STD>
- * Copyright (C) 2003-2005 Advanced Micro Devices, Inc.  All Rights Reserved.
- * </LIC_AMD_STD>  */
-//<CTL_AMD_STD>
-//$Id: //bios/main/vsa_ii/inc/vr.h#18 $
-//$Header: //bios/main/vsa_ii/inc/vr.h#18 $
-//$Date: 2005/09/29 $
-//$DateTime: 2005/09/29 11:07:14 $
-//$Change: 65425 $
-//$File: //bios/main/vsa_ii/inc/vr.h $
-//$Revision: #18 $
-//$Author: johnk $
-//</CTL_AMD_STD>
-//<DOC_AMD_STD>
-// Virtual Register USAGE:
-//
-// 	Index: 	AH = Class, AL = Parameter_ID
-// 	Data:	AX = data
-//</DOC_AMD_STD>
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/

-#define VRC_INDEX				0xAC1C	// Index register 
+#ifndef CPU_AMD_VR_H
+#define CPU_AMD_VR_H
+
+#define VRC_INDEX				0xAC1C	// Index register
 #define VRC_DATA				0xAC1E	// Data register
 #define VR_UNLOCK				0xFC53	// Virtual register unlock code
 #define NO_VR					-1		// No virtual registers

#define	VRC_MISCELLANEOUS		0x00	// Miscellaneous Class
-    #define VSA_VERSION_NUM     0x00
+	#define VSA_VERSION_NUM		0x00
    #define HIGH_MEM_ACCESS		0x01
-    #define GET_VSM_INFO        0x02	// Used by INFO
-       #define GET_BASICS       0x00
-       #define GET_EVENT        0x01
-       #define GET_STATISTICS   0x02
-       #define GET_HISTORY      0x03
-       #define GET_HARDWARE     0x04
-       #define GET_ERROR        0x05
-       #define SET_VSM_TYPE     0x06
+	#define GET_VSM_INFO		0x02	// Used by INFO
+	   #define GET_BASICS		0x00
+	   #define GET_EVENT		0x01
+	   #define GET_STATISTICS	0x02
+	   #define GET_HISTORY		0x03
+	   #define GET_HARDWARE		0x04
+	   #define GET_ERROR		0x05
+	   #define SET_VSM_TYPE		0x06
    #define SIGNATURE			0x03
-       #define VSA2_SIGNATURE	0x56534132	// 'VSA2' returned in EAX 
+	   #define VSA2_SIGNATURE	0x56534132	// 'VSA2' returned in EAX

-    #define GET_HW_INFO			0x04
-    #define VSM_VERSION			0x05
+	#define GET_HW_INFO			0x04
+	#define VSM_VERSION			0x05
    #define CTRL_ALT_DEL		0x06
-    #define MSR_ACCESS          0x07
-    #define GET_DESCR_INFO		0x08
-    #define PCI_INT_AB			0x09	// GPIO pins for INTA# and INTB#
-    #define PCI_INT_CD			0x0A	// GPIO pins for INTC# and INTD#	
-    #define WATCHDOG			0x0B	// Watchdog timer
+	#define MSR_ACCESS			0x07
+	#define GET_DESCR_INFO		0x08
+	#define PCI_INT_AB			0x09	// GPIO pins for INTA# and INTB#
+	#define PCI_INT_CD			0x0A	// GPIO pins for INTC# and INTD#
+	#define WATCHDOG			0x0B	// Watchdog timer

-    #define MAX_MISC           	WATCHDOG
+	#define MAX_MISC			WATCHDOG

// NOTE:  Do not change the order of the following registers:
-#define	VRC_AUDIO      			0x01	// XpressAudio Class
-	#define AUDIO_VERSION      	0x00
-	#define PM_STATE        	0x01
-	#define SB_16_IO_BASE   	0x02
-	#define MIDI_BASE       	0x03
-	#define CPU_USAGE       	0x04
-	#define CODEC_TYPE      	0x05
-	#define STATE_INDEX     	0x06
-	#define STATE_DATA      	0x07
-	#define AUDIO_IRQ	      	0x08	// For use by native audio drivers 
+#define	VRC_AUDIO				0x01	// XpressAudio Class
+	#define AUDIO_VERSION		0x00
+	#define PM_STATE			0x01
+	#define SB_16_IO_BASE		0x02
+	#define MIDI_BASE			0x03
+	#define CPU_USAGE			0x04
+	#define CODEC_TYPE			0x05
+	#define STATE_INDEX			0x06
+	#define STATE_DATA			0x07
+	#define AUDIO_IRQ			0x08	// For use by native audio drivers
    #define STATUS_PTR			0x09	// For use by native audio drivers
-	#define MAX_AUDIO           STATUS_PTR
+	#define MAX_AUDIO			STATUS_PTR

#define	VRC_VG					0x02	// SoftVG Class
 #define	VRC_VGA					0x02	// SoftVGA Class
@@ -97,7 +86,7 @@
    		#define VG_CFG_DPMS_V		0x0080	// VSYNC mask bit
    	#define VG_VESA_SV_RST		0x0020	// VESA Save/Restore state flag
    		#define VG_VESA_RST			0x0000	// VESA Restore state
-			#define VG_VESA_SV			0x0020	// VESA Save state 
+			#define VG_VESA_SV			0x0020	// VESA Save state
    	#define VG_FRSH_MODE		0x0002	// Mode refresh flag
    	#define VG_FRSH_TIMINGS		0x0001	// Timings only refresh flag

@@ -194,28 +183,28 @@
    		#define VG_TV_PAL			0x0010	// PAL output format
    		#define VG_TV_HDTV			0x0020	// HDTV output format

-		// The meaning of the VG_TV_RES field is dependent on the selected  
+		// The meaning of the VG_TV_RES field is dependent on the selected
    	// encoder and output format.  The translations are:
    	//		ADV7171 - Not Used
    	//		SAA7127 - Not Used
    	//		ADV7300 - HDTV resolutions only
-		//			LO  -> 720x480p
-		//	   		MED -> 1280x720p
-		//			HI  -> 1920x1080i
-		// 		FS454   - Both SD and HD resolutions	
-		// 			SD Resolutions - NTSC and PAL
-		//				LO  -> 640x480
-		//	   			MED -> 800x600
-		//				HI  -> 1024x768
-		// 			HD Resolutions
-		//				LO  -> 720x480p
-		//	   			MED -> 1280x720p
-		//				HI  -> 1920x1080i
+		//			LO	-> 720x480p
+		//			MED -> 1280x720p
+		//			HI	-> 1920x1080i
+		//		FS454	- Both SD and HD resolutions
+		//			SD Resolutions - NTSC and PAL
+		//				LO	-> 640x480
+		//				MED -> 800x600
+		//				HI	-> 1024x768
+		//			HD Resolutions
+		//				LO	-> 720x480p
+		//				MED -> 1280x720p
+		//				HI	-> 1920x1080i
    	#define VG_TV_RES			0x0780	// TV resolution select mask
    		#define VG_TV_RES_SHIFT		0x0007	// Right shift value
    		#define VG_TV_RES_LO		0x0000	// Low resolution
    		#define VG_TV_RES_MED		0x0080	// Medium resolution
-			#define VG_TV_RES_HI 		0x0100	// High resolution
+			#define VG_TV_RES_HI		0x0100	// High resolution
    	#define VG_TV_PASSTHRU		0x0800	// TV passthru mode

#define	VG_TV_SCALE_ADJ		0x05	// Modifies scaling factors for TV resolutions
@@ -248,33 +237,33 @@
    #define	VG_FT_VESST			0x2C	// Fixed timings, vertical sync start
    #define	VG_FT_VESND			0x2D	// Fixed timings, vertical sync end

-	#define MAX_VGA           	VGA_MEM_SIZE
-//	#define MAX_VG           	VG_FP_OPTION
-//	#define MAX_VG           	VG_START_OFFS_HI
-	#define MAX_VG           	VG_FT_VESND
+	#define MAX_VGA				VGA_MEM_SIZE
+//	#define MAX_VG				VG_FP_OPTION
+//	#define MAX_VG				VG_START_OFFS_HI
+	#define MAX_VG				VG_FT_VESND

#define	VRC_APM					0x03
-    #define REPORT_EVENT		0x00
-    #define CAPABILITIES    	0x01
+	#define REPORT_EVENT		0x00
+	#define CAPABILITIES		0x01
    #define APM_PRESENT		0x02
-	#define MAX_APM           	APM_PRESENT
+	#define MAX_APM				APM_PRESENT

#define	VRC_PM					0x04	// Legacy PM Class
    #define	POWER_MODE			0x00
    #define POWER_STATE			0x01
    #define	DOZE_TIMEOUT		0x02
-	#define	STANDBY_TIMEOUT	   	0x03
-	#define	SUSPEND_TIMEOUT	   	0x04
-    #define PS2_TIMEOUT		    0x05
+	#define	STANDBY_TIMEOUT		0x03
+	#define	SUSPEND_TIMEOUT		0x04
+	#define PS2_TIMEOUT			0x05
    #define RESUME_ON_RING		0x06
    #define VIDEO_TIMEOUT		0x07
    #define	DISK_TIMEOUT		0x08
-	#define	FLOPPY_TIMEOUT	   	0x09
-	#define	SERIAL_TIMEOUT	    0x0A
+	#define	FLOPPY_TIMEOUT		0x09
+	#define	SERIAL_TIMEOUT		0x0A
    #define	PARALLEL_TIMEOUT	0x0B
-	#define IRQ_WAKEUP_MASK	   	0x0C
-//	#define SUSPEND_MODULATION 	0x0D
+	#define IRQ_WAKEUP_MASK		0x0C
+//	#define SUSPEND_MODULATION	0x0D
    #define SLEEP_PIN			0x0E
    #define SLEEP_PIN_ATTR		0x0F
 //	#define SMI_WAKEUP_MASK		0x10
@@ -286,29 +275,29 @@
 //	#define PM_S3_CLOCKS		0x14
 //	#define PM_S4_CLOCKS		0x15
 //	#define PM_S5_CLOCKS		0x16
-    #define PM_S0_LED           0x17
-    #define PM_S1_LED           0x18
-    #define PM_S2_LED           0x19
-    #define PM_S3_LED           0x1A
-    #define PM_S4_LED           0x1B
-    #define PM_S5_LED           0x1C
+	#define PM_S0_LED			0x17
+	#define PM_S1_LED			0x18
+	#define PM_S2_LED			0x19
+	#define PM_S3_LED			0x1A
+	#define PM_S4_LED			0x1B
+	#define PM_S5_LED			0x1C
    #define PM_LED_GPIO			0x1D
-    #define PM_IMM_LED			0x1E
-    #define PM_PWR_LEDS			0x1F
-	    #define MB_LED0				0x01
-	    #define MB_LED1				0x02
-	    #define MB_LED2				0x04
-	    #define MB_LED3				0x08
-	    #define SIO_LED0			0x10
-	    #define SIO_LED1			0x20
-	    #define SIO_LED2			0x40
-	    #define SIO_LED3			0x80
+	#define PM_IMM_LED			0x1E
+	#define PM_PWR_LEDS			0x1F
+		#define MB_LED0				0x01
+		#define MB_LED1				0x02
+		#define MB_LED2				0x04
+		#define MB_LED3				0x08
+		#define SIO_LED0			0x10
+		#define SIO_LED1			0x20
+		#define SIO_LED2			0x40
+		#define SIO_LED3			0x80
    #define PM_PME_MASK			0x20
-    #define MAX_PM              PM_PME_MASK
+	#define MAX_PM				PM_PME_MASK

#define VRC_INFRARED			0x05
-	#define MAX_INFRARED        NO_VR
+	#define MAX_INFRARED		NO_VR

#define	VRC_TV					0x06	// TV Encoder Class
    #define TV_ENCODER_TYPE		0x00
@@ -319,31 +308,31 @@
    #define TV_CONTRAST			0x05
    #define TV_OUTPUT			0x06
    #define TV_TIMING			0x10	// 0x10...0x1D are all timings
-	#define MAX_TV           	TV_TIMING
+	#define MAX_TV				TV_TIMING

#define VRC_EXTERNAL_AMP		0x07
-    #define EAPD_VERSION        0x00
-    #define AMP_POWER          	0x01
-	   #define AMP_OFF          0x00
-	   #define AMP_ON           0x01
-	#define AMP_TYPE            0x02
-	#define MAX_EXTERNAL_AMP    	AMP_TYPE
+	#define EAPD_VERSION		0x00
+	#define AMP_POWER			0x01
+	   #define AMP_OFF			0x00
+	   #define AMP_ON			0x01
+	#define AMP_TYPE			0x02
+	#define MAX_EXTERNAL_AMP		AMP_TYPE

#define	VRC_ACPI				0x08
-    #define	ENABLE_ACPI			0x00	// Enable ACPI Mode
-	#define SCI_IRQ			   	0x01	// Set the IRQ the SCI is mapped to, sysbios use.
+	#define	ENABLE_ACPI			0x00	// Enable ACPI Mode
+	#define SCI_IRQ				0x01	// Set the IRQ the SCI is mapped to, sysbios use.
    #define ACPINVS_LO			0x02	// new calls to send 32bit physAddress of
-	#define ACPINVS_HI		  	0x03	// ACPI NVS region to VSA
+	#define ACPINVS_HI			0x03	// ACPI NVS region to VSA
    #define GLOBAL_LOCK			0x04	// read requests semaphore, write clears
    #define ACPI_UNUSED1		0x05
    #define RW_PIRQ				0x06	// read/write PCI IRQ router regs in SB Func0 cfg space
    #define SLPB_CLEAR			0x07	// clear sleep button GPIO status's
    #define PIRQ_ROUTING		0x08	// read the PCI IRQ routing based on BIOS setup
-	#define ACPI_UNUSED2		0x09	
-	#define ACPI_UNUSED3		0x0A	
+	#define ACPI_UNUSED2		0x09
+	#define ACPI_UNUSED3		0x0A
    #define PIC_INTERRUPT		0x0B
    #define ACPI_PRESENT		0x0C
    #define	ACPI_GEN_COMMAND	0x0D
@@ -351,47 +340,47 @@
    #define	ACPI_GEN_PARAM2		0x0F
    #define	ACPI_GEN_PARAM3		0x10
    #define	ACPI_GEN_RETVAL		0x11
-	#define MAX_ACPI	        ACPI_GEN_RETVAL
+	#define MAX_ACPI			ACPI_GEN_RETVAL

#define	VRC_ACPI_OEM			0x09
-	#define MAX_ACPI_OEM        NO_VR
+	#define MAX_ACPI_OEM		NO_VR

-#define VRC_POWER               0x0A
-    #define BATTERY_UNITS       0x00	// No. battery units
-    #define BATTERY_SELECT      0x01
-    #define AC_STATUS           0x02
+#define VRC_POWER				0x0A
+	#define BATTERY_UNITS		0x00	// No. battery units
+	#define BATTERY_SELECT		0x01
+	#define AC_STATUS			0x02
    #define BATTERY_STATUS		0x03
    #define BATTERY_FLAG		0x04
    #define BATTERY_PERCENTAGE	0x05
-    #define BATTERY_TIME        0x06
-	#define MAX_POWER           BATTERY_TIME
+	#define BATTERY_TIME		0x06
+	#define MAX_POWER			BATTERY_TIME

#define VRC_OHCI				0x0B	// OHCI Class
-    #define SET_LED             0x00
-    #define INIT_OHCI			0x01
-    #define MAX_OHCI            INIT_OHCI
-
-#define VRC_KEYBOARD            0x0C	// Kbd Controller Class
-    #define KEYBOARD_PRESENT    0x00
-    #define SCANCODE            0x01
-    #define MOUSE_PRESENT		0x02
-    #define MOUSE_BUTTONS       0x03
-	#define MOUSE_XY            0x04
-	#define MAX_KEYBOARD        MOUSE_XY
+	#define SET_LED				0x00
+	#define INIT_OHCI			0x01
+	#define MAX_OHCI			INIT_OHCI
+
+#define VRC_KEYBOARD			0x0C	// Kbd Controller Class
+	#define KEYBOARD_PRESENT	0x00
+	#define SCANCODE			0x01
+	#define MOUSE_PRESENT		0x02
+	#define MOUSE_BUTTONS		0x03
+	#define MOUSE_XY			0x04
+	#define MAX_KEYBOARD		MOUSE_XY

-#define VRC_DDC     			0x0D	// Video DDC Class
-	#define VRC_DDC_ENABLE 		0x00	// Enable/disable register
+#define VRC_DDC					0x0D	// Video DDC Class
+	#define VRC_DDC_ENABLE		0x00	// Enable/disable register
    	#define DDC_DISABLE		0x00
-		#define DDC_ENABLE 		0x01
-	#define VRC_DDC_IO	  		0x01	// A non-zero value for safety
-	#define MAX_DDC           	VRC_DDC_IO
+		#define DDC_ENABLE		0x01
+	#define VRC_DDC_IO			0x01	// A non-zero value for safety
+	#define MAX_DDC				VRC_DDC_IO

#define VRC_DEBUGGER			0x0E
-	#define MAX_DEBUGGER        NO_VR
-						   
+	#define MAX_DEBUGGER		NO_VR
+

#define	VRC_STR					0x0F		// Virtual Register class
    #define RESTORE_ADDR		0x00		// Physical address of MSR restore table
@@ -406,16 +395,16 @@
    #define	VRC_HIB_VERSION		0x03		// Read COP8 version
    #define	VRC_HIB_SERIAL		0x04		// Read 8 byte serial number
    #define	VRC_HIB_USRBTN		0x05		// Read POST button pressed status
-	#define MAX_COP8	        NO_VR
+	#define MAX_COP8			NO_VR

#define	VRC_OWL					0x11		// Virtual Register class
    #define	VRC_OWL_DAC			0x00		// DAC (Backlight) Control
-	#define	VRC_OWL_GPIO 		0x01		// GPIO Control
+	#define	VRC_OWL_GPIO		0x01		// GPIO Control
    #define MAX_OWL				VRC_OWL_GPIO

#define	VRC_SYSINFO				0x12		// Virtual Register class
    #define	VRC_SI_VERSION				0x00		// Sysinfo VSM version
-	#define	VRC_SI_CPU_MHZ				0x01	// CPU speed in MHZ 
+	#define	VRC_SI_CPU_MHZ				0x01	// CPU speed in MHZ
    #define	VRC_SI_CHIPSET_BASE_LOW		0x02
    #define	VRC_SI_CHIPSET_BASE_HI		0x03
    #define	VRC_SI_CHIPSET_ID			0x04
@@ -470,17 +459,42 @@
    #define VRC_CS_UART2		0x02
    #define MAX_CHIPSET			VRC_CS_UART2

-#define VRC_THERMAL     0x15
-    #define VRC_THERMAL_CURR_RTEMP      0x00        // read only
-    #define VRC_THERMAL_CURR_LTEMP      0x01        // read only
-    #define VRC_THERMAL_FAN             0x02
-    #define VRC_THERMAL_LOW_THRESHOLD   0x03
-    #define VRC_THERMAL_HIGH_THRESHOLD  0x04
-    #define VRC_THERMAL_INDEX           0x05
-    #define VRC_THERMAL_DATA            0x06
-    #define VRC_THERMAL_SMB_ADDRESS     0x07
-    #define VRC_THERMAL_SMB_INDEX       0x08
-    #define VRC_THERMAL_SMB_DATA        0x09
-    #define MAX_THERMAL         VRC_THERMAL_SMB_DATA
-
-#define MAX_VR_CLASS	  		VRC_THERMAL
+#define VRC_THERMAL		0x15
+	#define VRC_THERMAL_CURR_RTEMP		0x00		// read only
+	#define VRC_THERMAL_CURR_LTEMP		0x01		// read only
+	#define VRC_THERMAL_FAN				0x02
+	#define VRC_THERMAL_LOW_THRESHOLD	0x03
+	#define VRC_THERMAL_HIGH_THRESHOLD	0x04
+	#define VRC_THERMAL_INDEX			0x05
+	#define VRC_THERMAL_DATA			0x06
+	#define VRC_THERMAL_SMB_ADDRESS		0x07
+	#define VRC_THERMAL_SMB_INDEX		0x08
+	#define VRC_THERMAL_SMB_DATA		0x09
+	#define MAX_THERMAL			VRC_THERMAL_SMB_DATA
+
+#define MAX_VR_CLASS			VRC_THERMAL
+
+/*
+ * Write to a Virtual Register
+ * AX = Class/Index
+ * CX = data to write
+ */
+static inline void vrWrite(uint16_t wClassIndex, uint16_t wData)
+{
+	outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
+	outw(wData, VRC_DATA);
+}
+
+ /*
+ * Read from a Virtual Register
+ * AX = Class/Index
+ * Returns a 16-bit word of data
+ */
+static inline uint16_t vrRead(uint16_t wClassIndex)
+{
+	uint16_t wData;
+	outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
+	wData = inw(VRC_DATA);
+	return wData;
+}
+#endif
Index: LinuxBIOSv2/src/include/spd.h
===================================================================
--- LinuxBIOSv2.orig/src/include/spd.h	2007-04-30 15:25:28.000000000 -0600
+++ LinuxBIOSv2/src/include/spd.h	2007-05-01 12:09:15.000000000 -0600
@@ -16,7 +16,7 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */

/*
@@ -85,6 +85,17 @@
 #define SPD_INTEL_SPEC_FOR_FREQUENCY       126 /* Intel specification for frequency */
 #define SPD_INTEL_SPEC_100_MHZ             127 /* Intel specification details for 100MHz support */

+/* DRAM specifications use the following naming conventions for SPD locations */
+#define SPD_tRP                             SPD_MIN_ROW_PRECHARGE_TIME
+#define SPD_tRRD                            SPD_MIN_ROWACTIVE_TO_ROWACTIVE
+#define SPD_tRCD                            SPD_MIN_RAS_TO_CAS_DELAY
+#define SPD_tRAS                            SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
+#define SPD_BANK_DENSITY                    SPD_DENSITY_OF_EACH_ROW_ON_MODULE
+#define SPD_ADDRESS_CMD_HOLD                SPD_CMD_SIGNAL_INPUT_HOLD_TIME
+#define SPD_tRC									41	/* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
+#define SPD_tRFC								42	/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
+
+
 /* SPD_MEMORY_TYPE values. */
 #define SPD_MEMORY_TYPE_FPM_DRAM         1
 #define SPD_MEMORY_TYPE_EDO              2
@@ -103,30 +114,30 @@
 #define SPD_VOLTAGE_SSTL2                4 /* SSTL 2.5 */

/* SPD_DIMM_CONFIG_TYPE values. */
-#define ERROR_SCHEME_NONE                0
-#define ERROR_SCHEME_PARITY              1
-#define ERROR_SCHEME_ECC                 2
+#define ERROR_SCHEME_NONE		0
+#define ERROR_SCHEME_PARITY		1
+#define ERROR_SCHEME_ECC		2

/* SPD_ACCEPTABLE_CAS_LATENCIES values. */
 // TODO: Check values.
-#define SPD_CAS_LATENCY_1_0              0x01
-#define SPD_CAS_LATENCY_1_5              0x02
-#define SPD_CAS_LATENCY_2_0              0x04
-#define SPD_CAS_LATENCY_2_5              0x08
-#define SPD_CAS_LATENCY_3_0              0x10
-#define SPD_CAS_LATENCY_3_5              0x20
-#define SPD_CAS_LATENCY_4_0              0x40
+#define SPD_CAS_LATENCY_1_0		0x01
+#define SPD_CAS_LATENCY_1_5		0x02
+#define SPD_CAS_LATENCY_2_0		0x04
+#define SPD_CAS_LATENCY_2_5		0x08
+#define SPD_CAS_LATENCY_3_0		0x10
+#define SPD_CAS_LATENCY_3_5		0x20
+#define SPD_CAS_LATENCY_4_0		0x40

/* SPD_SUPPORTED_BURST_LENGTHS values. */
-#define SPD_BURST_LENGTH_1               1
-#define SPD_BURST_LENGTH_2               2
-#define SPD_BURST_LENGTH_4               4
-#define SPD_BURST_LENGTH_8               8
-#define SPD_BURST_LENGTH_PAGE            (1 << 7)
+#define SPD_BURST_LENGTH_1		1
+#define SPD_BURST_LENGTH_2		2
+#define SPD_BURST_LENGTH_4		4
+#define SPD_BURST_LENGTH_8		8
+#define SPD_BURST_LENGTH_PAGE	(1<<7)

/* SPD_MODULE_ATTRIBUTES values. */
-#define MODULE_BUFFERED                  1
-#define MODULE_REGISTERED                2
+#define MODULE_BUFFERED			1
+#define MODULE_REGISTERED		2

#endif /* _SPD_H_ */

Index: LinuxBIOSv2/src/cpu/amd/model_lx/cache_as_ram.inc
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/cpu/amd/model_lx/cache_as_ram.inc	2007-05-01 12:09:15.000000000 -0600
@@ -0,0 +1,370 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/
+
+
+#define	LX_STACK_BASE		DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
+#define	LX_STACK_END		LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
+
+#define	LX_NUM_CACHELINES	0x080	/* there are 128lines per way */
+#define	LX_CACHELINE_SIZE	0x020	/* there are 32bytes per line */
+#define	LX_CACHEWAY_SIZE	(LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
+#define	CR0_CD				0x40000000	/* bit 30 = Cache Disable */
+#define	CR0_NW				0x20000000	/* bit 29 = Not Write Through */
+#include <cpu/amd/lxdef.h>
+/***************************************************************************
+/**
+/**	DCacheSetup
+/**
+/**	Setup data cache for  use as RAM for a stack.
+/**
+/***************************************************************************/
+DCacheSetup:
+
+	invd
+	/* set cache properties */
+	movl	$CPU_RCONF_DEFAULT, %ecx
+	rdmsr
+	movl	$0x010010000, %eax		/*1MB system memory in write back 1|00100|00 */
+	wrmsr
+
+	/* in LX DCDIS is set after POR which disables the cache..., clear this bit */
+	movl	CPU_DM_CONFIG0,%ecx
+	rdmsr
+	andl	$(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax	/* TODO: make consistent with i$ init,	either whole reg = 0,  or just this bit... */
+	wrmsr
+
+	/* get cache timing params from BIOS config data locations and apply */
+	/* fix delay controls for DM and IM arrays */
+	/* fix delay controls for DM and IM arrays */
+	movl	$CPU_BC_MSS_ARRAY_CTL0, %ecx
+	xorl	%edx, %edx
+	movl	$0x2814D352, %eax
+	wrmsr
+
+	movl	$CPU_BC_MSS_ARRAY_CTL1, %ecx
+	xorl	%edx, %edx
+	movl	$0x1068334D, %eax
+	wrmsr
+
+	movl	$CPU_BC_MSS_ARRAY_CTL2, %ecx
+	movl	$0x00000106, %edx
+	movl	$0x83104104, %eax
+	wrmsr
+
+	movl	$GLCP_FIFOCTL, %ecx
+	rdmsr
+	movl	$0x00000005, %edx
+	wrmsr
+
+	/* Enable setting */
+	movl	$CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
+	xorl	%edx, %edx
+	movl	$0x01, %eax
+	wrmsr
+
+	/* Get cleaned up. */
+	xorl	%edi, %edi
+	xorl	%esi, %esi
+	xorl	%ebp, %ebp
+
+	/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */
+	/* remember,  there is NO stack yet... */
+
+	/* Tell cache we want to fill WAY 0 starting at the top */
+	xorl	%edx, %edx
+	xorl	%eax, %eax
+	movl	$CPU_DC_INDEX, %ecx
+	wrmsr
+
+	/* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
+	movl	$LX_STACK_BASE, %ebp	/* init to start address */
+	orl		$1, %ebp				/* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
+
+	/* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
+	movl	$LX_NUM_CACHELINES, %edi
+DCacheSetupFillWay:
+
+	/* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
+	/* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
+	movw	$0x04, %si
+	xorl	%edx, %edx
+	xorl	%eax, %eax
+	movl	$CPU_DC_DATA, %ecx
+DCacheSetup_quadWordLoop:
+	wrmsr
+	decw	%si
+	jnz	DCacheSetup_quadWordLoop
+
+	/* Set the tag for this line,  need to do this for every new cache line to validate it! */
+	/* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
+	xorl	%edx, %edx
+	movl	%ebp, %eax
+	movl	$CPU_DC_TAG, %ecx
+	wrmsr
+
+	/* switch to next line */
+	/* lines are in Bits10:4 */
+	/* when index is crossing 0x7F -> 0x80	writing a RSVD bit as 0x80 is not a valid CL anymore! */
+	movl	$CPU_DC_INDEX, %ecx
+	rdmsr
+	addl	$0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */
+	wrmsr
+
+	decl	%edi
+	jnz	DCacheSetupFillWay
+
+	/* 1 Way has been filled,  forward start address for next Way,	terminate if we have reached end of desired address range */
+	addl	$LX_CACHEWAY_SIZE, %ebp
+	cmpl	$LX_STACK_END, %ebp
+	jge	leave_DCacheSetup
+	movl	$LX_NUM_CACHELINES, %edi
+
+	/* switch to next way */
+	movl	$CPU_DC_INDEX, %ecx
+	rdmsr
+	addl	$0x01, %eax
+	andl	$0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */
+	wrmsr
+
+	jmp	DCacheSetupFillWay
+
+leave_DCacheSetup:
+	xorl	%edi, %edi
+	xorl	%esi, %esi
+	xorl	%ebp, %ebp
+
+	/* Disable the cache,  but ... DO NOT INVALIDATE the tags. */
+	/* Memory reads and writes will all hit in the cache. */
+	/* Cache updates and memory write-backs will not occur ! */
+	movl	%cr0, %eax
+	orl		$(CR0_CD + CR0_NW), %eax	/* set the CD and NW bits */
+	movl	%eax, %cr0
+
+	/* Now point sp to the cached stack. */
+	/* The stack will be fully functional at this location. No system memory is required at all ! */
+	/* set up the stack pointer */
+	movl	$LX_STACK_END, %eax
+	movl	%eax, %esp
+
+	/* test the stack*/
+	movl	$0x0F0F05A5A, %edx
+	pushl	%edx
+	popl	%ecx
+	cmpl	%ecx, %edx
+	je	DCacheSetupGood
+	movb	$0xC5, %al
+	outb	%al, $0x80
+DCacheSetupBad:
+	hlt		/* issues */
+	jmp DCacheSetupBad
+DCacheSetupGood:
+
+	/* Go do early init and memory setup */
+	call	cache_as_ram_main
+
+	/* If you wanted to maintain the stack in memory you would need to set the tags as dirty
+	  so the wbinvd would push out the old stack contents to memory */
+	/* Clear the cache, the following code from crt0.S.lb will setup a new stack*/
+	wbinvd
+
+/* the following code is from crt0.S.lb */
+/* This takes the place of the post-CAR funtions that the K8 uses to setup the stack and copy LB low.*/
+
+#ifndef CONSOLE_DEBUG_TX_STRING
+	/* uses:	 esp, ebx, ax, dx */
+# define __CRT_CONSOLE_TX_STRING(string) \
+	mov	string, %ebx	; \
+	CALLSP(crt_console_tx_string)
+
+# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+#  define CONSOLE_DEBUG_TX_STRING(string)        __CRT_CONSOLE_TX_STRING(string)
+# else
+#  define CONSOLE_DEBUG_TX_STRING(string)
+# endif
+#endif
+
+	/* clear boot_complete flag */
+	xorl	%ebp, %ebp
+__main:
+	CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
+
+	/*
+	 *	Copy data into RAM and clear the BSS. Since these segments
+	 *	isn't really that big we just copy/clear using bytes, not
+	 *	double words.
+	 */
+	intel_chip_post_macro(0x11)		/* post 11 */
+
+	cld				/* clear direction flag */
+
+	/* copy linuxBIOS from it's initial load location to
+	 * the location it is compiled to run at.
+	 * Normally this is copying from FLASH ROM to RAM.
+	 */
+#if !CONFIG_COMPRESS
+	movl	$_liseg, %esi
+	movl	$_iseg,  %edi
+	movl	$_eiseg, %ecx
+	subl	%edi, %ecx
+	rep	movsb
+#else
+	leal	4+_liseg, %esi
+	leal	_iseg, %edi
+	movl	%ebp, %esp	/* preserve %ebp */
+	movl	$-1, %ebp	/* last_m_off = -1 */
+	jmp	dcl1_n2b
+
+/* ------------- DECOMPRESSION -------------
+
+ Input:
+   %esi - source
+   %edi - dest
+   %ebp - -1
+   cld
+
+ Output:
+   %eax - 0
+   %ecx - 0
+*/
+
+.macro getbit bits
+.if	\bits == 1
+	addl	%ebx, %ebx
+	jnz	1f
+.endif
+	movl	(%esi), %ebx
+	subl	$-4, %esi	/* sets carry flag */
+	adcl	%ebx, %ebx
+1:
+.endm
+
+decompr_literals_n2b:
+	movsb
+
+decompr_loop_n2b:
+	addl	%ebx, %ebx
+	jnz	dcl2_n2b
+dcl1_n2b:
+	getbit	32
+dcl2_n2b:
+	jc	decompr_literals_n2b
+	xorl	%eax, %eax
+	incl	%eax		/* m_off = 1 */
+loop1_n2b:
+	getbit	1
+	adcl	%eax, %eax	/* m_off = m_off*2 + getbit() */
+	getbit	1
+	jnc	loop1_n2b	/* while(!getbit()) */
+	xorl	%ecx, %ecx
+	subl	$3, %eax
+	jb	decompr_ebpeax_n2b	/* if (m_off == 2) goto decompr_ebpeax_n2b ? */
+	shll	$8, %eax
+	movb	(%esi), %al	/* m_off = (m_off - 3)*256 + src[ilen++] */
+	incl	%esi
+	xorl	$-1, %eax
+	jz	decompr_end_n2b	/* if (m_off == 0xffffffff) goto decomp_end_n2b */
+	movl	%eax, %ebp	/* last_m_off = m_off ?*/
+decompr_ebpeax_n2b:
+	getbit	1
+	adcl	%ecx, %ecx	/* m_len = getbit() */
+	getbit	1
+	adcl	%ecx, %ecx	/* m_len = m_len*2 + getbit()) */
+	jnz	decompr_got_mlen_n2b	/* if (m_len == 0) goto decompr_got_mlen_n2b */
+	incl	%ecx		/* m_len++ */
+loop2_n2b:
+	getbit	1
+	adcl	%ecx, %ecx	/* m_len = m_len*2 + getbit() */
+	getbit	1
+	jnc	loop2_n2b	/* while(!getbit()) */
+	incl	%ecx
+	incl	%ecx		/* m_len += 2 */
+decompr_got_mlen_n2b:
+	cmpl	$-0xd00, %ebp
+	adcl	$1, %ecx	/* m_len = m_len + 1 + (last_m_off > 0xd00) */
+	movl	%esi, %edx
+	leal	(%edi,%ebp), %esi	/* m_pos = dst + olen + -m_off  */
+	rep
+	movsb			/* dst[olen++] = *m_pos++ while(m_len > 0) */
+	movl	%edx, %esi
+	jmp	decompr_loop_n2b
+decompr_end_n2b:
+	intel_chip_post_macro(0x12)		/* post 12 */
+
+	movl	%esp, %ebp
+#endif
+
+	CONSOLE_DEBUG_TX_STRING($str_pre_main)
+	leal	_iseg, %edi
+	jmp	*%edi
+
+.Lhlt:
+	intel_chip_post_macro(0xee)	/* post fail ee */
+	hlt
+	jmp	.Lhlt
+
+#ifdef __CRT_CONSOLE_TX_STRING
+	/* Uses esp, ebx, ax, dx  */
+crt_console_tx_string:
+	mov	(%ebx), %al
+	inc	%ebx
+	cmp	$0, %al
+	jne	9f
+	RETSP
+9:
+/* Base Address */
+#ifndef TTYS0_BASE
+#define TTYS0_BASE	0x3f8
+#endif
+/* Data */
+#define TTYS0_RBR (TTYS0_BASE+0x00)
+
+/* Control */
+#define TTYS0_TBR TTYS0_RBR
+#define TTYS0_IER (TTYS0_BASE+0x01)
+#define TTYS0_IIR (TTYS0_BASE+0x02)
+#define TTYS0_FCR TTYS0_IIR
+#define TTYS0_LCR (TTYS0_BASE+0x03)
+#define TTYS0_MCR (TTYS0_BASE+0x04)
+#define TTYS0_DLL TTYS0_RBR
+#define TTYS0_DLM TTYS0_IER
+
+/* Status */
+#define TTYS0_LSR (TTYS0_BASE+0x05)
+#define TTYS0_MSR (TTYS0_BASE+0x06)
+#define TTYS0_SCR (TTYS0_BASE+0x07)
+
+	mov	%al, %ah
+10:	mov	$TTYS0_LSR, %dx
+	inb	%dx, %al
+	test	$0x20, %al
+	je	10b
+	mov	$TTYS0_TBR, %dx
+	mov	%ah, %al
+	outb	%al, %dx
+
+	jmp crt_console_tx_string
+#endif /* __CRT_CONSOLE_TX_STRING */
+
+#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+.section ".rom.data"
+str_copying_to_ram:  .string "Copying LinuxBIOS to ram.\r\n"
+str_pre_main:        .string "Jumping to LinuxBIOS.\r\n"
+.previous
+
+#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
Index: LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c
===================================================================
--- LinuxBIOSv2.orig/src/cpu/amd/model_lx/model_lx_init.c	2007-05-01 12:07:16.000000000 -0600
+++ LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c	2007-05-01 12:09:25.000000000 -0600
@@ -1,3 +1,9 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -22,7 +28,6 @@
    printk_debug("model_lx_init\n");

/* Turn on caching if we haven't already */
-	
    x86_enable_cache();

/* Enable the local cpu apics */
@@ -36,7 +41,7 @@
    outb(0x02,0x92);
    printk_debug("A20 (0x92): %d\n",inb(0x92));

-	printk_debug("model_lx_init DONE\n");
+	printk_debug("CPU model_lx_init DONE\n");
 };

static struct device_operations cpu_dev_ops = {

[LinuxBIOS] [patch 1/4] Geode LX: CPU

[Uwe Hermann]

On Tue, May 01, 2007 at 04:48:28PM -0600, Marc Jones wrote:
> This patch adds support for the AMD Geode LX CPU.
>
> Signed-off-by: Marc Jones
> Index: LinuxBIOSv2/src/cpu/amd/model_lx/cpubug.c
>
> --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/cpubug.c	2007-04-30 15:25:27.000000000 -0600
> +++ LinuxBIOSv2/src/cpu/amd/model_lx/cpubug.c	2007-05-01 12:09:15.000000000 -0600
> @@ -1,35 +1,18 @@
> +/*
> +* Copyright (C) 2007 Advanced Micro Devices
> +*/

This is not enough, sorry. The copyright being with AMD is fine, but we
need a license statement, too. Please use the common LinuxBIOS license
header in _all_ files:

http://linuxbios.org/Development_Guidelines#Common_License_Header

Thanks!

(further review of the code coming soon)

Uwe.

[LinuxBIOS] Geode LX: CPU

[Jordan Crouse]

On 02/05/07 01:37 +0200, Uwe Hermann wrote:
> > ===================================================================
> > --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/cpubug.c	2007-04-30 15:25:27.000000000 -0600
> > +++ LinuxBIOSv2/src/cpu/amd/model_lx/cpubug.c	2007-05-01 12:09:15.000000000 -0600
> > @@ -1,35 +1,18 @@
> > +/*
> > +* Copyright (C) 2007 Advanced Micro Devices
> > +*/
>
> This is not enough, sorry. The copyright being with AMD is fine, but we
> need a license statement, too. Please use the common LinuxBIOS license
> header in _all_ files:

This file (and others) already existed in the repository - we don't
want to presume to assign the license and copyright for code we didn't
write.  I'll make a patch adding the license to the
files as they exist now, and CC the original authors to sign off on it.

Jordan

[LinuxBIOS] [patch 1/4] Geode LX: CPU

[Peter Stuge]

On Tue, May 01, 2007 at 04:48:28PM -0600, Marc Jones wrote:
> -void bug784(void)

What about all this bug and engineering note related code?

//Peter

[LinuxBIOS] [patch 1/4] Geode LX: CPU

[ron minnich]

I'm good with this patch as is, with only the license header change required.

If you can put the patch back in with the header I will ack it.

thanks

ron
p.s. we just have to be very careful about provenance nowadays, given
the spate of lawsuits hitting the courts in the US.

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Marc Jones]

This patch adds support for the AMD Norwich development platform
based on the Geode LX processor.  The Norwich is the canonical 
Geode reference, and will server as a good basis for other
Geode based platforms.

Signed-off-by: Marc Jones

Index: LinuxBIOSv2/src/mainboard/amd/norwich/Config.lb
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/Config.lb	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,189 @@
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE			= ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE	  = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_PIRQ_TABLE
+	object irq_tables.o
+end
+	#object reset.o
+
+
+if USE_DCACHE_RAM
+	#compile cache_as_ram.c to auto.inc
+	makerule ./cache_as_ram_auto.inc
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+			action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+			action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+	end
+end
+
+
+
+##
+## Romcc output
+##
+#makerule ./failover.E
+#	depends "$(MAINBOARD)/failover.c ./romcc"
+#	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+#end
+#
+#makerule ./failover.inc
+#	depends "$(MAINBOARD)/failover.c ./romcc"
+#	action "./romcc	   -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+#end
+#
+#makerule ./auto.E
+#	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
+#	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+#end
+#makerule ./auto.inc
+#	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+#	action	"./romcc	-mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+#end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+#	mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+
+if USE_DCACHE_RAM
+	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
+	mainboardinit ./cache_as_ram_auto.inc
+end
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/amd/lx
+	register "video_size_MB" = "8" # 8,16,32MB see softvg spec for supported modes per size
+	device pci_domain 0 on
+		device pci 1.0 on end	# Northbridge
+		device pci 1.1 on end	# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			register "lpc_serirq_enable" = "0x00001002"
+			register "lpc_serirq_polarity" = "0x0000EFFD"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "1"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "1"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci b.0 on end	# Slot 3
+			device pci c.0 on end	# Slot 4
+			device pci d.0 on end	# Slot 1
+			device pci e.0 on end	# Slot 2
+			device pci f.0 on end	# ISA Bridge
+			device pci f.2 on end	# IDE Controller
+			device pci f.3 on end	# Audio
+			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+
+end
+
Index: LinuxBIOSv2/src/mainboard/amd/norwich/Options.lb
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/Options.lb	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,179 @@
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_VIDEO_MB
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE  = 256*1024
+
+###
+### Build options
+###
+default CONFIG_CONSOLE_VGA=0
+default CONFIG_VIDEO_MB=8
+default CONFIG_PCI_ROM_RUN=0
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## no MP table
+##
+default HAVE_MP_TABLE=0
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=0
+
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=6
+#object irq_tables.o
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=0
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+default FALLBACK_SIZE = 131072
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xc8000
+default DCACHE_RAM_SIZE=0x08000
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+
+default _RAMBASE = 0x00004000
+
+default CONFIG_ROM_PAYLOAD     = 1
+
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+end
+
Index: LinuxBIOSv2/src/mainboard/amd/norwich/auto.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/auto.c	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,92 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/geode_post_code.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+#define POST_CODE(x) outb(x, 0x80)
+
+#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
+#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+		return smbus_read_byte(device, address);
+}
+
+#define ManualConf 0		/* Do automatic strapped PLL config */
+#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
+#define PLLMSRlo 0x02000030
+#define DIMM0 0xA0
+#define DIMM1 0xA2
+#include "northbridge/amd/lx/raminit.h"
+#include "northbridge/amd/lx/pll_reset.c"
+#include "northbridge/amd/lx/raminit.c"
+#include "sdram/generic_sdram.c"
+#include "cpu/amd/model_lx/cpureginit.c"
+#include "cpu/amd/model_lx/syspreinit.c"
+
+static void msr_init(void)
+{
+	/* Setup access to the MC for low memory. Note MC not setup yet. */
+	__builtin_wrmsr(CPU_RCONF_DEFAULT,	 0x10f3bf00, 0x24fffc02);
+
+	__builtin_wrmsr(MSR_GLIU0 + 0x20, 0xfff80, 0x20000000);
+	__builtin_wrmsr(MSR_GLIU0 + 0x21, 0x80fffe0, 0x20000000);
+
+	__builtin_wrmsr(MSR_GLIU1 + 0x20, 0xfff80, 0x20000000);
+	__builtin_wrmsr(MSR_GLIU1 + 0x21, 0x80fffe0, 0x20000000);
+}
+
+static void mb_gpio_init(void)
+{
+	/* Early mainboard specific GPIO setup */
+}
+
+static void main(unsigned long bist)
+{
+	static const struct mem_controller memctrl [] = {
+		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+	};
+
+	SystemPreInit();
+	msr_init();
+
+	cs5536_early_setup();
+
+	/* NOTE: must do this AFTER the early_setup!
+	 * it is counting on some early MSR setup
+	 * for cs5536
+	 */
+	/* cs5536_disable_internal_uart	 disable them for now, set them up later...*/
+	cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
+	mb_gpio_init();
+	uart_init();
+	console_init();
+
+	pll_reset(ManualConf);
+
+	cpuRegInit();
+
+	sdram_initialize(1, memctrl);
+
+	/* Check all of memory */
+	//ram_check(0x00000000, 640*1024);
+}
Index: LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,118 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/geode_post_code.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+#define POST_CODE(x) outb(x, 0x80)
+
+#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
+#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+		return smbus_read_byte(device, address);
+}
+
+#define ManualConf 0		/* Do automatic strapped PLL config */
+#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
+#define PLLMSRlo 0x02000030
+#define DIMM0 0xA0
+#define DIMM1 0xA2
+#include "northbridge/amd/lx/raminit.h"
+#include "northbridge/amd/lx/pll_reset.c"
+#include "northbridge/amd/lx/raminit.c"
+#include "sdram/generic_sdram.c"
+#include "cpu/amd/model_lx/cpureginit.c"
+#include "cpu/amd/model_lx/syspreinit.c"
+
+static void msr_init(void)
+{
+	msr_t msr;
+	/* Setup access to the cache for under 1MB. */
+	msr.hi = 0x24fffc02;
+	msr.lo =  0x1000A000; /* 0-A0000 write back */
+	wrmsr(CPU_RCONF_DEFAULT, msr);
+
+	msr.hi = 0x0;	/* write back */
+	msr.lo =  0x0;
+	wrmsr(CPU_RCONF_A0_BF, msr);
+	wrmsr(CPU_RCONF_C0_DF, msr);
+	wrmsr(CPU_RCONF_E0_FF, msr);
+
+	/* Setup access to the cache for under 640K. Note MC not setup yet. */
+	msr.hi = 0x20000000;
+	msr.lo = 0xfff80;
+	wrmsr(MSR_GLIU0 + 0x20, msr);
+
+	msr.hi = 0x20000000;
+	msr.lo = 0x80fffe0;
+	wrmsr(MSR_GLIU0 + 0x21, msr);
+
+	msr.hi = 0x20000000;
+	msr.lo =  0xfff80;
+	wrmsr(MSR_GLIU1 + 0x20, msr);
+
+	msr.hi = 0x20000000;
+	msr.lo =  0x80fffe0;
+	wrmsr(MSR_GLIU1 + 0x21, msr);
+
+}
+
+static void mb_gpio_init(void)
+{
+	/* Early mainboard specific GPIO setup */
+}
+
+void cache_as_ram_main(void)
+{
+	POST_CODE(0x01);
+
+	static const struct mem_controller memctrl [] = {
+		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+	};
+
+	SystemPreInit();
+	msr_init();
+
+	cs5536_early_setup();
+
+	/* NOTE: must do this AFTER the early_setup!
+	 * it is counting on some early MSR setup
+	 * for cs5536
+	 */
+	/* cs5536_disable_internal_uart	 disable them for now, set them up later...*/
+	cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
+	mb_gpio_init();
+	uart_init();
+	console_init();
+
+	pll_reset(ManualConf);
+
+	cpuRegInit();
+
+	sdram_initialize(1, memctrl);
+
+	/* Check all of memory */
+	/*ram_check(0x00000000, 640*1024);*/
+
+	/* Memory is setup. Return to cache_as_ram.inc and continue to boot */
+	return;
+}
Index: LinuxBIOSv2/src/mainboard/amd/norwich/chip.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/chip.h	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,12 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+
+*/
+
+extern struct chip_operations mainboard_amd_norwich_ops;
+
+struct mainboard_amd_norwich_config {
+	int nothing;
+};
Index: LinuxBIOSv2/src/mainboard/amd/norwich/cmos.layout
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/cmos.layout	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,75 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+440	     1	     e	     0	      dcon_present
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
Index: LinuxBIOSv2/src/mainboard/amd/norwich/debug.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/debug.c	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,65 @@
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0, 0x1f, 0x7);
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		print_debug_pci_dev(dev);
+		print_debug("\r\n");
+	}
+}
+
+static void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\r\n");
+
+	for(i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0, 0x1f, 0x7);
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		dump_pci_device(dev);
+	}
+}
Index: LinuxBIOSv2/src/mainboard/amd/norwich/failover.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/failover.c	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,34 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+
+static unsigned long main(unsigned long bist)
+{
+#if 0
+	/* This is the primary cpu how should I boot? */
+	if (do_normal_boot()) {
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
+	}
+ normal_image:
+	asm volatile ("jmp __normal_image"
+		: /* outputs */
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
+ cpu_reset:
+	asm volatile ("jmp __cpu_reset"
+		: /* outputs */
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+ fallback_image:
+#endif
+	return bist;
+}
Index: LinuxBIOSv2/src/mainboard/amd/norwich/irq_tables.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/irq_tables.c	2007-05-01 21:45:35.000000000 -0600
@@ -0,0 +1,103 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	 02110-1301 USA
+*/
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 5
+#define PIRQC 10
+#define PIRQD 10
+
+/* Map */
+#define M_PIRQA (1 << PIRQA)  /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB)  /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC)  /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD)  /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA	 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB	 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC	 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD	 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE, /* u32 signature */
+	PIRQ_VERSION,	/* u16 version	 */
+	32+16*IRQ_SLOT_COUNT,		/* there can be total 6 devices on the bus */
+	0x00,			/* Where the interrupt router lies (bus) */
+	(0x0F<<3)|0x0,	/* Where the interrupt router lies (dev) */
+	0x00,			/* IRQs devoted exclusively to PCI usage */
+	0x100B,			/* Vendor */
+	0x002B,			/* Device */
+	0,				/* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x00,			/*	u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+		/* bus,		dev|fn,		 {link, bitmap},	 {link, bitmap},	 {link, bitmap},	 {link, bitmap},  slot, rfu */
+		{0x00,(0x01<<3)|0x0, {{L_PIRQA, M_PIRQA},	 {0x00, 0x00},		 {0x00, 0x00},		 {0x00, 0x00}},	   0x0, 0x0},	 /* cpu */
+		{0x00,(0x0F<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	 /* chipset */
+		{0x00,(0x0D<<3)|0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0},	 /* slot1 */
+		{0x00,(0x0E<<3)|0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0},	 /* slot2 */
+		{0x00,(0x0B<<3)|0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0},	 /* slot3 */
+		{0x00,(0x0C<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0},	 /* slot4 */
+	}
+};
+
+
+unsigned long write_pirq_routing_table(unsigned long addr){
+	int i, j, k, num_entries;
+	unsigned char pirq[4];
+	uint16_t chipset_irq_map;
+	uint32_t pciAddr, pirtable_end;
+	struct irq_routing_table *pirq_tbl;
+
+	pirtable_end = copy_pirq_routing_table(addr);
+
+	/* Set up chipset IRQ steering */
+	pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+	chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
+	printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
+	outl(pciAddr & ~3, 0xCF8);
+	outl(chipset_irq_map, 0xCFC);
+
+	pirq_tbl = (struct irq_routing_table *)(addr);
+	num_entries = (pirq_tbl->size - 32)/16;
+
+	/* Set PCI IRQs */
+	for (i=0; i < num_entries; i++){
+		printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
+		for (j = 0; j < 4; j++){
+		printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
+			for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
+			pirq[j] = k;
+			printk_debug("PIRQ: %d\n", k);
+		}
+		pci_assign_irqs(pirq_tbl->slots[i].bus,
+				pirq_tbl->slots[i].devfn >> 3, pirq);	/* bus, device, slots IRQs for {A,B,C,D} */
+	}
+
+	/* put the PIR table in memory and checksum */
+	return pirtable_end;
+}
Index: LinuxBIOSv2/src/mainboard/amd/norwich/mainboard.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/mainboard.c	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,169 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/lxdef.h>
+#include <device/pci_def.h>
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+#include "chip.h"
+
+/* Print the platform configuration - do before PCI init or it will not work right */
+void print_conf(void) {
+#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+	int i;
+	unsigned long iol;
+	msr_t msr;
+
+	int cpu_msr_defs[] =  { CPU_BC_L2_CONF, CPU_IM_CONFIG,
+							CPU_DM_CONFIG0,  CPU_RCONF_DEFAULT,
+							CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
+							CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
+							};
+
+	int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,  MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
+							 GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
+							 GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
+							 GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
+							 GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
+							 GLIU0_GLD_MSR_COH, GL_END
+							};
+
+	int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
+							 MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
+							 GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
+							 GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
+							 GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
+							 GLIU1_GLD_MSR_COH, GL_END
+							};
+
+	int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
+						CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
+							};
+
+	int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
+						 MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
+							};
+
+	int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
+					  GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE,
+						 GL_END
+							};
+
+	int dma_msr[] =	 { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
+							MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
+							MDD_DMA_SHAD9, GL_END
+							};
+
+
+	printk_debug("---------- CPU ------------\n");
+
+	for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(cpu_msr_defs[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- GLIU 0 ------------\n");
+
+	for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(gliu0_msr_defs[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- GLIU 1 ------------\n");
+
+	for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(gliu1_msr_defs[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- RCONF ------------\n");
+
+	for(i = 0; rconf_msr[i] != GL_END; i++) {
+		msr = rdmsr(rconf_msr[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- VARIA ------------\n");
+	msr = rdmsr(0x51300010);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
+
+	msr = rdmsr(0x51400015);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
+
+	printk_debug("---------- DIVIL IRQ ------------\n");
+	msr = rdmsr(MDD_IRQM_YLOW);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
+	msr = rdmsr(MDD_IRQM_YHIGH);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
+	msr = rdmsr(MDD_IRQM_ZLOW);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
+	msr = rdmsr(MDD_IRQM_ZHIGH);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
+
+
+	printk_debug("---------- PCI ------------\n");
+
+	for(i = 0; pci_msr[i] != GL_END; i++) {
+		msr = rdmsr(pci_msr[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- LPC/UART DMA ------------\n");
+
+	for(i = 0; dma_msr[i] != GL_END; i++) {
+		msr = rdmsr(dma_msr[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- CS5536 ------------\n");
+
+	for(i = 0; cs5536_msr[i] != GL_END; i++) {
+		msr = rdmsr(cs5536_msr[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
+	}
+
+	iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
+	iol = inl(GPIOL_EVENTS_ENABLE);
+	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
+	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
+	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
+	iol = inl(GPIO_MAPPER_X);
+	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol);
+#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+}
+
+static void init(struct device *dev) {
+	printk_debug("Norwich ENTER %s\n", __FUNCTION__);
+	printk_debug("Norwich EXIT %s\n", __FUNCTION__);
+}
+
+static void enable_dev(struct device *dev)
+{
+        dev->ops->init = init;
+}
+
+struct chip_operations mainboard_amd_norwich_ops = {
+	CHIP_NAME("Norwich mainboard ")
+        .enable_dev = enable_dev,
+
+};
Index: LinuxBIOSv2/src/mainboard/amd/norwich/reset.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/mainboard/amd/norwich/reset.c	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,43 @@
+#if 0
+//#include "arch/romcc_io.h"
+#include <arch/io.h>
+
+typedef unsigned device_t;
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFF) << 16) | \
+	(((DEV) & 0x1f) << 11) | \
+	(((FN)  & 0x7) << 8))
+
+static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+{
+        unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+	unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+	unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
+}
+#endif
Index: LinuxBIOSv2/targets/amd/norwich/Config.lb
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/targets/amd/norwich/Config.lb	2007-05-01 01:32:02.000000000 -0600
@@ -0,0 +1,29 @@
+# Config file for the AMD Geode LX/5536 Norwich Platform
+
+target norwich
+mainboard amd/norwich
+
+#HACK to get the right tsc support
+option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+# leave 36k for vsa
+option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
+option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
+
+option ROM_SIZE=512*1024-36*1024
+#option ROM_SIZE=256*1024-36*1024
+option FALLBACK_SIZE=ROM_SIZE
+
+option DEFAULT_CONSOLE_LOGLEVEL = 11
+option MAXIMUM_CONSOLE_LOGLEVEL = 11
+#option DEFAULT_CONSOLE_LOGLEVEL = 4
+#option MAXIMUM_CONSOLE_LOGLEVEL = 4
+
+romimage "fallback"
+	option USE_FALLBACK_IMAGE=1
+	option ROM_IMAGE_SIZE=64*1024
+	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+	payload ../payload.elf
+end
+
+buildrom ./norwich.rom ROM_SIZE  "fallback"

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Peter Stuge]

On Tue, May 01, 2007 at 04:48:29PM -0600, Marc Jones wrote:
> This patch adds support for the AMD Norwich development platform
> based on the Geode LX processor.  The Norwich is the canonical 
> Geode reference, and will server as a good basis for other
> Geode based platforms.
>
> Signed-off-by: Marc Jones

I say

Acked-by: Peter Stuge

but would appreciate if someone else also had a look. I won't commit.

//Peter

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Uwe Hermann]

On Tue, May 01, 2007 at 04:48:29PM -0600, Marc Jones wrote:
> This patch adds support for the AMD Norwich development platform
> based on the Geode LX processor.  The Norwich is the canonical 
> Geode reference, and will server as a good basis for other
> Geode based platforms.

So is this a physically existing product or merely a development
board/prototype? I'm asking because I'd like to know into which
category this should go later in the wiki:

http://linuxbios.org/Supported_Motherboards
> Index: LinuxBIOSv2/src/mainboard/amd/norwich/auto.c
>
> --- /dev/null	1970-01-01 00:00:00.000000000 +0000
> +++ LinuxBIOSv2/src/mainboard/amd/norwich/auto.c	2007-05-01 01:32:02.000000000 -0600

[...]
> +#define POST_CODE(x) outb(x, 0x80)

Why this? We have a post_code() function in src/console/console.c.
> +static void mb_gpio_init(void)
> +{
> /* Early mainboard specific GPIO setup */
>
> +}

Required, now or later? Otherwise please drop it.
> SystemPreInit();

[...]
> pll_reset(ManualConf);
> cpuRegInit();

Please use lowercase names (and underscores) only for function names,
variables etc. I think we have exceptions from this rule in the current
code, but in general we try to follow the Linux kernel coding style
and conventions:

http://lxr.linux.no/source/Documentation/CodingStyle
> +struct chip_operations mainboard_amd_norwich_ops = {
> CHIP_NAME("Norwich mainboard ")

Just some cosmetics: "AMD Norwich Mainboard"

Uwe.

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[ron minnich]

On 5/1/07, Uwe Hermann  wrote:
> On Tue, May 01, 2007 at 04:48:29PM -0600, Marc Jones wrote:
> > This patch adds support for the AMD Norwich development platform
> > based on the Geode LX processor.  The Norwich is the canonical
> > Geode reference, and will server as a good basis for other
> > Geode based platforms.
>
> So is this a physically existing product or merely a development
> board/prototype? I'm asking because I'd like to know into which
> category this should go later in the wiki:
>
> http://linuxbios.org/Supported_Motherboards

I'd say put it in as supported.
> > +#define POST_CODE(x) outb(x, 0x80)
>
> Why this? We have a post_code() function in src/console/console.c.

Marc, is it possible to use the standard one? (There may be a reason
for the macro, if so, leave it in)
> > SystemPreInit();
>
> [...]
> > pll_reset(ManualConf);
> > cpuRegInit();

Those names may be the fault of Ollie or me, not sure; Marc, change if you wish.

So, I'm with Peter, I'd go for the
Acked-by: Ronald G. Minnich 
and, Marc, consider either a new patch with Uwe's recommendations or
fixup later. But I don't want to delay getting this in; there are some
customers waiting for it, literally daily.

thanks

ron

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Uwe Hermann]

On Wed, May 02, 2007 at 09:53:45AM -0700, ron minnich wrote:
> > > SystemPreInit();
> >
> > [...]
> > > pll_reset(ManualConf);
> > > cpuRegInit();
>
> Those names may be the fault of Ollie or me, not sure; Marc, change if you 
> wish.
>
> So, I'm with Peter, I'd go for the
> Acked-by: Ronald G. Minnich 
> and, Marc, consider either a new patch with Uwe's recommendations or
> fixup later. But I don't want to delay getting this in; there are some
> customers waiting for it, literally daily.

I agree, let's commit ASAP and fix the smaller issues later in extra
patches.

However, the following things should be fixed before we commit, IMHO:

- All license issues.

- The commit should not break other targets, apart from OLPC maybe.
   At the moment a few more targets will be broken (see my other mail).

Also, I think we should commit all four patches in one go, otherwise I'm
almost certain that the build will be broken...

Uwe.

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[ron minnich]

No, those other boards don't matter. Marc is not responsible for them.

So, I give you two options:

marc, if you want, fix the other boards.

ELSE,

marc, commit, and I will submit a patch to fix the other boards, since
I own most of them ...

I am debating removing OLPC from tree; comments?

ron

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Peter Stuge]

On Wed, May 02, 2007 at 10:50:23AM -0700, ron minnich wrote:
> I am debating removing OLPC from tree; comments?

A bit sad to see it go, but since it will never be used and thus not
maintained there's not much point in keeping it around..

//Peter

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Uwe Hermann]

On Wed, May 02, 2007 at 10:50:23AM -0700, ron minnich wrote:
> No, those other boards don't matter.

Huh? Of course they matter.
> Marc is not responsible for them.

Sure, but still the boards should not be broken by any patches, right?
> So, I give you two options:
>
> marc, if you want, fix the other boards.
>
> ELSE,
>
> marc, commit, and I will submit a patch to fix the other boards, since
> I own most of them ...

FWIW, I don't think the fixes are very hard. I'll see if I can provide
a patch.
> I am debating removing OLPC from tree; comments?

Don't do it. Thanks. Removing working code is not a good option, and
there may still be people with rev_a/btest boards out there.
Also, the code is very useful as a reference for other boards etc.

Please also don't forget that there will be _millions_ of OLPC machines
out there eventually. Whether or not they are _shipped_ with LinuxBIOS
doesn't matter. The OLPC is designed with hackability in mind (at least
that's what I read and heard in many presentations) and there _will_ be
people who'll want to replace OFW with LinuxBIOS.

The code should definately not be removed.

Uwe.

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Marc Jones]

Uwe Hermann wrote:
> On Wed, May 02, 2007 at 10:50:23AM -0700, ron minnich wrote:
> > No, those other boards don't matter.
>
> Huh? Of course they matter.
> > Marc is not responsible for them.
>
> Sure, but still the boards should not be broken by any patches, right?
> > So, I give you two options:
> >
> > marc, if you want, fix the other boards.
> >
> > ELSE,
> >
> > marc, commit, and I will submit a patch to fix the other boards, since
> > I own most of them ...
>
> FWIW, I don't think the fixes are very hard. I'll see if I can provide
> a patch.
> > I am debating removing OLPC from tree; comments?
>
> Don't do it. Thanks. Removing working code is not a good option, and
> there may still be people with rev_a/btest boards out there.
> Also, the code is very useful as a reference for other boards etc.
>
> Please also don't forget that there will be _millions_ of OLPC machines
> out there eventually. Whether or not they are _shipped_ with LinuxBIOS
> doesn't matter. The OLPC is designed with hackability in mind (at least
> that's what I read and heard in many presentations) and there _will_ be
> people who'll want to replace OFW with LinuxBIOS.
>
> The code should definately not be removed.
>
> Uwe.

I am trying to bring olpc and rumba up to the geodelx patch level and I 
am hitting a build problem that I can't seem to figure out. I get the 
following build error.

gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o  mainboard.o 
uart8250_console.o cs5536.o model_gx2_init.o linuxbios.a 
/usr/lib/gcc/i486-linux-gnu/4.1.2/libgcc.a
gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T 
/home/marcj/LinuxBIOSv2/src/config/linuxbios_ram.ld linuxbios_ram.o
linuxbios_ram.o: In function `number':
vtxprintf.c:(.text+0x2f0a): undefined reference to `__stack_chk_fail'
linuxbios_ram.o: In function `report_resource_stored':
(.text+0x42ba): undefined reference to `__stack_chk_fail'
linuxbios_ram.o: In function `cpu_initialize':
(.text+0x8b4d): undefined reference to `__stack_chk_fail'
collect2: ld returned 1 exit status
make[1]: *** [linuxbios_ram] Error 1
make[1]: Leaving directory 
`/home/marcj/LinuxBIOSv2/targets/olpc/rev_a/rev_a/fallback'
make: *** [fallback/linuxbios.rom] Error 1

I get this on both platforms. Any idea what the problem might be?
Marc

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Corey Osgood]

Marc Jones wrote:
> I am trying to bring olpc and rumba up to the geodelx patch level and I 
> am hitting a build problem that I can't seem to figure out. I get the 
> following build error.
>
> gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o  mainboard.o 
> uart8250_console.o cs5536.o model_gx2_init.o linuxbios.a 
> /usr/lib/gcc/i486-linux-gnu/4.1.2/libgcc.a
> gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T 
> /home/marcj/LinuxBIOSv2/src/config/linuxbios_ram.ld linuxbios_ram.o
> linuxbios_ram.o: In function `number':
> vtxprintf.c:(.text+0x2f0a): undefined reference to `__stack_chk_fail'
> linuxbios_ram.o: In function `report_resource_stored':
> (.text+0x42ba): undefined reference to `__stack_chk_fail'
> linuxbios_ram.o: In function `cpu_initialize':
> (.text+0x8b4d): undefined reference to `__stack_chk_fail'
> collect2: ld returned 1 exit status
> make[1]: *** [linuxbios_ram] Error 1
> make[1]: Leaving directory 
> `/home/marcj/LinuxBIOSv2/targets/olpc/rev_a/rev_a/fallback'
> make: *** [fallback/linuxbios.rom] Error 1
>
> I get this on both platforms. Any idea what the problem might be?
> Marc

Weird, can you build the norwich target? Try passing
-fno-stack-protector to gcc.

-Corey

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Marc Jones]

Corey,
Thanks! that was the problem. Jordan had worked around this in buildrom 
but I was building these other mainboards by hand.
Thanks,
Marc

Corey Osgood wrote:
> Marc Jones wrote:
> > I am trying to bring olpc and rumba up to the geodelx patch level and I 
> > am hitting a build problem that I can't seem to figure out. I get the 
> > following build error.
> >
> > gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o  mainboard.o 
> > uart8250_console.o cs5536.o model_gx2_init.o linuxbios.a 
> > /usr/lib/gcc/i486-linux-gnu/4.1.2/libgcc.a
> > gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T 
> > /home/marcj/LinuxBIOSv2/src/config/linuxbios_ram.ld linuxbios_ram.o
> > linuxbios_ram.o: In function `number':
> > vtxprintf.c:(.text+0x2f0a): undefined reference to `__stack_chk_fail'
> > linuxbios_ram.o: In function `report_resource_stored':
> > (.text+0x42ba): undefined reference to `__stack_chk_fail'
> > linuxbios_ram.o: In function `cpu_initialize':
> > (.text+0x8b4d): undefined reference to `__stack_chk_fail'
> > collect2: ld returned 1 exit status
> > make[1]: *** [linuxbios_ram] Error 1
> > make[1]: Leaving directory 
> > `/home/marcj/LinuxBIOSv2/targets/olpc/rev_a/rev_a/fallback'
> > make: *** [fallback/linuxbios.rom] Error 1
> >
> > I get this on both platforms. Any idea what the problem might be?
> > Marc
>
> Weird, can you build the norwich target? Try passing
> -fno-stack-protector to gcc.
>
> -Corey

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[ron minnich]

On 5/2/07, Marc Jones  wrote:
> I am trying to bring olpc and rumba up to the geodelx patch level and I
> am hitting a build problem that I can't seem to figure out. I get the
> following build error.
>
> gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o  mainboard.o
> uart8250_console.o cs5536.o model_gx2_init.o linuxbios.a
> /usr/lib/gcc/i486-linux-gnu/4.1.2/libgcc.a
> gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T
> /home/marcj/LinuxBIOSv2/src/config/linuxbios_ram.ld linuxbios_ram.o
> linuxbios_ram.o: In function `number':
> vtxprintf.c:(.text+0x2f0a): undefined reference to `__stack_chk_fail'
> linuxbios_ram.o: In function `report_resource_stored':
> (.text+0x42ba): undefined reference to `__stack_chk_fail'
> linuxbios_ram.o: In function `cpu_initialize':
> (.text+0x8b4d): undefined reference to `__stack_chk_fail'
> collect2: ld returned 1 exit status
> make[1]: *** [linuxbios_ram] Error 1
> make[1]: Leaving directory
> `/home/marcj/LinuxBIOSv2/targets/olpc/rev_a/rev_a/fallback'
> make: *** [fallback/linuxbios.rom] Error 1
>
> I get this on both platforms. Any idea what the problem might be?

yes, it is companies and organizations that ship distros and turn on
switches that require things like stack checking, and hence break
linuxbios builds on certain distros. They don't seem to realize that
all the world is NOT an application ...

It's nothing you (or we) are doing; it is churn in the gcc universe,
and the distro guys just don't think these things through. It's
frustrating.

Try the  -fno-stack-protector Corey mentioned.

thanks

ron

[LinuxBIOS] Geode LX: Norwich mainboard

[Jordan Crouse]

On 02/05/07 21:12 -0700, ron minnich wrote:
> yes, it is companies and organizations that ship distros and turn on
> switches that require things like stack checking, and hence break
> linuxbios builds on certain distros. They don't seem to realize that
> all the world is NOT an application ...
>
> It's nothing you (or we) are doing; it is churn in the gcc universe,
> and the distro guys just don't think these things through. It's
> frustrating.
>
> Try the  -fno-stack-protector Corey mentioned.

Please note that the new buildROM code understands how to handle
-fno-stackp-protector (it automatically includes it if it is needed,
thanks to code stolen^H^H^H^H borrowed from the kernel Make scripts),
so thats another great reason to use the buildROM scripts, since it hides
distro churn from you.

Jordan

[LinuxBIOS] Geode LX: Norwich mainboard

[Jordan Crouse]

On 02/05/07 20:50 +0200, Uwe Hermann wrote:
> Don't do it. Thanks. Removing working code is not a good option, and
> there may still be people with rev_a/btest boards out there.
> Also, the code is very useful as a reference for other boards etc.

There's no indication that code is actually working - most of the 
more serious LinuxBIOS changes for OLPC went into the GIT tree on
dev.laptop.org, and never got merged back to the SVN.
> Please also don't forget that there will be _millions_ of OLPC machines
> out there eventually. Whether or not they are _shipped_ with LinuxBIOS
> doesn't matter. The OLPC is designed with hackability in mind (at least
> that's what I read and heard in many presentations) and there _will_ be
> people who'll want to replace OFW with LinuxBIOS.

If there are people who are interested in doing this - then I recommend
a brand new implementation, based on the new LX code for B3 and newer.
Dump any of the old hacky code that exists, and start over from scratch.
Other then the DCON support, it should be a pretty short trip to make
a working version.

Jordan

[LinuxBIOS] Geode LX: Norwich mainboard

[ron minnich]

let me say it differently. I think if we want to target OLPC, we ought
to do it from V3, not V2. I'm still in favor of dropping the current
code and forcing a 'rework' of the code.

Get people into working with V3. It is so much nicer ...

ron

[LinuxBIOS] Geode LX: Norwich mainboard

[Jordan Crouse]

On 03/05/07 08:52 -0700, ron minnich wrote:
> let me say it differently. I think if we want to target OLPC, we ought
> to do it from V3, not V2. I'm still in favor of dropping the current
> code and forcing a 'rework' of the code.

To me, the current OLPC code is the worst possible example of a Geode
port we have.  I feel comfortable saying that because a bunch of that
hack job is mine.

I have no problem at all with somebody porting V3 to work on the OLPC -
I hope they do it for every Geode platform they can get their hands on.
But perpetrating iffy code that will never be used in production for a board
that will never *be* in production to me is silly.  Lets stop giving people
the wrong impression and lets stop leaving a poor example of platform
support around.

Very few LinuxBIOS developers have platforms, and those that do are too busy
trying to get the production image ready to go to worry about any side
hobbies.  I'm confident that by the time enough people have the platform
to make a LinuxBIOS port useful, then V3 will be solid, and we'll have
dozens of good Geode examples under our belt to choose from.

Jordan

[LinuxBIOS] Geode LX: Norwich mainboard

[Richard Smith]

Jordan Crouse wrote:
> I have no problem at all with somebody porting V3 to work on the OLPC -
> I hope they do it for every Geode platform they can get their hands on.
> But perpetrating iffy code that will never be used in production for a board
> that will never *be* in production to me is silly.  Lets stop giving people
> the wrong impression and lets stop leaving a poor example of platform
> support around.

If we remove code from the LinuxBIOS tree bases on this criteria then we
end up dropping half the tree.  This is not something unique to the OLPC 
and GX.

Case in point. The 440bx stuff.  Its long since dead. V1 even. But guess 
what?  Its currently the only reference we have for a working 440bx 
Linuxbios setup and currently getting heavily reviewed to make the V2 work.

Don't make working with the tree any harder than it already is. If we 
drop code then for someone to go look at the olpc stuff they will have 
to figure out what revision of the tree had the olpc stuff and check 
that out.

Lets concentrate on working on the code rather than just increasing our 
admin load.

[LinuxBIOS] Geode LX: Norwich mainboard

[Peter Stuge]

On Thu, May 03, 2007 at 12:20:14PM -0400, Richard Smith wrote:
> then we end up dropping half the tree.  This is not something
> unique to the OLPC and GX.

Good point.
> If we drop code then for someone to go look at the olpc stuff they
> will have to figure out what revision of the tree had the olpc
> stuff and check that out.

Well, we could just make a wiki page or even better an auto-generated
page that shows when something was dropped.

I don't feel strongly either way, I am a collector so if it were up
to me I'd keep it around. You never know.. ;)

//Peter

[LinuxBIOS] Geode LX: Norwich mainboard

[Stefan Reinauer]

* Jordan Crouse  [070503 18:01]:
> I have no problem at all with somebody porting V3 to work on the OLPC -
> I hope they do it for every Geode platform they can get their hands on.
> But perpetrating iffy code that will never be used in production for a board
> that will never *be* in production to me is silly.  Lets stop giving people
> the wrong impression and lets stop leaving a poor example of platform
> support around.

I fully agree.

Stefan

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Marc Jones]

ron minnich wrote:
> No, those other boards don't matter. Marc is not responsible for them.
>
> So, I give you two options:
>
> marc, if you want, fix the other boards.
>
> ELSE,
>
> marc, commit, and I will submit a patch to fix the other boards, since
> I own most of them ...
>
> I am debating removing OLPC from tree; comments?
>
> ron

I knew about OLPC but not the other mainboards. I will look into the 
required changes and see what I can do.

Marc

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Stefan Reinauer]

* Marc Jones  [070502 21:01]:
> I knew about OLPC but not the other mainboards. I will look into the 
> required changes and see what I can do.

As a small help for developers we have abuild.

$ cd util/abuild
$ ./abuild
to build all targets or
$ ./abuild -t olpc/rev_a 
to build the target olpc/rev_a only.

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Carl-Daniel Hailfinger]

On 02.05.2007 19:50, ron minnich wrote:
> I am debating removing OLPC from tree; comments?

Please don't. I still hope we can offer LinuxBIOS as an alternative
for shipped machines. C ist so much easier to learn and write than
Forth. And even if you planned to remove OLPC now to re-add it later,
the removal would make diffing between revisions (old OLPC and new
OLPC) more difficult.

Regards,
Carl-Daniel

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Richard Smith]

Carl-Daniel Hailfinger wrote:
> On 02.05.2007 19:50, ron minnich wrote:
> > I am debating removing OLPC from tree; comments?
>
> Please don't. I still hope we can offer LinuxBIOS as an alternative
> for shipped machines.

Yes. Please don't.  The OLPC will have a long life and just because we 
use OFW only as the firmware doesn't mean full LinuxBIOS ports won't 
happen.
> C ist so much easier to learn and write than
> Forth.

I disagree with you quite violently. I learned forth in about 2 days. 
Its a trivial language. Openfirmware is a bit more complex due to the 
massive library it has but still far below the learning of _anything_ 
associated with Linuxbios.  At least OFW is documented. (TROLL)  But 
lets keep language religion to a minimum.

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Ward Vandewege]

On Thu, May 03, 2007 at 11:17:14AM -0400, Richard Smith wrote:
> > C is so much easier to learn and write than
> > Forth.
>
> I disagree with you quite violently. I learned forth in about 2 days.

Yeah, I was going to say the same thing :) Not that I've looked at forth in
the last, hmmm, 15 years or so - but I remember playing with it as a teenager
and finding it extremely intuitive; way, way easier than C.

Thanks,
Ward.

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Peter Stuge]

On Wed, May 02, 2007 at 07:30:20PM +0200, Uwe Hermann wrote:
> However, the following things should be fixed before we commit,
> IMHO:
>
> All license issues.
>
> The commit should not break other targets

Agreed. I would also really like if the whitespace breakage was
eliminated first, but I may be puritan.
> Also, I think we should commit all four patches in one go,
> otherwise I'm almost certain that the build will be broken...

As long as the mainboard goes in last that shouldn't be a problem.

//Peter

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Marc Jones]

Peter Stuge wrote:
> On Wed, May 02, 2007 at 07:30:20PM +0200, Uwe Hermann wrote:
> > However, the following things should be fixed before we commit,
> > IMHO:
> >
> > All license issues.
> >
> > The commit should not break other targets
>
> Agreed. I would also really like if the whitespace breakage was
> eliminated first, but I may be puritan.
> > Also, I think we should commit all four patches in one go,
> > otherwise I'm almost certain that the build will be broken...
>
> As long as the mainboard goes in last that shouldn't be a problem.
>
> //Peter

I agree and will try to fix all of these relatively minor (but 
important) issues before we commit.
Marc

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Marc Jones]

ron minnich wrote:
> On 5/1/07, Uwe Hermann  wrote:
> > On Tue, May 01, 2007 at 04:48:29PM -0600, Marc Jones wrote:
> > > This patch adds support for the AMD Norwich development platform
> > > based on the Geode LX processor.  The Norwich is the canonical
> > > Geode reference, and will server as a good basis for other
> > > Geode based platforms.
> >
> > So is this a physically existing product or merely a development
> > board/prototype? I'm asking because I'd like to know into which
> > category this should go later in the wiki:
> >
> > http://linuxbios.org/Supported_Motherboards
>
> I'd say put it in as supported.
> > > +#define POST_CODE(x) outb(x, 0x80)
> >
> > Why this? We have a post_code() function in src/console/console.c.
>
> Marc, is it possible to use the standard one? (There may be a reason
> for the macro, if so, leave it in)

This was for pre-stack code when we were using romcc. Now that it is CAR 
code I think it could be changed to use console.c.
> > > SystemPreInit();
> >
> > [...]
> > > pll_reset(ManualConf);
> > > cpuRegInit();
>
> Those names may be the fault of Ollie or me, not sure; Marc, change if 
> you wish.

I think this would be best as a follow-on patch.
> So, I'm with Peter, I'd go for the
> Acked-by: Ronald G. Minnich 
> and, Marc, consider either a new patch with Uwe's recommendations or
> fixup later. But I don't want to delay getting this in; there are some
> customers waiting for it, literally daily.
>
> thanks
>
> ron

Marc

[LinuxBIOS] [patch 2/4] Geode LX: Norwich mainboard

[Uwe Hermann]

On Wed, May 02, 2007 at 01:49:25PM -0600, Marc Jones wrote:
> > Those names may be the fault of Ollie or me, not sure; Marc, change if 
> > you wish.
>
> I think this would be best as a follow-on patch.

Agreed. This is not critical right now.

Uwe.

[LinuxBIOS] [patch 3/4] Geode LX: Northbridge

[Marc Jones]

This patch adds support for the northbridge integrated into the AMD
Geode LX platform, including memory and graphics.

Signed-off-by: Marc Jones 
Index: LinuxBIOSv2/src/northbridge/amd/lx/Config.lb
===================================================================
--- LinuxBIOSv2.orig/src/northbridge/amd/lx/Config.lb	2007-05-01 14:37:02.000000000 -0600
+++ LinuxBIOSv2/src/northbridge/amd/lx/Config.lb	2007-05-01 14:38:33.000000000 -0600
@@ -1,5 +1,4 @@
 config chip.h
 object northbridge.o
 object northbridgeinit.o
-object chipsetinit.o
 object grphinit.o
Index: LinuxBIOSv2/src/northbridge/amd/lx/chip.h
===================================================================
--- LinuxBIOSv2.orig/src/northbridge/amd/lx/chip.h	2007-05-01 14:37:02.000000000 -0600
+++ LinuxBIOSv2/src/northbridge/amd/lx/chip.h	2007-05-01 14:38:33.000000000 -0600
@@ -1,7 +1,12 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
+
 struct northbridge_amd_lx_config
 {
- 	uint16_t irqmap;
-	int setupflash;
+	int video_size_MB;
 };

extern struct chip_operations northbridge_amd_lx_ops;
Index: LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c
===================================================================
--- LinuxBIOSv2.orig/src/northbridge/amd/lx/grphinit.c	2007-05-01 14:37:02.000000000 -0600
+++ LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c	2007-05-01 14:38:33.000000000 -0600
@@ -1,31 +1,14 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
+
 #include <arch/io.h>
 #include <stdint.h>
 #include <cpu/amd/vr.h>
 #include <console/console.h>

-/*
- * Write to a Virtual Register
- * AX = Class/Index
- * CX = data to write
- */
-void vrWrite(uint16_t wClassIndex, uint16_t wData)
-{
-	outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
-	outw(wData, VRC_DATA);
-}
-
- /*
- * Read from a Virtual Register
- * AX = Class/Index
- * Returns a 16-bit word of data
- */
-uint16_t vrRead(uint16_t wClassIndex)
-{
-	uint16_t wData;
-	outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
-	wData = inw(VRC_DATA);
-	return wData;
-}

/*
  * This function mirrors the Graphics_Init routine in GeodeROM.
@@ -40,7 +23,7 @@
    /* Call SoftVG with the main configuration parameters. */
    /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
    
-	wClassIndex = (VRC_VG <<  8) + VG_MEM_SIZE;
+	wClassIndex = (VRC_VG <<  8) + VG_CONFIG;
    
    /*
     * Graphics Driver Enabled (13) 			0, NO (lets BIOS controls the GP)
@@ -52,12 +35,12 @@
     * PLL Reference Clock Bypass(0)			0, Default
     */

-	/*	 video RAM has to be given in 2MB chunks
+	/* Video RAM has to be given in 2MB chunks
     *   the value is read @ 7:1 (value in 7:0 looks like /2)
     *   so we can add the real value in megabytes
     */
     
-	wData =  0x0800 | (CONFIG_VIDEO_MB & VG_MEM_MASK);
+	wData =  VG_CFG_DRIVER | VG_CFG_PRIORITY | VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK);
    vrWrite(wClassIndex, wData);
    
    res = vrRead(wClassIndex);
Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c
===================================================================
--- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridge.c	2007-05-01 14:37:02.000000000 -0600
+++ LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c	2007-05-01 14:40:04.000000000 -0600
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <arch/io.h>
 #include <stdint.h>
@@ -7,20 +26,20 @@
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>
-#include "chip.h"
-#include "northbridge.h"
 #include <cpu/cpu.h>
 #include <cpu/amd/lxdef.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/vr.h>
+#include "chip.h"
+#include "northbridge.h"

/* here is programming for the various MSRs.*/
 #define IM_QWAIT 0x100000

#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
-#define DMCF_SERIAL_LOAD_MISSES  (2) /* enabled */
+#define DMCF_SERIAL_LOAD_MISSES	 (2) /* enabled */

/* these are the 8-bit attributes for controlling RCONF registers */
 #define CACHE_DISABLE (1<<0)
@@ -56,9 +75,11 @@

extern void graphics_init(void);
 extern void cpubug(void);
+extern void chipsetinit(void);
+extern void print_conf(void);
+extern uint32_t get_systop(void);

void northbridge_init_early(void);
-void chipsetinit(struct northbridge_amd_lx_config *nb);
 void setup_realmode_idt(void);
 void do_vsmbios(void);

@@ -86,334 +107,65 @@
    /* GLIU0 */
    P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80),
    P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
-	P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0,  0xff03, 0xC0000),
+	P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0,	 0xff03, 0xC0000),
    /* GLIU1 */
    P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),
    P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
-	P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0,  0xff03, 0xC0000),
+	P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0,	 0xff03, 0xC0000),
    {0}
 };

-/* todo: add a resource record. We don't do this here because this may be called when 
+/* todo: add a resource record. We don't do this here because this may be called when
   * very little of the platform is actually working.
   */
-int
-sizeram(void)
+int sizeram(void)
 {
    msr_t msr;
    int sizem = 0;
    unsigned short dimm;

-	msr = rdmsr(0x20000018);
-	printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
+	msr = rdmsr(MC_CF07_DATA);
+	printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);

/* dimm 0 */
    dimm = msr.hi;
-	sizem = (1 << ((dimm >> 12)-1)) * 8;
-
+	/* installed? */
+	if ((dimm & 7) != 7){
+		sizem = 4 << ((dimm >> 12) & 0x0F);
+	}

/* dimm 1*/
    dimm = msr.hi >> 16;
    /* installed? */
-	if ((dimm & 7) != 7)
-		sizem += (1 << ((dimm >> 12)-1)) * 8;
+	if ((dimm & 7) != 7){
+		sizem += 4 << ((dimm >> 12) & 0x0F);
+	}

-	printk_debug("sizeram: sizem 0x%x\n", sizem);
+	printk_debug("sizeram: sizem 0x%xMB\n", sizem);
    return sizem;
 }

-/* note that dev is NOT used -- yet */
-static void irq_init_steering(struct device *dev, uint16_t irq_map) {
-	/* Set up IRQ steering */
-	uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-
-	printk_debug("%s(%08X [%08X], %04X)\n", __FUNCTION__, dev, pciAddr, irq_map);
-
-	/* The IRQ steering values (in hex) are effectively dcba, where:
-	 *    <a> represents the IRQ for INTA, 
-	 *    <b> represents the IRQ for INTB,
-	 *    <c> represents the IRQ for INTC, and
-	 *    <d> represents the IRQ for INTD.
-	 * Thus, a value of irq_map = 0xAA5B translates to:
-	 *    INTA = IRQB (IRQ 11)
-	 *    INTB = IRQ5 (IRQ 5)
-	 *    INTC = IRQA (IRQ 10)
-	 *    INTD = IRQA (IRQ 10)
-	 */
-	outl(pciAddr & ~3, 0xCF8);
-	outl(irq_map,      0xCFC);
-}
-

-/*
- * setup_lx_cache
- *
- * Returns the amount of memory (in KB) available to the system.  This is the 
- * total amount of memory less the amount of memory reserved for SMM use.
- *
- */ 
-static int
-setup_lx_cache(void)
-{
-	msr_t msr;
-	unsigned long long val;
-	int sizekbytes, sizereg;
-
-	sizekbytes = sizeram() * 1024;
-	printk_debug("setup_lx_cache: enable for %d KB\n", sizekbytes);
-	/* build up the rconf word. */
-	/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
-	/* set romrp */
-	val = ((unsigned long long) ROM_PROPERTIES) << 56;
-	/* make rom base useful for 1M roms */
-	/* Flash base address -- sized for 1M for now*/
-	val |= ((unsigned long long) 0xfff00)<<36;
-	/* set the devrp properties */
-	val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
-	/* Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
-	/* yank off memory for the SMM handler */
-	sizekbytes -= SMM_SIZE;
-	sizereg = sizekbytes;
-	sizereg >>= 2;
-	sizereg <<= 8;
-	val |= sizereg;
-	val |= RAM_PROPERTIES;
-	msr.lo = val;
-	msr.hi = (val >> 32);
-	
-	// GX3
-	//msr.hi = 0x04FFFC02;
-	//msr.lo = 0x1077BE00;
-	
-	//sizekbytes = 122616;
-
-	printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	enable_cache();
-	wbinvd();
-	return sizekbytes;
-}
-
-/* we have to do this here. We have not found a nicer way to do it */
-void
-setup_lx(void)
-{
-
-	unsigned long tmp, tmp2;
-	msr_t msr;
-	unsigned long size_kb, membytes;
-
-	size_kb = setup_lx_cache();
-
-#if 0	// andrei: this is done in northbridge.c SMMGL0Init and SystemInit!
-	membytes = size_kb * 1024;
-	/* NOTE! setup_lx_cache returns the SIZE OF RAM - RAMADJUST!
-	  * so it is safe to use. You should NOT at this point call 	
-	  * sizeram() directly. 
-	  */
-
-	/* we need to set 0x10000028 and 0x40000029 */
-	/*
-	 * These two descriptors cover the range from 1 MB (0x100000) to 
-	 * SYSTOP (a.k.a. TOM, or Top of Memory)
-	 */
-
-
-	/* fixme: SMM MSR 0x10000026 and 0x400000023 */
-	/* calculate the OFFSET field */
-	tmp = membytes - SMM_OFFSET;
-	tmp >>= 12;
-	tmp <<= 8;
-	tmp |= 0x20000000;
-	tmp |= (SMM_OFFSET >> 24);
-
-	/* calculate the PBASE and PMASK fields */
-	tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20  == left 8 */
-	tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
-	msr.hi = tmp;
-	msr.lo = tmp2;
-	wrmsr(0x10000026, msr);
-#endif
-}

static void enable_shadow(device_t dev)
 {
 }

-void print_conf(void) {
-	int i;
-	unsigned long iol;
-	msr_t msr;
-	
-	int cpu_msr_defs[] =  { L2_CONFIG_MSR, CPU_IM_CONFIG, 
-							CPU_DM_CONFIG0, CPU_DM_CONFIG1, CPU_DM_PFLOCK, CPU_RCONF_DEFAULT,
-							CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
-							CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
-							};
-
-	int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE3, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
-							 GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
-							 GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
-							 GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
-							 GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
-							 GLIU0_GLD_MSR_COH, GL_END
-							};
-
-	int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
-							 MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
-							 GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
-							 GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
-							 GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
-							 GLIU1_GLD_MSR_COH, GL_END
-							};
-
-	int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
-						CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
-							};
-							
-	int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
-						 MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
-							};
-							
-	int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
-					  GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_EXT_MSR, GLPCI_SPARE,
-						 GL_END
-							};
-
-	int dma_msr[] =  { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
-							MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
-							MDD_DMA_SHAD9, GL_END
-							};
-
-
-	printk_debug("---------- CPU ------------\n");
-
-	for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
-		msr = rdmsr(cpu_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
-	}
-
-	printk_debug("---------- GLIU 0 ------------\n");
-
-	for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
-		msr = rdmsr(gliu0_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
-	}
-
-	printk_debug("---------- GLIU 1 ------------\n");
-
-	for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
-		msr = rdmsr(gliu1_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
-	}
-
-	printk_debug("---------- RCONF ------------\n");
-
-	for(i = 0; rconf_msr[i] != GL_END; i++) {
-		msr = rdmsr(rconf_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
-	}
-
-	printk_debug("---------- VARIA ------------\n");
-	msr = rdmsr(0x51300010);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
-
-	msr = rdmsr(0x51400015);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
-
-	printk_debug("---------- DIVIL IRQ ------------\n");
-	msr = rdmsr(MDD_IRQM_YLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
-	msr = rdmsr(MDD_IRQM_YHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
-	msr = rdmsr(MDD_IRQM_ZLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
-	msr = rdmsr(MDD_IRQM_ZHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
-
-
-	printk_debug("---------- PCI ------------\n");
-
-	for(i = 0; pci_msr[i] != GL_END; i++) {
-		msr = rdmsr(pci_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
-	}
-
-	printk_debug("---------- LPC/UART DMA ------------\n");
-
-	for(i = 0; dma_msr[i] != GL_END; i++) {
-		msr = rdmsr(dma_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
-	}
-
-	printk_debug("---------- CS5536 ------------\n");
-
-	for(i = 0; cs5536_msr[i] != GL_END; i++) {
-		msr = rdmsr(cs5536_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
-	}
-	
-	iol = inl(GPIOL_INPUT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_ENABLE, iol);
-	iol = inl(GPIOL_EVENTS_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_EVENTS_ENABLE, iol);
-	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_INVERT_ENABLE, iol);
-	iol = inl(GPIO_MAPPER_X);
-	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_MAPPER_X, iol);
-	
-}
-
-static void enable_L2_cache(void) {
-	msr_t msr;
-
-	/* Instruction Memory Configuration register
-	 * set EBE bit, required when L2 cache is enabled
-	 */ 
-	msr = rdmsr(CPU_IM_CONFIG);
-	msr.lo |= 0x400;
-	wrmsr(CPU_IM_CONFIG, msr);
-	
-	/* Data Memory Subsystem Configuration register
-	 * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
-	 */
-	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.lo |= 0x4000;
-	wrmsr(CPU_DM_CONFIG0, msr);
-
-	/* invalidate L2 cache */
-	msr.hi = 0x00;
-	msr.lo = 0x10;
-	wrmsr(L2_CONFIG_MSR, msr);
-
-	/* Enable L2 cache */	
-	msr.hi = 0x00;
-	msr.lo = 0x0f;	
-	wrmsr(L2_CONFIG_MSR, msr);
-	
-	printk_debug("L2 cache enabled\n");
-}
-
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
    //msr_t msr;
-	struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;

printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
-	
+
    enable_shadow(dev);
    /*
     * Swiss cheese
     */
    //msr = rdmsr(MSR_GLIU0_SHADOW);
-	
+
    //msr.hi |= 0x3;
    //msr.lo |= 0x30000;
-	
-// not needed (also irq steering is in legacy vsm so it wouldnt work either)
-//	irq_init_steering(dev, nb->irqmap);
+

//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
    //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
@@ -457,18 +209,18 @@
    if (line) {
    	pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
    }
-	
+
    /* set the cache line size, so far 64 bytes is good for everyone */
    pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }

static struct device_operations northbridge_operations = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = northbridge_set_resources,
+	.read_resources	  = pci_dev_read_resources,
+	.set_resources	  = northbridge_set_resources,
    .enable_resources = pci_dev_enable_resources,
-	.init             = northbridge_init,
-	.enable           = 0,
-	.ops_pci          = 0,
+	.init			  = northbridge_init,
+	.enable			  = 0,
+	.ops_pci		  = 0,
 };

static struct pci_driver northbridge_driver __pci_driver = {
@@ -480,32 +232,32 @@

static void pci_domain_read_resources(device_t dev)
 {
-        struct resource *resource;
+		struct resource *resource;
    printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);

-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+		/* Initialize the system wide io space constraints */
+		resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
+		resource->limit = 0xffffUL;
+		resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+		/* Initialize the system wide memory resources constraints */
+		resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
+		resource->limit = 0xffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }

static void ram_resource(device_t dev, unsigned long index,
-        unsigned long basek, unsigned long sizek)
+		unsigned long basek, unsigned long sizek)
 {
-        struct resource *resource;
+		struct resource *resource;

if (!sizek) return;
-	
-        resource = new_resource(dev, index);
-        resource->base  = ((resource_t)basek) << 10;
-        resource->size  = ((resource_t)sizek) << 10;
+
+		resource = new_resource(dev, index);
+		resource->base	= ((resource_t)basek) << 10;
+		resource->size	= ((resource_t)sizek) << 10;
    resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE |
-                IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+				IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }

static void pci_domain_set_resources(device_t dev)
@@ -516,12 +268,12 @@
    printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);

mc_dev = dev->link[0].children;
-	if (mc_dev) 
+	if (mc_dev)
    {
    	/* Report the memory regions */
    	idx = 10;
    	ram_resource(dev, idx++, 0, 640);
-		ram_resource(dev, idx++, 1024, ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024);
+		ram_resource(dev, idx++, 1024, (get_systop()- 0x100000)/1024 ); // Systop - 1 MB -> KB
    }

assign_resources(&dev->link[0]);
@@ -529,25 +281,23 @@

static void pci_domain_enable(device_t dev)
 {
-	struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;

printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);

// do this here for now -- this chip really breaks our device model
-	enable_L2_cache();
    northbridge_init_early();
    cpubug();
-	chipsetinit(nb);
-	setup_lx();
+	chipsetinit();
+
    setup_realmode_idt();

printk_debug("Before VSA:\n");
-	print_conf();
+	// print_conf();

do_vsmbios();	// do the magic stuff here, so prepare your tambourine ;)
-	
+
    printk_debug("After VSA:\n");
-	print_conf();
+	// print_conf();

graphics_init();
    pci_set_method(dev);
@@ -557,23 +307,23 @@
 {
    printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);

-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
+		max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+		return max;
 }

static struct device_operations pci_domain_ops = {
-        .read_resources   = pci_domain_read_resources,
-        .set_resources    = pci_domain_set_resources,
-        .enable_resources = enable_childrens_resources,
-        .scan_bus         = pci_domain_scan_bus,
-        .enable           = pci_domain_enable,
-};  
+		.read_resources	  = pci_domain_read_resources,
+		.set_resources	  = pci_domain_set_resources,
+		.enable_resources = enable_childrens_resources,
+		.scan_bus		  = pci_domain_scan_bus,
+		.enable			  = pci_domain_enable,
+};

static void cpu_bus_init(device_t dev)
 {
    printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);

-        initialize_cpus(&dev->link[0]);
+		initialize_cpus(&dev->link[0]);
 }

static void cpu_bus_noop(device_t dev)
@@ -581,26 +331,26 @@
 }

static struct device_operations cpu_bus_ops = {
-        .read_resources   = cpu_bus_noop,
-        .set_resources    = cpu_bus_noop,
-        .enable_resources = cpu_bus_noop,
-        .init             = cpu_bus_init,
-        .scan_bus         = 0,
+		.read_resources	  = cpu_bus_noop,
+		.set_resources	  = cpu_bus_noop,
+		.enable_resources = cpu_bus_noop,
+		.init			  = cpu_bus_init,
+		.scan_bus		  = 0,
 };

static void enable_dev(struct device *dev)
 {
-	printk_spew(">> Entering northbridge.c: %s with path %d\n", 
+	printk_spew(">> Entering northbridge.c: %s with path %d\n",
    	__FUNCTION__, dev->path.type);

-        /* Set the operations if it is a special bus type */
+		/* Set the operations if it is a special bus type */
    if (dev->path.type == DEVICE_PATH_PCI_DOMAIN)
    	dev->ops = &pci_domain_ops;
    else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER)
-                dev->ops = &cpu_bus_ops;
+				dev->ops = &cpu_bus_ops;
 }

struct chip_operations northbridge_amd_lx_ops = {
    CHIP_NAME("AMD LX Northbridge")
-	.enable_dev = enable_dev, 
+	.enable_dev = enable_dev,
 };
Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c
===================================================================
--- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridgeinit.c	2007-05-01 14:37:02.000000000 -0600
+++ LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c	2007-05-01 14:40:18.000000000 -0600
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <arch/io.h>
 #include <stdint.h>
@@ -13,7 +32,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>

-/* put this here for now, we are not sure where it belongs */

struct gliutable {
    unsigned long desc_name;
@@ -22,27 +40,28 @@
 };

struct gliutable gliu0table[] = {
-	{.desc_name=MSR_GLIU0_BASE1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},		/*  0-7FFFF to MC*/
-	{.desc_name=MSR_GLIU0_BASE2,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},		/*  80000-9ffff to Mc*/
-	{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},	/*  C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
-	{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},		/*  Catch and fix dynamicly.*/
-	{.desc_name=MSR_GLIU0_SMM,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},		/*  Catch and fix dynamicly.*/
+	{.desc_name=MSR_GLIU0_BASE1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=	 0x0FFF80},		/*	0-7FFFF to MC*/
+	{.desc_name=MSR_GLIU0_BASE2,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},		/*	80000-9ffff to Mc*/
+	{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=	 0x03},	/*	C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
+	{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi=	 MSR_MC,.lo=  0x0},		/*	Catch and fix dynamicly.*/
+	{.desc_name=MSR_GLIU0_SMM,	  .desc_type= BMO_SMM,.hi=	MSR_MC,.lo=	 0x0},		/*	Catch and fix dynamicly.*/
    {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
-	{.desc_name=GL_END,           .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+	{.desc_name=GL_END,			  .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };

struct gliutable gliu1table[] = {
-	{.desc_name=MSR_GLIU1_BASE1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},	/*  0-7FFFF to MC*/
-	{.desc_name=MSR_GLIU1_BASE2,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/*  80000-9ffff to Mc*/
-	{.desc_name=MSR_GLIU1_SHADOW,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03}, /*  C0000-Fffff split to MC and PCI (sub decode)*/
-	{.desc_name=MSR_GLIU1_SYSMEM,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},		/*  Cat0xc and fix dynamicly.*/
-	{.desc_name=MSR_GLIU1_SMM,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},			/*  Cat0xc and fix dynamicly.*/
+	{.desc_name=MSR_GLIU1_BASE1,.desc_type=	 BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},	/*	0-7FFFF to MC*/
+	{.desc_name=MSR_GLIU1_BASE2,.desc_type=	 BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/*	80000-9ffff to Mc*/
+	{.desc_name=MSR_GLIU1_SHADOW,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03}, /*	 C0000-Fffff split to MC and PCI (sub decode)*/
+	{.desc_name=MSR_GLIU1_SYSMEM,.desc_type=  R_SYSMEM,.hi=	 MSR_GL0,.lo=  0x0},		/*	Catch and fix dynamicly.*/
+	{.desc_name=MSR_GLIU1_SMM,.desc_type=  BM_SMM,.hi=	MSR_GL0,.lo=  0x0},			/*	Catch and fix dynamicly.*/
    {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
+	{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0},	/*  FooGlue FPU 0xF0*/
    {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };

-struct gliutable *gliutables[]  = {gliu0table, gliu1table, 0};
+struct gliutable *gliutables[]	= {gliu0table, gliu1table, 0};

struct msrinit {
    unsigned long msrnum;
@@ -51,54 +70,36 @@

struct msrinit ClockGatingDefault [] = {
    {GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
-			/*  MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142*/
-	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},
-	{GLIU1_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
-	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},			/*  lotus #77.163*/
+	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
+	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0015}},
    {GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
-	/*{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0155}},*/ //GX3 
-	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
+	{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0555}},
+	{GLIU1_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
+	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0014}},
    {GLPCI_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
-	/*{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},	*/		/* Always on*/ //GX3
-	{0xffffffff, 				{0xffffffff, 0xffffffff}},
-};
-	/*  All On*/
-struct msrinit ClockGatingAllOn[] = {
-	{GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
-	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0FFFFFFFF}},
-	{GLIU1_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
-	{VG_GLD_MSR_PM,		{.hi=0x00, .lo=0x00}},
-	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x000000001}},
-	/*{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0FFFFFFFF}}, */ //GX3
-	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
-	{GLPCI_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
-	/*{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}}, */ //GX3
- 	{0xffffffff, 				{0xffffffff, 0xffffffff}},
+	{VIP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
+	{AES_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
+	{CPU_BC_PMODE_MSR,	{.hi=0x00,.lo=0x70303}},
+	{0xffffffff,		{0xffffffff, 0xffffffff}},
 };

-	/*  Performance*/
-struct msrinit ClockGatingPerformance[] = {
-	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},		/*  lotus #77.163*/
-	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
-	/*{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0155}},	*/ //GX3
-	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
-	{0xffffffff, 				{0xffffffff, 0xffffffff}},
-};
 /* */
-/*  SET GeodeLink PRIORITY*/
+/*	SET GeodeLink PRIORITY*/
 /* */
 struct msrinit GeodeLinkPriorityTable [] = {
-	{CPU_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0220}},	/*  CPU Priority.*/
-	/*{DF_GLD_MSR_MASTER_CONF,	{.hi=0x00,.lo=0x0000}},*/ 	/*  DF Priority.*/		//GX3
-	{VG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0720}},	/*  VG Primary and Secondary Priority.*/
-	{GP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0010}},	/*  Graphics Priority.*/
-	{GLPCI_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0027}},	/*  GLPCI Priority + PID*/
-	{GLCP_GLD_MSR_CONF,		{.hi=0x00,.lo=0x0001}},	/*  GLCP Priority + PID*/
-	{VIP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},	/*  VIP PID*/
-	{AES_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0013}},	/*  AES PID*/
-	{0x0FFFFFFFF, 			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/*  END*/
+	{CPU_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0220}},
+	{DF_GLD_MSR_MASTER_CONF,	{.hi=0x00,.lo=0x0000}},
+	{VG_GLD_MSR_CONFIG,			{.hi=0x00,.lo=0x0720}},
+	{GP_GLD_MSR_CONFIG,			{.hi=0x00,.lo=0x0010}},
+	{GLPCI_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0017}},
+	{GLCP_GLD_MSR_CONF,			{.hi=0x00,.lo=0x0001}},
+	{VIP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},
+	{AES_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0013}},
+	{0x0FFFFFFFF,			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/*	END*/
 };

+extern int sizeram(void);
+
 static void
 writeglmsr(struct gliutable *gl){
    msr_t msr;
@@ -106,10 +107,7 @@
    msr.lo = gl->lo;
    msr.hi = gl->hi;
    wrmsr(gl->desc_name, msr);	// MSR - see table above
-	// printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); //GX3
-	/* they do this, so we do this */
-	msr = rdmsr(gl->desc_name);
-	// printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3
+	printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3
 }

static void
@@ -120,72 +118,66 @@
    msr = rdmsr(gl->desc_name);

if (msr.lo == 0) {
-		writeglmsr(gl); 
+		writeglmsr(gl);
    }
 }

-/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. 
-  * CLEAN ME UP
-   */
-/* yes, this duplicates later code, but it seems that is how they want it done. 
-  */
 extern int sizeram(void);
-static void
-SysmemInit(struct gliutable *gl)
+static void SysmemInit(struct gliutable *gl)
 {
    msr_t msr;
    int sizembytes, sizebytes;

-	/* 
-	 * Figure out how much RAM is in the machine and alocate all to the 
+	/*
+	 * Figure out how much RAM is in the machine and alocate all to the
     * system. We will adjust for SMM now and Frame Buffer later.
     */
    sizembytes = sizeram();
-	printk_debug("%s: enable for %dm bytes\n", __FUNCTION__, sizembytes);
+	printk_debug("%s: enable for %dMBytes\n", __FUNCTION__, sizembytes);
    sizebytes = sizembytes << 20;

-	sizebytes -= ((SMM_SIZE)<<10);
+	sizebytes -= ((SMM_SIZE * 1024) + 1);
    printk_debug("usable RAM: %d bytes\n", sizebytes);

+	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
+	 The top 8 bits go into 0-7 of msr.hi. */
+	sizebytes--;
    msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
-	/* set up sizebytes to fit into msr.lo */
-	sizebytes <<= 8; /* what? well, we want bits 23:12 in bits 31:20. */
+	sizebytes <<= 8;		/* move bits 23:12 in bits 31:20. */
    sizebytes &= 0xfff00000;
-	sizebytes |= 0x100;
+	sizebytes |= 0x100;		/* start at 1MB */
    msr.lo = sizebytes;

wrmsr(gl->desc_name, msr);	// MSR - see table above
-	msr = rdmsr(gl->desc_name);
-	/* printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, 
-				gl->desc_name, msr.hi, msr.lo); */ // GX3	
+	printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__,
+				gl->desc_name, msr.hi, msr.lo);
 }

-static void
-SMMGL0Init(struct gliutable *gl) {
+static void SMMGL0Init(struct gliutable *gl) {
    msr_t msr;
    int sizebytes = sizeram()<<20;
    long offset;

-	sizebytes -= ((SMM_SIZE)<<10);
+	sizebytes -= (SMM_SIZE*1024);

printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);

+	/* calculate the Two's complement offset */
    offset = sizebytes - SMM_OFFSET;
    offset = (offset >> 12) & 0x000fffff;
-	printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, offset);
+	printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, SMM_OFFSET);

-	msr.hi = offset << 8 | MSR_MC;
+	msr.hi = offset << 8 | gl->hi;
    msr.hi |= SMM_OFFSET>>24;

msr.lo = SMM_OFFSET << 8;
-	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
-	
+	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
+
    wrmsr(gl->desc_name, msr);	// MSR - See table above
-	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+	printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
 }
-static void
-SMMGL1Init(struct gliutable *gl) {
+
+static void SMMGL1Init(struct gliutable *gl) {
    msr_t msr;
    printk_debug("%s:\n", __FUNCTION__ );

@@ -193,58 +185,57 @@
    /* I don't think this is needed */
    msr.hi &= 0xffffff00;
    msr.hi |= (SMM_OFFSET >> 24);
-	msr.lo = SMM_OFFSET << 8;
-	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
-	
+	msr.lo = (SMM_OFFSET << 8) & 0xFFF00000;
+	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
+
    wrmsr(gl->desc_name, msr);	// MSR - See table above
-	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+	printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
 }

-static void
-GLIUInit(struct gliutable *gl){
+static void GLIUInit(struct gliutable *gl){

while (gl->desc_type != GL_END){
    	switch(gl->desc_type){
-		default: 
+		default:
    		/* For Unknown types: Write then read MSR */
    		writeglmsr(gl);
-		case SC_SHADOW: /*  Check for a Shadow entry*/
+		case SC_SHADOW: /*	Check for a Shadow entry*/
    		ShadowInit(gl);
    		break;
-	
+
    	case R_SYSMEM: /*  check for a SYSMEM entry*/
    		SysmemInit(gl);
    		break;
-	
+
    	case BMO_SMM	: /*  check for a SMM entry*/
    		SMMGL0Init(gl);
    		break;
-	
+
    	case BM_SMM	: /*  check for a SMM entry*/
-			SMMGL1Init(gl);	
+			SMMGL1Init(gl);
    		break;
    	}
    	gl++;
    }

}
-	/* ***************************************************************************/
-	/* **/
-	/* *	GLPCIInit*/
-	/* **/
-	/* *	Set up GLPCI settings for reads/write into memory*/
-	/* *	R0:  0-640KB,*/
-	/* *	R1:  1MB - Top of System Memory*/
-	/* *	R2: SMM Memory*/
-	/* *	R3: Framebuffer? - not set up yet*/
-	/* *	R4: ??*/
-	/* **/
-	/* *	Entry:*/
-	/* *	Exit:*/
-	/* *	Modified:*/
-	/* **/
-	/* ***************************************************************************/
+
+/* ***************************************************************************/
+/* **/
+/* *	GLPCIInit*/
+/* **/
+/* *	Set up GLPCI settings for reads/write into memory*/
+/* *	R0:	 0-640KB,*/
+/* *	R1:	 1MB - Top of System Memory*/
+/* *	R2: SMM Memory*/
+/* *	R3: Framebuffer? - not set up yet*/
+/* *	R4: ??*/
+/* **/
+/* *	Entry:*/
+/* *	Exit:*/
+/* *	Modified:*/
+/* **/
+/* ***************************************************************************/
 static void GLPCIInit(void){
    struct gliutable *gl = 0;
    int i;
@@ -253,18 +244,18 @@
    int nic_grants_control, enable_bus_parking;

/* */
-	/*  R0 - GLPCI settings for Conventional Memory space.*/
+	/*	R0 - GLPCI settings for Conventional Memory space.*/
    /* */
-	msr.hi =  (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT		/*  640*/;
-	msr.lo =  0							/*  0*/;
+	msr.hi =  (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;		/* 640 */
+	msr.lo =  0;							/* 0*/
    msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
    msrnum = GLPCI_RC0;
    wrmsr(msrnum, msr);

/* */
-	/*  R1 - GLPCI settings for SysMem space.*/
+	/*	R1 - GLPCI settings for SysMem space.*/
    /* */
-	/*  Get systop from GLIU0 SYSTOP Descriptor*/
+	/* Get systop from GLIU0 SYSTOP Descriptor */
    for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
    	if (gliu0table[i].desc_type == R_SYSMEM) {
    		gl = &gliu0table[i];
@@ -276,15 +267,14 @@
    	msrnum = gl->desc_name;
    	msr = rdmsr(msrnum);
    	/* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
-                 * translates to a base of 0x00100000 and top of 0xffbf0000
-                 * base of 1M and top of around 256M
+				 * translates to a base of 0x00100000 and top of 0xffbf0000
+				 * base of 1M and top of around 256M
    	 */
    	/* we have to create a page-aligned (4KB page) address for base and top */
    	/* So we need a high page aligned addresss (pah) and low page aligned address (pal)
    	 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
    	 */
-		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
-		pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
+		pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);
    	/* we have the page address. Now make it a page-aligned address */
    	pah <<= 12;

@@ -292,24 +282,25 @@
    	msr.hi =  pah;
    	msr.lo =  pal;
    	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
-		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
    	msrnum = GLPCI_RC1;
    	wrmsr(msrnum, msr);
    }

/* */
-	/*  R2 - GLPCI settings for SMM space.*/
+	/*	R2 - GLPCI settings for SMM space */
    /* */
    msr.hi =  ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
    msr.lo =  (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
    msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
+	printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
    msrnum = GLPCI_RC2;
    wrmsr(msrnum, msr);

/* this is done elsewhere already, but it does no harm to do it more than once */
-	/*  write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
-	msr.lo =  0x021212121								/*  cache disabled and write serialized*/;
-	msr.hi =  0x021212121								/*  cache disabled and write serialized*/;
+	/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
+	msr.lo =  0x021212121;								/* cache disabled and write serialized */
+	msr.hi =  0x021212121;								/* cache disabled and write serialized */

msrnum = CPU_RCONF_A0_BF;
    wrmsr(msrnum, msr);
@@ -320,7 +311,7 @@
    msrnum = CPU_RCONF_E0_FF;
    wrmsr(msrnum, msr);

-	/*  Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/
+	/* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */
    msrnum = GLPCI_A0_BF;
    msr.hi =  0x35353535;
    msr.lo =  0x35353535;
@@ -336,22 +327,21 @@
    msr.lo =  0x35353535;
    wrmsr(msrnum, msr);

-	/*  Set WSREQ*/
+	/* Set WSREQ */
    msrnum = CPU_DM_CONFIG0;
    msr = rdmsr(msrnum);
    msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
-	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT	;	/*  reduce to 1 for safe mode.*/
+	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT;	/* reduce to 1 for safe mode */
    wrmsr(msrnum, msr);

/* we are ignoring the 5530 case for now, and perhaps forever. */

/* */
-	/* 5535 NB Init*/
-	/* */	
+	/* 553x NB Init*/
+	/* */

/* Arbiter setup */
-
-	enable_preempt = GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET; 
+	enable_preempt = GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET;
    enable_cpu_override = GLPCI_ARB_LOWER_COV_SET;
    enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET;
    nic_grants_control = (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 << GLPCI_ARB_UPPER_H2_SHIFT );
@@ -360,13 +350,13 @@
    msr = rdmsr(msrnum);

msr.hi |=  nic_grants_control;
-	msr.lo |=  enable_cpu_override  | enable_preempt | enable_bus_parking;
+	msr.lo |=  enable_cpu_override	| enable_preempt | enable_bus_parking;
    wrmsr(msrnum, msr);

msrnum = GLPCI_CTRL;
    msr = rdmsr(msrnum);

-	msr.lo |=  GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; 	/*   (Out will be disabled in CPUBUG649 for < 2.0 parts .)*/
+	msr.lo |=  GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET;	/* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
    msr.lo |=  GLPCI_CTRL_LOWER_LDE_SET;

msr.lo &=  ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
@@ -374,84 +364,61 @@

msr.lo &=  ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
    msr.lo |=  0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
-	
+
    msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
    msr.hi |=  0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
-	
+
    msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
    msr.hi |=  0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
-	
+
    msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
    msr.hi |=  0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
-	
+
    msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
    msr.hi |=  0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
-	
+
    msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
    msr.hi |=  0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
    wrmsr(msrnum, msr);

-	/*  Set GLPCI Latency Timer.*/
+	/* Set GLPCI Latency Timer */
    msrnum = GLPCI_CTRL;
    msr = rdmsr(msrnum);
-	msr.hi |=  0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; 	/*  Change once 1.x is gone.*/
+	msr.hi |=  0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT;	/* Change once 1.x is gone */
    wrmsr(msrnum, msr);

-	/*  GLPCI_SPARE*/
+	/* GLPCI_SPARE */
    msrnum = GLPCI_SPARE;
    msr = rdmsr(msrnum);
    msr.lo &=  ~ 0x7;
    msr.lo |=  GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
    wrmsr(msrnum, msr);
-
 }

-	/* ***************************************************************************/
-	/* **/
-	/* *	ClockGatingInit*/
-	/* **/
-	/* *	Enable Clock Gating.*/
-	/* **/
-	/* *	Entry:*/
-	/* *	Exit:*/
-	/* *	Modified:*/
-	/* **/
-	/* ***************************************************************************/
-static void 
-ClockGatingInit (void){
+/* ***************************************************************************/
+/* **/
+/* *	ClockGatingInit*/
+/* **/
+/* *	Enable Clock Gating.*/
+/* **/
+/* *	Entry:*/
+/* *	Exit:*/
+/* *	Modified:*/
+/* **/
+/* ***************************************************************************/
+static void ClockGatingInit (void){
    msr_t msr;
    struct msrinit *gating = ClockGatingDefault;
    int i;

-#if 0
-	mov	cx, TOKEN_CLK_GATE
-	NOSTACK	bx, GetNVRAMValueBX
-	cmp	al, TVALUE_CG_OFF
-	je	gatingdone
-	
-	cmp	al, TVALUE_CG_DEFAULT
-	jb	allon
-	ja	performance
-	lea	si, ClockGatingDefault
-	jmp	nextdevice
-
-allon:
-	lea	si, ClockGatingAllOn
-	jmp	nextdevice
-
-performance:
-	lea	si, ClockGatingPerformance
-#endif
-
    for(i = 0; gating->msrnum != 0xffffffff; i++) {
    	msr = rdmsr(gating->msrnum);
-		//printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, gating->msrnum, msr.hi, msr.lo); //GX3 
    	msr.hi |= gating->msr.hi;
    	msr.lo |= gating->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __FUNCTION__, 
+		/* printk_debug("%s: MSR 0x%08x will be set to	0x%08x:0x%08x\n", __FUNCTION__,
    		gating->msrnum, msr.hi, msr.lo); */ // GX3
    	wrmsr(gating->msrnum, msr);	// MSR - See the table above
    	gating +=1;
@@ -459,35 +426,33 @@

}

-static void 
-GeodeLinkPriority(void){
+static void GeodeLinkPriority(void){
    msr_t msr;
    struct msrinit *prio = GeodeLinkPriorityTable;
    int i;

for(i = 0; prio->msrnum != 0xffffffff; i++) {
    	msr = rdmsr(prio->msrnum);
-		// printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, prio->msrnum, msr.hi, msr.lo); // GX3
    	msr.hi |= prio->msr.hi;
    	msr.lo &= ~0xfff;
    	msr.lo |= prio->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, 
-			prio->msrnum, msr.hi, msr.lo);  */ // GX3
+		/* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__,
+			prio->msrnum, msr.hi, msr.lo);	*/ // GX3
    	wrmsr(prio->msrnum, msr);	// MSR - See the table above
    	prio +=1;
    }
 }

-	
+
 /*
  *	Get the GLIU0 shadow register settings
  *	If the setShadow function is used then all shadow descriptors
  *	  will stay sync'ed.
  */
-static uint64_t getShadow(void)
-{
+static uint64_t getShadow(void){
    msr_t msr;
+
    msr = rdmsr(MSR_GLIU0_SHADOW);
    return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
 }
@@ -499,8 +464,8 @@
  *	This is part of the PCI lockup solution
  *	Entry: EDX:EAX is the shadow settings
  */
-static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
-{
+static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo){
+
    // ok this is whacky bit translation time.
    int bit;
    uint8_t shadowByte;
@@ -555,9 +520,8 @@
 static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
 {
    msr_t msr;
-	
-// Set the Enable Register.

+	// Set the Enable Register.
    msr = rdmsr(GLPCI_REN);
    msr.lo &= 0xFFFF00FF;
    msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8);
@@ -589,29 +553,16 @@

msr = rdmsr(pTable->desc_name);
    			msr.lo = (uint32_t) shadowSettings;
-				msr.hi &= 0xFFFF0000;		// maintain PDID in upper EDX
+				msr.hi &= 0xFFFF0000;			// maintain PDID in upper EDX
    			msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF;
    			wrmsr(pTable->desc_name, msr);	// MSR - See the table above
-
    		}
    	}
    }
 }

-/**************************************************************************
- *
- *	shadowRom
- *
- *	Set up a stack for ease of further testing
- *
- *	Entry:
- *	Exit:
- *	Destroys:
- *
- **************************************************************************/
-static void 
-shadowRom(void)
-{
+static void rom_shadow_settings(void){
+
    uint64_t shadowSettings = getShadow();
    shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL;	// Disable read & writes
    shadowSettings |= (uint64_t) 0x00000000F0000000ULL;	// Enable reads for F0000-FFFFF
@@ -623,15 +574,15 @@

/***************************************************************************
  *
- * RCONFInit
+ * L1Init
  *	  Set up RCONF_DEFAULT and any other RCONF registers needed
  *
- *  DEVRC_RCONF_DEFAULT:
- *  ROMRC(63:56) = 04h	 ; write protect ROMBASE
- *  ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
- *  DEVRC(35:28) =  39h	 ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
- *  SYSTOP(27:8) = top of system memory
- *  SYSRC(7:0) = 00h 		 ; writeback, can set to 08h to make writethrough 
+ *	DEVRC_RCONF_DEFAULT:
+ *	ROMRC(63:56) = 04h	 ; write protect ROMBASE
+ *	ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
+ *	DEVRC(35:28) =	39h	 ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
+ *	SYSTOP(27:8) = top of system memory
+ *	SYSRC(7:0) = 00h		 ; writeback, can set to 08h to make writethrough
  *
  ***************************************************************************/
 #define SYSMEM_RCONF_WRITETHROUGH 8
@@ -639,14 +590,12 @@
 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000
 #define ROMRC_RCONF_DEFAULT 0x25

-static void
-RCONFInit(void)
+static void enable_L1_cache(void)
 {
    struct gliutable *gl = 0;
    int i;
    msr_t msr;
    uint8_t SysMemCacheProp;
-	//uint8_t RegionProp;

/* Locate SYSMEM entry in GLIU0table */
    for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
@@ -660,26 +609,21 @@
    	while (1);
    }

-// sysdescfound:	
-	/* found the descriptor... get its contents */
+	// sysdescfound:
    msr = rdmsr(gl->desc_name);

-	printk_debug("SYSDESC: 0x%08X:0x%08X\n",msr.hi,msr.lo);
-
-	/* 20 bit address -  The bottom 12 bits go into bits 20-31 in eax, the 
-	 * top 8 bits go into 0-7 of edx. 
+	/* 20 bit address -	 The bottom 12 bits go into bits 20-31 in eax, the
+	 * top 8 bits go into 0-7 of edx.
     */
    msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
    msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
    msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	// 8
-	
-	printk_debug("RCONF LO: 0x%08X\n",msr.lo);
-	
+
    // Set Default SYSMEM region properties
-	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	// 8 (or ~8)
+	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	// NOT writethrough == writeback 8 (or ~8)

// Set PCI space cache properties
-	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	// only need the bottom bits and lets clean the rest of edx
+	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	// setting is split betwwen hi and lo...
    msr.lo |= (DEVRC_RCONF_DEFAULT << 28);

// Set the ROMBASE. This is usually FFFC0000h
@@ -687,9 +631,10 @@

// Set ROMBASE cache properties.
    msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
-	
+
    // now program RCONF_DEFAULT
    wrmsr(CPU_RCONF_DEFAULT, msr);
+	printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n",msr.hi,msr.lo);

// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
    // Set to match system memory cache properties.
@@ -698,22 +643,85 @@
    msr = rdmsr(CPU_RCONF_BYPASS);
    msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
    wrmsr(CPU_RCONF_BYPASS, msr);
-	
-	printk_debug("CPU_RCONF_SMM (180E)  0x%08x : 0x%08x\n", msr.hi, msr.lo);
+
+	printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo);
+}
+
+static void enable_L2_cache(void) {
+	msr_t msr;
+
+	/* Instruction Memory Configuration register
+	 * set EBE bit, required when L2 cache is enabled
+	 */
+	msr = rdmsr(CPU_IM_CONFIG);
+	msr.lo |= 0x400;
+	wrmsr(CPU_IM_CONFIG, msr);
+
+	/* Data Memory Subsystem Configuration register
+	 * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
+	 */
+	msr = rdmsr(CPU_DM_CONFIG0);
+	msr.lo |= 0x4000;
+	wrmsr(CPU_DM_CONFIG0, msr);
+
+	/* invalidate L2 cache */
+	msr.hi = 0x00;
+	msr.lo = 0x10;
+	wrmsr(CPU_BC_L2_CONF, msr);
+
+	/* Enable L2 cache */
+	msr.hi = 0x00;
+	msr.lo = 0x0f;
+	wrmsr(CPU_BC_L2_CONF, msr);
+
+	printk_debug("L2 cache enabled\n");
 }

+static void setup_lx_cache(void)
+{
+	msr_t msr;
+
+	enable_L1_cache();
+	enable_L2_cache();
+
+	// Make sure all INVD instructions are treated as WBINVD.  We do this
+	// because we've found some programs which require this behavior.
+	msr = rdmsr(CPU_DM_CONFIG0);
+	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
+	wrmsr(CPU_DM_CONFIG0, msr);
+
+	x86_enable_cache();
+	wbinvd();
+}
+
+uint32_t get_systop(void) {
+	struct gliutable *gl = 0;
+	uint32_t systop;
+	msr_t msr;
+	int i;
+
+	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
+		if (gliu0table[i].desc_type == R_SYSMEM) {
+			gl = &gliu0table[i];
+			break;
+		}
+	}
+	if (gl) {
+		msr = rdmsr(gl->desc_name);
+		systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);
+		systop += 0x1000;		/* 4K */
+	}else{
+		systop = ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024;
+	}
+	return systop;
+}

/****************************************************************************/
 /* *	northbridge_init_early */
 /* **/
-/* *	Core Logic initialization:  Host bridge*/
-/* **/
-/* *	Entry:*/
-/* *	Exit:*/
-/* *	Modified:*/
+/* *	Core Logic initialization:	Host bridge*/
 /* **/
 /* ***************************************************************************/
-
 void northbridge_init_early(void)
 {
    msr_t msr;
@@ -723,34 +731,21 @@
    for(i = 0; gliutables[i]; i++)
    	GLIUInit(gliutables[i]);

-	GeodeLinkPriority();
-	
-	shadowRom();
-	
-	// GeodeROM ensures that the BIOS waits the required 1 second before 
-	// allowing anything to access PCI
-	// PCIDelay();
-	
-	RCONFInit();
-	
-	// The cacheInit function in GeodeROM tests cache and, among other things,
-	// makes sure all INVD instructions are treated as WBINVD.  We do this
-	// because we've found some programs which require this behavior.
-	// That subset of cacheInit() is implemented here:
-	
-	/* GX3 OK */
-	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
-	wrmsr(CPU_DM_CONFIG0, msr);
-	
-	/*  Now that the descriptor to memory is set up.*/
-	/*  The memory controller needs one read to synch its lines before it can be used.*/
+	/*	Now that the descriptor to memory is set up.*/
+	/*	The memory controller needs one read to synch its lines before it can be used.*/
    i = *(int *) 0;

+	GeodeLinkPriority();
+
+	setup_lx_cache();
+
+	rom_shadow_settings();
+
    GLPCIInit();
+
    ClockGatingInit();
-	__asm__("FINIT\n");
-	/* CPUBugsFix -- called elsewhere */
+
+	__asm__ __volatile__("FINIT\n");
    printk_debug("Exit %s\n", __FUNCTION__);
 }

Index: LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c
===================================================================
--- LinuxBIOSv2.orig/src/northbridge/amd/lx/pll_reset.c	2007-05-01 14:37:02.000000000 -0600
+++ LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c	2007-05-01 14:40:34.000000000 -0600
@@ -1,43 +1,103 @@
-#define POST_CODE(x) outb(0x80, x)
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */

-static void pll_reset(void)
+static void pll_reset(char manualconf)
 {
    msr_t msrGlcpSysRstpll;

-        msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
-	
+	msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
+
    print_debug("_MSR GLCP_SYS_RSTPLL (");
    	print_debug_hex32(GLCP_SYS_RSTPLL);
    	print_debug(") value is: ");
    	print_debug_hex32(msrGlcpSysRstpll.hi);
    	print_debug(":");
    	print_debug_hex32(msrGlcpSysRstpll.lo);
-		print_debug("\n");
-	
-        msrGlcpSysRstpll.lo &= 0x80000000;
-
-	// If the "we've already been here" flag is set, don't reconfigure the pll
-        if ( !(msrGlcpSysRstpll.lo) )
-	{ // we haven't configured the PLL; do it now
-	    print_debug("CONFIGURING PLL");
-	
-                POST_CODE(0x77);
-	
-		// HARDCODED VALUES MOVED BACK TO auto.c AS THEY HAVE TO BE BOARD-SPECIFIC
-		// (this file is included from there)
+		print_debug("\r\n");
+	POST_CODE(POST_PLL_INIT);

-			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
-		msrGlcpSysRstpll.hi = PLLMSRhi;
+	if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))){
+		print_debug("Configuring PLL\n");
+		if(manualconf){
+			POST_CODE(POST_PLL_MANUAL);
+			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)	*/
+			msrGlcpSysRstpll.hi = PLLMSRhi;

/* Hold Count - how long we will sit in reset */
-		msrGlcpSysRstpll.lo = PLLMSRlo;
+			msrGlcpSysRstpll.lo = PLLMSRlo;
+		}
+		else{
+			/*automatic configuration (straps)*/
+			POST_CODE(POST_PLL_STRAP);
+			msrGlcpSysRstpll.lo &= ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
+			msrGlcpSysRstpll.lo |= (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
+			msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_COREBYPASS_SET | RSTPPL_LOWER_MBBYPASS_SET);
+			msrGlcpSysRstpll.lo |= RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
+		}
+		/* Use SWFLAGS to remember: "we've already been here"  */
+		msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);

-			/* Use SWFLAGS to remember: "we've already been here"  */
-			msrGlcpSysRstpll.lo |= 0x80000000;
+		/* "reset the chip" value */
+		msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
+		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);

-			/* "reset the chip" value */
-			msrGlcpSysRstpll.lo |= 0x00000001;
+		/*	You should never get here..... The chip has reset.*/
+		print_debug("CONFIGURING PLL FAILURE\n");
+		POST_CODE(POST_PLL_RESET_FAIL);
+		__asm__ __volatile__("hlt\n");

-		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
    }
+	print_debug("Done cpuRegInit\n");
+	return;
 }
+
+static unsigned int CPUSpeed(void){
+	unsigned int speed;
+	msr_t msr;
+
+	msr = rdmsr(GLCP_SYS_RSTPLL);
+	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F)+1)*333)/10;
+	if((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F)+1)*333)%10) > 5){
+		++speed;
+	}
+	return(speed);
+}
+static unsigned int GeodeLinkSpeed(void){
+	unsigned int speed;
+	msr_t msr;
+
+	msr = rdmsr(GLCP_SYS_RSTPLL);
+	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F)+1)*333)/10;
+	if((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F)+1)*333)%10) > 5){
+		++speed;
+	}
+	return(speed);
+}
+static unsigned int PCISpeed(void){
+	msr_t msr;
+
+	msr = rdmsr(GLCP_SYS_RSTPLL);
+	if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)){
+		return(66);
+	}
+	else{
+		return(33);
+	}
+}
+
Index: LinuxBIOSv2/src/northbridge/amd/lx/raminit.c
===================================================================
--- LinuxBIOSv2.orig/src/northbridge/amd/lx/raminit.c	2007-05-01 14:37:02.000000000 -0600
+++ LinuxBIOSv2/src/northbridge/amd/lx/raminit.c	2007-05-01 14:38:33.000000000 -0600
@@ -1,123 +1,769 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	 02110-1301 USA
+*/
+
 #include <cpu/amd/lxdef.h>
+#include <arch/io.h>
+#include <spd.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+static const unsigned char NumColAddr[] = {0x00,0x10,0x11,0x00,0x00,0x00,0x00,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F};
+
+static void auto_size_dimm(unsigned int dimm){
+	uint32_t dimm_setting;
+	uint16_t dimm_size;
+	uint8_t spd_byte;
+	msr_t msr;

+	dimm_setting = 0;

-static void sdram_set_registers(const struct mem_controller *ctrl)
-{
+	/* Check that we have a dimm */
+	if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF){
+		return;
+	}
+
+	/* Field: Module Banks per DIMM */
+	/* EEPROM byte usage: (5) Number of DIMM Banks */
+	spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
+	if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)){
+		print_debug("Number of module banks not compatible\r\n");
+		POST_CODE(ERROR_BANK_SET);
+		__asm__ __volatile__("hlt\n");
+	}
+	dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
+
+
+	/* Field: Banks per SDRAM device */
+	/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
+	spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
+	if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)){
+		print_debug("Number of device banks not compatible\r\n");
+		POST_CODE(ERROR_BANK_SET);
+		__asm__ __volatile__("hlt\n");
+	}
+	dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
+
+
+	/*; Field: DIMM size
+	*; EEPROM byte usage: (3)  Number or Row Addresses
+	*;					  (4)  Number of Column Addresses
+	*;					  (5)  Number of DIMM Banks
+	*;					  (31) Module Bank Density
+	*; Size = Module Density * Module Banks
+	*/
+	if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)){
+		print_debug("Assymetirc DIMM not compatible\r\n");
+		POST_CODE(ERROR_UNSUPPORTED_DIMM);
+		__asm__ __volatile__("hlt\n");
+	}
+
+	dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
+	dimm_size |= (dimm_size << 8);	/* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out*/
+	dimm_size &= 0x01FC;		/* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top*/
+
+	/*	 Module Density * Module Banks */
+	dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
+	dimm_size = __builtin_ctz(dimm_size);
+	if (dimm_size > 8){		/* 8 is 1GB only support 1GB per DIMM */
+		print_debug("Only support up to 1 GB per DIMM\r\n");
+		POST_CODE(ERROR_DENSITY_DIMM);
+		__asm__ __volatile__("hlt\n");
+	}
+	dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
+
+
+/*; Field: PAGE size
+*; EEPROM byte usage: (4)  Number of Column Addresses
+*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
+*
+*; But this really works by magic.
+*;If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address
+*;that MC generates, here is how the MC assigns the pa onto the ma pins:
+*
+*;ma  12 11 10 09 08 07 06 05 04 03 02 01 00
+*;-------------------------------------------
+*;pa					09 08 07 06 05 04 03	(7 col addr bits = 1K page size)
+*;pa				 10 09 08 07 06 05 04 03	(8 col addr bits = 2K page size)
+*;pa			  11 10 09 08 07 06 05 04 03	(9 col addr bits = 4K page size)
+*;pa		   12 11 10 09 08 07 06 05 04 03	(10 col addr bits = 8K page size)
+*;pa	 13 AP 12 11 10 09 08 07 06 05 04 03	(11 col addr bits = 16K page size)
+*;pa  14 13 AP 12 11 10 09 08 07 06 05 04 03	(12 col addr bits = 32K page size)
+*; *AP=autoprecharge bit
+*
+*;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
+*;so lower 3 address bits are dont_cares.So from the table above,
+*;it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
+*;it adds 3 to get 10, then does 2^10=1K.  Get it?*/
+
+	spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
+	if (spd_byte > MAX_COL_ADDR) {
+		print_debug("DIMM page size not compatible\r\n");
+		POST_CODE(ERROR_SET_PAGE);
+		__asm__ __volatile__("hlt\n");
+	}
+	spd_byte -=7;
+	if (spd_byte > 5){			/* if the value is above 6 it means >12 address lines */
+		spd_byte = 7;			/* which means >32k so set to disabled */
+	}
+	dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
+
+	msr = rdmsr(MC_CF07_DATA);
+	if (dimm == DIMM0){
+		msr.hi &= 0xFFFF0000;
+		msr.hi |= dimm_setting;
+	}else{
+		msr.hi &= 0x0000FFFF;
+		msr.hi |= dimm_setting << 16;
+	}
+	wrmsr(MC_CF07_DATA, msr);
 }

-/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
- * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
-static void sdram_enable(int controllers, const struct mem_controller *ctrl)
-{
-	int i;
+
+static void checkDDRMax(void){
+	uint8_t spd_byte0, spd_byte1;
+	uint16_t speed;
+
+	 /* PC133 identifier */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+	if (spd_byte0 == 0xFF){
+		spd_byte0=0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+	if (spd_byte1 == 0xFF){
+		spd_byte1=0;
+	}
+
+	/* I don't think you need this check.
+	if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){
+		print_debug("DIMM overclocked. Check GeodeLink Speed\r\n");
+		POST_CODE(POST_PLL_MEM_FAIL);
+		__asm__	 __volatile__("hlt\n");
+	}*/
+
+
+	/* Use the slowest DIMM */
+	if (spd_byte0 < spd_byte1){
+		spd_byte0 = spd_byte1;
+	}
+
+	/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+	speed = 2*((10000/(((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));
+
+	/* current speed > max speed? */
+	if (GeodeLinkSpeed() > speed){
+		print_debug("DIMM overclocked. Check GeodeLink Speed\r\n");
+		POST_CODE(POST_PLL_MEM_FAIL);
+		__asm__ __volatile__("hlt\n");
+	}
+}
+
+
+const uint16_t REF_RATE[] = {15, 3, 7, 31, 62, 125}; /* ns */
+
+static void set_refresh_rate(void){
+	uint8_t spd_byte0, spd_byte1;
+	uint16_t rate0, rate1;
+	msr_t msr;
+
+	spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
+	spd_byte0 &= 0xF;
+	if (spd_byte0 > 5){
+		spd_byte0 = 5;
+	}
+	rate0 = REF_RATE[spd_byte0];
+
+	spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
+	spd_byte1 &= 0xF;
+	if (spd_byte1 > 5){
+		spd_byte1 = 5;
+	}
+	rate1 = REF_RATE[spd_byte1];
+
+	/* Use the faster rate (lowest number) */
+	if (rate0 > rate1){
+		rate0 = rate1;
+	}
+
+	msr = rdmsr(MC_CF07_DATA);
+	msr.lo|= ((rate0 * (GeodeLinkSpeed()/2))/16) << CF07_LOWER_REF_INT_SHIFT;
+	wrmsr(MC_CF07_DATA,msr);
+}
+
+
+const uint8_t CASDDR[] = {5, 5, 2, 6, 3, 7, 4, 0}; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
+
+static void setCAS(void){
+/*;*****************************************************************************
+;*
+;*	setCAS
+;*	EEPROM byte usage: (18) SDRAM device attributes - CAS latency
+;*	EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
+;*	EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
+;*
+;*	The CAS setting is based on the information provided in each DIMMs SPD.
+;*	 The speed at which a DIMM can run is described relative to the slowest
+;*	 CAS the DIMM supports. Each speed for the relative CAS settings is
+;*	 checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
+;*	 speed, the CAS setting	 is removed from the list of good settings for
+;*	 the DIMM. This is done for both DIMMs and the lists are compared to
+;*	 find the lowest common CAS latency setting. If there are no CAS settings
+;*	 in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
+;*
+;*	Entry:
+;*	Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
+;*	Destroys: We really use everything !
+;*****************************************************************************/
+	uint16_t glspeed, dimm_speed;
+	uint8_t spd_byte, casmap0, casmap1;
    msr_t msr;

-	/* DRAM initialization sequence according to the documentation:
-	 * 1)  Initialize the following GLMC registers/bits based on Serial Presence Detect (SPD) values:
-	 *  — MSR 20000018h except REF_INT bits [23:8]
-   	 *   — MSR 20000019h
-   	 */
-   	
-   	// This is done by sdram_set_spd_registers() that is called by sdram/generic_sdram.c just before this
-   	// sdram_set_spd_registers is responsible for reading ram settings from spd rom and configuring sdram conrtoller
-   	// Here follows generic sdram initialization procedure.
-
-	/* 2)  Initialize the following GLMC registers:
-	 *	— MSR 2000001Ah[15:8] = C8h
-	 *	— MSR 20002004h[2] = 0, [0] = 1
-	 */
-	msr.hi = 0x00000000;
-	msr.lo = 0x130AD101;
+	glspeed = GeodeLinkSpeed();
+
+	/**************************	 DIMM0	**********************************/
+	casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
+	if (casmap0 != 0xFF){
+		/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
+		spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
+		if(spd_byte != 0){
+			/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+			dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
+			if (dimm_speed >= glspeed){
+				/* IF -1 timing is supported, check -1 timing > GeodeLink */
+				spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
+				if(spd_byte != 0){
+					/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+					dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
+					if (dimm_speed <= glspeed){
+						/* set we can use -.5 timing but not -1 */
+						spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */
+						casmap0 &= 0xFF << (--spd_byte);
+					}
+				}		/*MIN_CYCLE_10 !=0 */
+			}
+			else{		/* Timing_05 < GLspeed, can't use -.5 or -1 timing */
+				spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */
+				casmap0 &= 0xFF << (spd_byte);
+			}
+		}				/*MIN_CYCLE_05 !=0 */
+	}
+	else{				/* No DIMM */
+		casmap0=0;
+	}
+
+	/**************************	 DIMM1	**********************************/
+	casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES);
+	if (casmap1 != 0xFF){
+		/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
+		spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND);
+		if(spd_byte != 0){
+			/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+			dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
+			if (dimm_speed >= glspeed){
+				/* IF -1 timing is supported, check -1 timing > GeodeLink */
+				spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD);
+				if(spd_byte != 0){
+					/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+					dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
+					if (dimm_speed <= glspeed){
+						/* set we can use -.5 timing but not -1 */
+						spd_byte =31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */
+						casmap1 &= 0xFF << (--spd_byte);
+					}
+				}		/*MIN_CYCLE_10 !=0 */
+			}
+			else{		/* Timing_05 < GLspeed, can't use -.5 or -1 timing */
+				spd_byte = 31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */
+				casmap1 &= 0xFF << (spd_byte);
+			}
+		}				/*MIN_CYCLE_05 !=0 */
+	}
+	else{				/* No DIMM */
+		casmap1=0;
+	}
+
+	/*********************	CAS_LAT MAP COMPARE	***************************/
+	if (casmap0 == 0){
+		spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap1)];
+	}
+	else if (casmap1 == 0){
+		spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap0)];
+	}
+	else if ((casmap0 &= casmap1)){
+		spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap0)];
+	}
+	else{
+		print_debug("DIMM CAS Latencies not compatible\r\n");
+		POST_CODE(ERROR_DIFF_DIMMS);
+		__asm__ __volatile__("hlt\n");
+	}
+
+
+	msr = rdmsr(MC_CF8F_DATA);
+	msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
+	msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
+	wrmsr(MC_CF8F_DATA, msr);
+}
+
+
+static void set_latencies(void){
+	uint32_t memspeed, dimm_setting;
+	uint8_t spd_byte0, spd_byte1;
+	msr_t msr;
+
+	memspeed = GeodeLinkSpeed()/2;
+	dimm_setting=0;
+
+	/* MC_CF8F setup */
+	/* tRAS */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
+	if (spd_byte0 == 0xFF){
+		spd_byte0=0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
+	if (spd_byte1 == 0xFF){
+		spd_byte1=0;
+	}
+	if (spd_byte0 < spd_byte1){
+		spd_byte0 = spd_byte1;
+	}
+
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	spd_byte1 = (spd_byte0 * memspeed)/1000;
+	if(((spd_byte0 * memspeed)%1000)){
+		++spd_byte1;
+	}
+	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
+
+
+	/* tRP */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
+	if (spd_byte0 == 0xFF){
+		spd_byte0=0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
+	if (spd_byte1 == 0xFF){
+		spd_byte1=0;
+	}
+	if (spd_byte0 < spd_byte1){
+		spd_byte0 = spd_byte1;
+	}
+
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000;
+	if((((spd_byte0 >> 2) * memspeed)%1000)){
+		++spd_byte1;
+	}
+	dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
+
+
+	/* tRCD */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
+	if (spd_byte0 == 0xFF){
+		spd_byte0=0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
+	if (spd_byte1 == 0xFF){
+		spd_byte1=0;
+	}
+	if (spd_byte0 < spd_byte1){
+		spd_byte0 = spd_byte1;
+	}
+
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000;
+	if((((spd_byte0 >> 2) * memspeed)%1000)){
+		++spd_byte1;
+	}
+	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
+
+
+	/* tRRD */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
+	if (spd_byte0 == 0xFF){
+		spd_byte0=0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
+	if (spd_byte1 == 0xFF){
+		spd_byte1=0;
+	}
+	if (spd_byte0 < spd_byte1){
+		spd_byte0 = spd_byte1;
+	}
+
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000;
+	if((((spd_byte0 >> 2) * memspeed)%1000)){
+		++spd_byte1;
+	}
+	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
+
+
+	/* tRC = tRP + tRAS */
+	dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) \
+					 << CF8F_LOWER_ACT2ACTREF_SHIFT;
+
+
+	msr = rdmsr(MC_CF8F_DATA);
+	msr.lo &= 0xF00000FF;
+	msr.lo |= dimm_setting;
+	msr.hi |=  CF8F_UPPER_REORDER_DIS_SET;
+	wrmsr(MC_CF8F_DATA, msr);
+
+	/* MC_CF1017 setup */
+	/* tRFC */
+	spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC);
+	if (spd_byte0 == 0xFF){
+		spd_byte0=0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC);
+	if (spd_byte1 == 0xFF){
+		spd_byte1=0;
+	}
+	if (spd_byte0 < spd_byte1){
+		spd_byte0 = spd_byte1;
+	}
+
+	if (spd_byte0){
+		/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+		spd_byte1 = (spd_byte0 * memspeed)/1000;
+		if(((spd_byte0 * memspeed)%1000)){
+			++spd_byte1;
+		}
+	}
+	else{	/* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
+		spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
+	}
+	dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT;		/* note this clears the cf8f dimm setting */
+	msr = rdmsr(MC_CF1017_DATA);
+	msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);
+	msr.lo |= dimm_setting;
    wrmsr(MC_CF1017_DATA, msr);

-	//ok
-	msr.hi = 0x00000000;
-	msr.lo = 0x00000001;
-	wrmsr(MC_GLD_MSR_PM, msr);
+	/* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */
+	if (memspeed > 198){
+		msr = rdmsr(MC_CF1017_DATA);
+		msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
+		msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT;
+		wrmsr(MC_CF1017_DATA, msr);
+	}
+}

-	/* 3) Release MASK_CKE[1:0] (MSR 2000001Dh[9:8] = 11) */
+static void set_extended_mode_registers(void){
+	uint8_t spd_byte0, spd_byte1;
+	msr_t msr;
+	spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
+	if (spd_byte0 == 0xFF){
+		spd_byte0=0;
+	}
+	spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
+	if (spd_byte1 == 0xFF){
+		spd_byte1=0;
+	}
+	spd_byte1 &= spd_byte0;

-	msr.hi = 0x00000000;
-	msr.lo = 0x00000000;
-	wrmsr(MC_CFCLK_DBUG, msr);
-	
-	// reset memory controller
    msr = rdmsr(MC_CF07_DATA);
-	msr.lo |=  0x00000002;
-	wrmsr(MC_CF07_DATA, msr);
-	msr.lo &= 0xFFFFFFFD;
+		if (spd_byte1 & 1){		/* Drive Strength Control */
+		msr.lo |= CF07_LOWER_EMR_DRV_SET;
+	}
+	if (spd_byte1 & 2){			/* FET Control */
+		msr.lo |= CF07_LOWER_EMR_QFC_SET;
+	}
    wrmsr(MC_CF07_DATA, msr);
+}
+
+static void EnableMTest (void){
+	msr_t msr;

-	/* 4. set and clear REF_TST 16 times, more shouldn't hurt
-	 * why this is before EMRS and MRS ? */
-	 
-	for (i = 0; i < 19; i++) {
-		msr = rdmsr(MC_CF07_DATA);
-		msr.lo |=  0x00000008;
-		wrmsr(MC_CF07_DATA, msr);
-		msr.lo &= 0xFFFFFFF7;
-		wrmsr(MC_CF07_DATA, msr);
+	msr = rdmsr(GLCP_DELAY_CONTROLS);
+	msr.hi &= ~(7 << 20);				/* clear bits 54:52 */
+	if (GeodeLinkSpeed() < 200){
+		msr.hi |= 2 << 20;
    }
+	wrmsr(GLCP_DELAY_CONTROLS, msr);

+	msr = rdmsr(MC_CFCLK_DBUG);
+	msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET | CFCLK_UPPER_MTST_RBEX_EN_SET;
+	msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
+	wrmsr(MC_CFCLK_DBUG, msr);

-	/* 5) Initialize REF_INT (MSR 20000018h[23:8]) to set refresh interval.	*/
-	msr.lo |= 0x3A00;
-	wrmsr(MC_CF07_DATA, msr);
+	print_debug("Enabled MTest for TLA debug\r\n");
+}

-	/* 6) Perform load-mode with MSR_BA = 01 (MSR 200000018h[29:28] = 01) 
-	 * to initialize DIMM Extended Mode register. 
-	 * Load-mode is performed by setting/clearing PROG_DRAM (MSR 200000018h[0]).
-	 */
-// eeldus et bit29 = 0, mida ta praegu ka on
-	msr.lo |=  ((0x01 << 28) | 0x01);
-	wrmsr(MC_CF07_DATA, msr);
+static void sdram_set_registers(const struct mem_controller *ctrl)
+{
+	msr_t msr;
+	uint32_t msrnum;

-	msr.lo &= ~((0x01 << 28) | 0x01);
-	wrmsr(MC_CF07_DATA, msr);
+	/* Set Timing Control */
+	msrnum = MC_CF1017_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
+	if (GeodeLinkSpeed() < 334){
+		msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
+	}
+	else{
+		msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
+	}
+	wrmsr(msrnum, msr);
+
+	/* Set Refresh Staggering */
+	msrnum = MC_CF07_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~0xF0;
+	msr.lo |= 0x40;			/* set refresh to 4SDRAM clocks */
+	wrmsr(msrnum, msr);
+
+	/* Memory Interleave: Set HOI here otherwise default is LOI */
+	/* msrnum = MC_CF8F_DATA;
+	msr = rdmsr(msrnum);
+	msr.hi |= CF8F_UPPER_HOI_LOI_SET;
+	wrmsr(msrnum, msr); */
+}
+
+
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+	uint8_t spd_byte;
+
+	POST_CODE(POST_MEM_SETUP);		// post_70h
+
+	spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
+	/* Check DIMM is not Register and not Buffered DIMMs. */
+	if ((spd_byte != 0xFF) && (spd_byte & 3) ){
+		print_debug("DIMM0 NOT COMPATIBLE\r\n");
+		POST_CODE(ERROR_UNSUPPORTED_DIMM);
+		__asm__ __volatile__("hlt\n");
+	}
+	spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
+	if ((spd_byte != 0xFF) && (spd_byte & 3)){
+		print_debug("DIMM1 NOT COMPATIBLE\r\n");
+		POST_CODE(ERROR_UNSUPPORTED_DIMM);
+		__asm__ __volatile__("hlt\n");
+	}
+
+	POST_CODE(POST_MEM_SETUP2);		// post_72h
+
+	/* Check that the memory is not overclocked. */
+	checkDDRMax();
+
+	/* Size the DIMMS */
+	POST_CODE(POST_MEM_SETUP3);		// post_73h
+	auto_size_dimm(DIMM0);
+	POST_CODE(POST_MEM_SETUP4);		// post_74h
+	auto_size_dimm(DIMM1);
+
+	/* Set CAS latency */
+	POST_CODE(POST_MEM_SETUP5);		// post_75h
+	setCAS();
+
+	/* Set all the other latencies here (tRAS, tRP....) */
+	set_latencies();
+
+	/* Set Extended Mode Registers */
+	set_extended_mode_registers();
+
+	/* Set Memory Refresh Rate */
+	set_refresh_rate();
+
+}

+/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
+ * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
+static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+{
+	uint32_t i, msrnum;
+	msr_t msr;
+
+/*********************************************************************
+;* Turn on MC/DIMM interface per JEDEC
+;* 1) Clock stabilizes > 200us
+;* 2) Assert CKE
+;* 3) Precharge All to put all banks into an idles state
+;* 4) EMRS to enable DLL
+;* 6) MRS w/ memory config & reset DLL set
+;* 7) Wait 200 clocks (2us)
+;* 8) Precharge All and 2 Auto refresh
+;* 9) MRS w/ memory config & reset DLL clear
+;* 8) DDR SDRAM ready for normal operation
+;********************************************************************/
+	POST_CODE(POST_MEM_ENABLE);		// post_76h

-	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
-	 * it is documented in LX datasheet  */	
-	/* load Mode Register by set and clear PROG_DRAM */
-// eeldus et bit27:28=00, mida nad ka on
+	/* Only enable MTest for TLA memory debug */
+	/*EnableMTest();*/
+
+	/* If both Page Size = "Not Installed" we have a problems and should halt. */
    msr = rdmsr(MC_CF07_DATA);
-	msr.lo |=  ((0x01 << 27) | 0x01);
-	wrmsr(MC_CF07_DATA, msr);
-	msr.lo &= ~((0x01 << 27) | 0x01);
-	wrmsr(MC_CF07_DATA, msr);
+	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) \
+		== ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))){
+		print_debug("No memory in the system\r\n");
+		POST_CODE(ERROR_NO_DIMMS);
+		__asm__ __volatile__("hlt\n");
+	}
+
+	/*	Set CKEs */
+	msrnum = MC_CFCLK_DBUG;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
+	wrmsr(msrnum, msr);
+
+
+	/* Force Precharge All on next command, EMRS */
+	msrnum = MC_CFCLK_DBUG;
+	msr = rdmsr(msrnum);
+	msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
+	wrmsr(msrnum,msr);
+
+
+	/* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
+	msrnum =  MC_CF07_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;
+	wrmsr(msrnum, msr);
+	msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
+	wrmsr(msrnum, msr);
+
+
+	/* Clear Force Precharge All */
+	msrnum = MC_CFCLK_DBUG;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
+	wrmsr(msrnum, msr);
+
+
+	/* MRS Reset DLL - set */
+	msrnum = MC_CF07_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;
+	wrmsr(msrnum,msr);
+	msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
+	wrmsr(msrnum, msr);
+
+
+	/* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */
+	/* Wait 2 PORT61 ticks. between 15us and 30us */
+	/* This would be endless if the timer is stuck. */
+	while ((inb(0x61)));  /* find the first edge */
+	while (!(~inb(0x61)));
+
+
+	/* Force Precharge All on the next command, auto-refresh */
+	msrnum = MC_CFCLK_DBUG;
+	msr = rdmsr(msrnum);
+	msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
+	wrmsr(msrnum, msr);
+
+
+	/* Manually AUTO refresh #1 */
+	/* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */
+	msrnum = MC_CF07_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo |= CF07_LOWER_REF_TEST_SET;
+	wrmsr(msrnum, msr);
+	msr.lo &= ~CF07_LOWER_REF_TEST_SET;
+	wrmsr(msrnum, msr);
+
+	/* Clear Force Precharge All */
+	msrnum = MC_CFCLK_DBUG;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
+	wrmsr(msrnum, msr);
+
+
+	/* Manually AUTO refresh */
+	/* The MC should insert the right delay between the refreshes */
+	msrnum = MC_CF07_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo |= CF07_LOWER_REF_TEST_SET;
+	wrmsr(msrnum, msr);
+	msr.lo &= ~CF07_LOWER_REF_TEST_SET;
+	wrmsr(msrnum, msr);
+
+
+	/* MRS Reset DLL - clear */
+	msrnum = MC_CF07_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo |= CF07_LOWER_PROG_DRAM_SET;
+	wrmsr(msrnum, msr);
+	msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
+	wrmsr(msrnum, msr);
+
+
+	/* Allow MC to tristate during idle cycles with MTEST OFF */
+	msrnum = MC_CFCLK_DBUG;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
+	wrmsr(msrnum, msr);

-	//Delay
-	i=inb(0x61);
-	while (i==inb(0x61));
-	i=inb(0x61);
-	while (i==inb(0x61));
-	i=inb(0x61);
-	while (i==inb(0x61));

-	/* 8. load Mode Register by set and clear PROG_DRAM */
+	/* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */
    msr = rdmsr(MC_CF07_DATA);
-	msr.lo |=  0x01;
-	wrmsr(MC_CF07_DATA, msr);
-	msr.lo &= ~0x01;
-	wrmsr(MC_CF07_DATA, msr);
+	if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) == (7 << CF07_UPPER_D1_PSZ_SHIFT)){
+		msrnum = GLCP_DELAY_CONTROLS;
+		msr = rdmsr(msrnum);
+		msr.hi |= (1 << 23);	/* SDCLK bit for 2.0 */
+		wrmsr(msrnum, msr);
+	}

-	/* wait 200 SDCLKs */
-	for (i = 0; i < 200; i++)
-		outb(0xaa, 0x80);
+	/* Set PMode0 Sensitivity Counter */
+	msr.lo = 0;			/* pmode 0=0 most aggressive */
+	msr.hi = 0x200;		/* pmode 1=200h */
+	wrmsr(MC_CF_PMCTR, msr);

-	print_debug("DRAM controller init done.\r\n");

-	/* Fixes from Jordan Crouse of AMD. */
+	/* Set PMode1 Up delay enable */
+	msrnum = MC_CF1017_DATA;
+	msr = rdmsr(msrnum);
+	msr.lo |= (209 << 8);	/* bits[15:8] = 209 */
+	wrmsr(msrnum, msr);
+
+	print_debug("DRAM controller init done.\r\n");
+	POST_CODE(POST_MEM_SETUP_GOOD);		//0x7E

/* make sure there is nothing stale in the cache */
-	__asm__("wbinvd\n");
+	/* CAR stack is in the cache __asm__ __volatile__("wbinvd\n");*/

-	print_debug("RAM DLL lock\r\n");
    /* The RAM dll needs a write to lock on so generate a few dummy writes */
+	/* Note: The descriptor needs to be enabled to point at memory */
    volatile unsigned long *ptr;
    for (i=0;i<5;i++) {
    	ptr = (void *)i;
    	*ptr = (unsigned long)i;
    }
+	/* SWAPSiF for PBZ 4112 (Errata 34) */
+	/* check for failed DLL settings now that we have done a memory write. */
+	msrnum = GLCP_DELAY_CONTROLS;
+	msr = rdmsr(msrnum);
+	if ((msr.lo & 0x7FF) == 0x104) {
+
+		/* If you had it you would need to clear out the fail boot count flag */
+		/*	 (depending on where it counts from etc).*/
+
+		/* The reset we are about to perform clears the PM_SSC register in the */
+		/*	 5536 so will need to store the S3 resume flag in NVRAM otherwise */
+		/*	 it would do a normal boot */
+
+		/* Reset the system */
+		msrnum = MDD_SOFT_RESET;
+		msr = rdmsr(msrnum);
+		msr.lo |= 1;
+		wrmsr(msrnum, msr);
+	}
+	print_debug("RAM DLL lock\r\n");
+

}
Index: LinuxBIOSv2/src/northbridge/amd/lx/chipsetinit.c
===================================================================
--- LinuxBIOSv2.orig/src/northbridge/amd/lx/chipsetinit.c	2007-05-01 14:37:02.000000000 -0600
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,384 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <bitops.h>
-#include "chip.h"
-#include "northbridge.h"
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-
-
-/* the structs in this file only set msr.lo. But ... that may not always be true */
-
-struct msrinit {
-	unsigned long msrnum;
-	msr_t msr;
-};
-
-/*  Master Configuration Register for Bus Masters.*/
-struct msrinit SB_MASTER_CONF_TABLE[] = {
-	{USB1_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000}},	/*  NOTE: Must be 1st entry in table*/
-	{USB2_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000}},
-	{ATA_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00048f000}},
-	{AC97_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000}},
-	{MDD_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00000f000}},
-/* GLPCI_SB_GLD_MSR_CONF,	0x0FFFFFFFF*/
-/* GLCP_SB_GLD_MSR_CONF,	0x0FFFFFFFF*/
-/* GLIU_SB_GLD_MSR_CONF,	0x0*/
-	{0,{0,0}}
-};
-
-/*  5535_A3 Clock Gating*/
-struct msrinit CS5535_CLOCK_GATING_TABLE[] = {
-	{      USB1_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
-	{      USB2_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
-	{      GLIU_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
-	{      GLPCI_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
-	{      GLCP_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
-	{      MDD_SB_GLD_MSR_PM,	{.hi=0,.lo=0x050554111}},
-	{      ATA_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
-	{	AC97_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
-	{0,{0,0}}
-};
-
-/*  5536 Clock Gating*/
-struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
-/* MSR		  Setting*/
-	{      GLIU_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
-	{      GLPCI_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
-	{      GLCP_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
-	{      MDD_SB_GLD_MSR_PM,	{.hi=0,.lo=0x050554111}}, /*  SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/
-	{      ATA_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
-	{      AC97_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
-	{0,{0,0}}
-};
-
-struct acpiinit {
-	unsigned short ioreg; 
-	unsigned long regdata;
-	unsigned short iolen;
-};
-
-struct acpiinit acpi_init_table[] = {
-	{ACPI_BASE+0x00, 0x01000000, 4},
-	{ACPI_BASE+0x08, 0, 4},
-	{ACPI_BASE+0x0C, 0, 4},
-	{ACPI_BASE+0x1C, 0, 4},
-	{ACPI_BASE+0x18, 0x0FFFFFFFF, 4},
-	{ACPI_BASE+0x00, 0x0000FFFF, 4},
-
-	{PM_SCLK, 0x000000E00, 4},
-	{PM_SED,  0x000004601, 4},
-	{PM_SIDD, 0x000008C02, 4},
-	{PM_WKD,  0x0000000A0, 4},
-	{PM_WKXD, 0x0000000A0, 4},
-	{0,0,0}
-};
-
-/* return 1 if we are a 5536-based system */
-static int is_5536(void){
-	msr_t msr;
-	msr = rdmsr(GLIU_SB_GLD_MSR_CAP);
-	msr.lo >>= 20;
-	printk_debug("is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
-	return ((msr.lo&0xf) == 5);
-}
-/* ***************************************************************************/
-/* **/
-/* *	pmChipsetInit*/
-/* **/
-/* *	Program ACPI LBAR and initialize ACPI registers.*/
-/* *  */
-/* **/
-/* *	Entry:*/
-/* *		None*/
-/* **/
-/* *	Exit:*/
-/* *		None*/
-/* **/
-/* *	Destroys:*/
-/* *		None*/
-/* **/
-/* ***************************************************************************/
-static void
-pmChipsetInit(void) {
-	unsigned long val = 0;
-	unsigned short port;
-
-	port =  (PMLogic_BASE + 0x010);
-	val =  0x0E00		; /*  1ms*/
-	outl(val, port);
-
-	/*  PM_WKXD*/
-	/*  Make sure bits[3:0]=0000b to clear the*/
-	/*  saved Sx state*/
-	port =  (PMLogic_BASE + 0x034);
-	val =  0x0A0		; /*  5ms*/
-	outl(val, port);
-	
-	/*  PM_WKD*/
-	port =  (PMLogic_BASE + 0x030);
-	outl(val, port);
-		
-	/*  PM_SED*/
-	port =  (PMLogic_BASE + 0x014);
-/* 	mov		eax, 0x057642	; 100ms, works*/
-	val =  0x04601		; /*  5ms*/
-	outl(val, port);
-	
-	/*  PM_SIDD*/
-	port =  (PMLogic_BASE + 0x020);
-/* 	mov		eax, 0x0AEC84	; 200ms, works*/
-	val =  0x08C02		; /*  10ms*/
-	outl(val, port);
-	
-	/*  GPIO24 OUT_AUX1 function is the external signal for 5535's vsb_working_aux*/
-	/*  which is de-asserted when 5535 enters Standby(S3 or S5) state.*/
-	/*  On Hawk, GPIO24 controls all voltage rails except Vmem and Vstandby.  This means*/
-	/*  GX2 will be fully de-powered if this control de-asserts in S3/S5.*/
-	/* */
-	/*  GPIO24 is setup in preChipsetInit for two reasons*/
-	/*  1. GPIO24 at reset defaults to disabled, since this signal is vsb_work_aux on*/
-	/*     Hawk it controls the FET's for all voltage rails except Vstanby & Vmem.*/
-	/*     BIOS needs to enable GPIO24 as OUT_AUX1 & OUTPUT_EN early so it is driven*/
-	/*     by 5535.*/
-	/*  2. Non-PM builds will require GPIO24 enabled for instant-off power button*/
-	/* */
-
-	/*  GPIO11 OUT_AUX1 function is the external signal for 5535's slp_clk_n which is asserted*/
-	/*  when 5535 enters Sleep(S1) state.*/
-	/*  On Hawk, GPIO11 is connected to control input of external clock generator*/
-	/*  for 14MHz, PCI, USB & LPC clocks.*/
-	/*  Programming of GPIO11 will be done by VSA PM code.  During VSA Init. BIOS writes*/
-	/*  PM Core Virual Register indicating if S1 Clocks should be On or Off. This is based*/
-	/*  on a Setup item.  We do not want to leave GPIO11 enabled because of a Hawk board*/
-	/*  problem.  With GPIO11 enabled in S3, something is back-driving GPIO11 causing it to*/
-	/*  float to 1.6-1.7V.*/
-
-}
-
-struct FLASH_DEVICE {
-	unsigned char fType;		/* Flash type: NOR or NAND */
-	unsigned char fInterface;	/* Flash interface: I/O or Memory */
-	unsigned long fMask;		/* Flash size/mask */
-};
-
-struct FLASH_DEVICE FlashInitTable[] = {
-	{ FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K },	/* CS0, or Flash Device 0 */
-	{ FLASH_TYPE_NONE, 0, 0 },	/* CS1, or Flash Device 1 */
-	{ FLASH_TYPE_NONE, 0, 0 },	/* CS2, or Flash Device 2 */
-	{ FLASH_TYPE_NONE, 0, 0 },	/* CS3, or Flash Device 3 */
-};
-
-#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
-
-uint32_t FlashPort[] = {
-	MDD_LBAR_FLSH0,
-	MDD_LBAR_FLSH1,
-	MDD_LBAR_FLSH2,
-	MDD_LBAR_FLSH3
-	};
-
-/***************************************************************************
- *
- *	ChipsetFlashSetup
- *
- *	Flash LBARs need to be setup before VSA init so the PCI BARs have
- *	correct size info.  Call this routine only if flash needs to be 
- *	configured (don't call it if you want IDE).
- *
- *	Entry:
- *	Exit:
- *	Destroys:
- *
- **************************************************************************/
-static void ChipsetFlashSetup(void)
-{
-	msr_t msr;
-	int i;
-	int numEnabled = 0;
-
-	printk_debug("ChipsetFlashSetup++\n");
-	for (i = 0; i < FlashInitTableLen; i++) {
-		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
-			printk_debug("Enable CS%d\n", i);
-			/* we need to configure the memory/IO mask */
-			msr = rdmsr(FlashPort[i]);
-			msr.hi = 0;	/* start with the "enabled" bit clear */
-			if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
-				msr.hi |= 0x00000002;
-			else
-				msr.hi &= ~0x00000002;
-			if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
-				msr.hi |= 0x00000004;
-			else
-				msr.hi &= ~0x00000004;
-			msr.hi |= FlashInitTable[i].fMask;
-			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
-			wrmsr(FlashPort[i], msr);
-
-			/* now write-enable the device */
-			msr = rdmsr(MDD_NORF_CNTRL);
-			msr.lo |= (1 << i);
-			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
-			wrmsr(MDD_NORF_CNTRL, msr);
-
-			/* update the number enabled */
-			numEnabled++;
-		}
-	}
-
-	/* enable the flash */
-	if (0 != numEnabled) {
-		msr = rdmsr(MDD_PIN_OPT);
-		msr.lo &= ~1; /* PIN_OPT_IDE */
-		printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
-		wrmsr(MDD_PIN_OPT, msr);
-	}
-	printk_debug("ChipsetFlashSetup--\n");
-
-}
-
-
- 
-/* ***************************************************************************/
-/* **/
-/* *	ChipsetGeodeLinkInit*/
-/* *	Handle chipset specific GeodeLink settings here. */
-/* *	Called from GeodeLink init code.*/
-/* **/
-/* *	Entry:*/
-/* *	Exit:*/
-/* *	Destroys: GS*/
-/* **/
-/* ***************************************************************************/
-static void 
-ChipsetGeodeLinkInit(void){
-	msr_t msr;
-	unsigned long msrnum;
-	unsigned long totalmem;
-
-	if (is_5536())
-		return;
-	/*  SWASIF for A1 DMA */
-	/*  Set all memory to  "just above systop" PCI so DMA will work*/
-	/*  check A1*/
-	msrnum = MSR_SB_GLCP + 0x17;
-	msr = rdmsr(msrnum);
-	if ((msr.lo&0xff) == 0x11)
-		return;
-
-	totalmem = (sizeram() << 20) - 1;
-	totalmem >>= 12; 
-	totalmem = ~totalmem;
-	totalmem &= 0xfffff;
-	msr.lo = totalmem;
-	msr.hi = 0x20000000;				/*  Port 1 (PCI)*/
-	msrnum = MSR_SB_GLIU + 0x20;		/*  */;
-	wrmsr(msrnum, msr);
-}
-
-void
-chipsetinit (struct northbridge_amd_lx_config *nb){
-	msr_t msr;
-	struct msrinit *csi;
-	int i;
-	unsigned long msrnum;
-
-	outb( P80_CHIPSET_INIT, 0x80);
-	ChipsetGeodeLinkInit();
-#if 0
-	/* we hope NEVER to be in linuxbios when S3 resumes 
-	if (! IsS3Resume()) */
-	{
-		struct acpiinit *aci = acpi_init_table;
-		while (aci->ioreg){
-			if (aci->iolen == 2) {
-				outw(aci->regdata, aci->ioreg);
-				inw(aci->ioreg);
-			} else {
-				outl(aci->regdata, aci->ioreg);
-				inl(aci->ioreg);
-			}
-		}
-
-		pmChipsetInit();
-	}
-#endif
-
-
-	if (!is_5536()) {
-		/*  Setup USB. Need more details. #118.18*/
-		msrnum = MSR_SB_USB1 + 8;
-		msr.lo =  0x00012090;
-		msr.hi = 0;
-		wrmsr(msrnum, msr);
-		msrnum = MSR_SB_USB2 + 8;
-		wrmsr(msrnum, msr);
-	}
-	
-	/* set hd IRQ */
-	outl	(GPIOL_2_SET, GPIOL_INPUT_ENABLE);
-	outl	(GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
-
-	/*  Allow IO read and writes during a ATA DMA operation.*/
-	/*   This could be done in the HD rom but do it here for easier debugging.*/
-	
-	msrnum = ATA_SB_GLD_MSR_ERR;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~0x100;
-	wrmsr(msrnum, msr);
-
-	/*  Enable Post Primary IDE.*/
-	msrnum = GLPCI_SB_CTRL;
-	msr = rdmsr(msrnum);
-	msr.lo |=  GLPCI_CRTL_PPIDE_SET;
-	wrmsr(msrnum, msr);
-
-
-	/*  Set up Master Configuration Register*/
-	/*  If 5536, use same master config settings as 5535, except for OHCI MSRs*/
-	if (is_5536()) 
-		i = 2;
-	else
-		i = 0;
-
-	csi = &SB_MASTER_CONF_TABLE[i];
-	for(; csi->msrnum; csi++){
-		msr.lo = csi->msr.lo;
-		msr.hi = csi->msr.hi;
-		wrmsr(csi->msrnum, msr); // MSR - see table above
-	}
-
-
-	/*  Flash Setup*/
-	printk_err("%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT");
-	if (nb->setupflash)
-		ChipsetFlashSetup();
-
-
-
-	/* */
-	/*  Set up Hardware Clock Gating*/
-	/* */
-	/* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */
-	{
-		if (is_5536())
-			csi = CS5536_CLOCK_GATING_TABLE;
-		else
-			csi = CS5535_CLOCK_GATING_TABLE;
-
-		for(; csi->msrnum; csi++){
-			msr.lo = csi->msr.lo;
-			msr.hi = csi->msr.hi;
-			wrmsr(csi->msrnum, msr);	// MSR - see table above
-		}
-	}
-
-}

[LinuxBIOS] [patch 4/4] AMD Geode GX/LX: CS5536 Southbridge

[Marc Jones]

This patch re-impelments support for the CS5536 companion chip for the
AMD GX and LX processors.   This aguments the previous code, which was
very specific to the OLPC platform with general purpose support and 
better integration with the VSA and CPUs.

Signed-off-by: Marc Jones 
Index: LinuxBIOSv2/src/include/device/pci_ids.h
===================================================================
--- LinuxBIOSv2.orig/src/include/device/pci_ids.h	2007-04-30 15:14:24.000000000 -0600
+++ LinuxBIOSv2/src/include/device/pci_ids.h	2007-04-30 15:14:24.000000000 -0600
@@ -452,12 +452,13 @@
 #define PCI_DEVICE_ID_AMD_AES		0x2082
 #define PCI_DEVICE_ID_AMD_CS5536_ISA	0x2090
 #define PCI_DEVICE_ID_AMD_CS5536_FLASH	0x2091
-#define PCI_DEVICE_ID_AMD_CS5536_IDE	0x2092
+#define PCI_DEVICE_ID_AMD_CS5536_IDE_OLD	0x2092
 #define PCI_DEVICE_ID_AMD_CS5536_AUDIO	0x2093
 #define PCI_DEVICE_ID_AMD_CS5536_OHCI	0x2094
 #define PCI_DEVICE_ID_AMD_CS5536_EHCI	0x2095
 #define PCI_DEVICE_ID_AMD_CS5536_UDC	0x2096
 #define PCI_DEVICE_ID_AMD_CS5536_OTG	0x2097
+#define PCI_DEVICE_ID_AMD_CS5536_IDE	0x209A

#define PCI_VENDOR_ID_TRIDENT		0x1023
 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/Config.lb
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/Config.lb	2007-04-30 15:14:24.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/amd/cs5536/Config.lb	2007-04-30 15:14:24.000000000 -0600
@@ -1,4 +1,22 @@
+#/*
+#* This file is part of the LinuxBIOS project.
+#*
+#*
+#* This program is free software; you can redistribute it and/or modify
+#* it under the terms of the GNU General Public License version 2 as
+#* published by the Free Software Foundation.
+#*
+#* This program is distributed in the hope that it will be useful,
+#* but WITHOUT ANY WARRANTY; without even the implied warranty of
+#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#* GNU General Public License for more details.
+#*
+#* You should have received a copy of the GNU General Public License
+#* along with this program; if not, write to the Free Software
+#* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#*/
+
+
 config chip.h
 driver cs5536.o
-#driver cs5536_pci.o
-#driver cs5536_ide.o
+driver cs5536_ide.o
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/chip.h	2007-04-30 15:14:23.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h	2007-04-30 15:14:23.000000000 -0600
@@ -1,28 +1,32 @@
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
+
 #ifndef _SOUTHBRIDGE_AMD_CS5536
 #define _SOUTHBRIDGE_AMD_CS5536

-#define MAX_UNWANTED_VPCI 10	/* increase if needed */
+#define MAX_UNWANTED_VPCI 8		/* increase if needed */

extern struct chip_operations southbridge_amd_cs5536_ops;

struct southbridge_amd_cs5536_config {
-	/* interrupt enable for LPC bus */
-	int lpc_serirq_enable;	/* how to enable, e.g. 0x80 */
- 	int lpc_irq;		/* what to enable, e.g. 0x18 */
- 	int enable_gpio0_inta; 	/* almost always will be true */
-	int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */
-	int enable_uarta; 		/* internal uarta interrupt enable */
-	int enable_USBP4_host;	/* Enable USB Port 4 as a host */
-	/* following are IRQ numbers for various southbridge resources. */
-	/* I have guessed at some things, as I still don't have an lspci from anyone */
-	int ide_irq;		/* f.2 */
-	int audio_irq; 		/* f.3 */
-	int usbf4_irq;		/* f.4 */
-	int usbf5_irq;		/* f.5 */
-	int usbf6_irq;		/* f.6 */
-	int usbf7_irq; 		/* f.7 */
-	/* the following allow you to disable unwanted virtualized PCI devices */
-	unsigned long unwanted_vpci[MAX_UNWANTED_VPCI];
+	unsigned int lpc_serirq_enable;			/* interrupt enables for LPC bus; each bit is an irq 0-15 */
+	unsigned int lpc_serirq_polarity;		/* LPC IRQ polarity; each bit is an irq 0-15 */
+	unsigned char lpc_serirq_mode;			/* 0:Continuous 1:Quiet */
+	unsigned int enable_gpio_int_route;		/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
+	unsigned char enable_ide_nand_flash;	/* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */
+	unsigned char enable_USBP4_device;		/* Enable USB Port 4 0:host 1:device */
+	unsigned int enable_USBP4_overcurrent;	/* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */
+	unsigned char com1_enable;				/* enable COM1 */
+	unsigned int com1_address;				/* e.g. 0x3F8 */
+	unsigned int com1_irq;					/* e.g. 4 */
+	unsigned char com2_enable;				/* enable COM2 */
+	unsigned int com2_address;				/* e.g. 0x2F8 */
+	unsigned int com2_irq;					/* e.g. 3 */
+	unsigned int unwanted_vpci[MAX_UNWANTED_VPCI];	/* the following allow you to disable unwanted virtualized PCI devices */
+
 };

#endif	/* _SOUTHBRIDGE_AMD_CS5536 */
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536.c	2007-04-30 15:14:24.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2007-04-30 15:14:24.000000000 -0600
@@ -1,3 +1,21 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	 02110-1301 USA
+*/

#include <arch/io.h>
 #include <device/device.h>
@@ -5,167 +23,575 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include <cpu/amd/gx2def.h>
+#include <stdint.h>
+#include <pc80/isa-dma.h>
+#include <pc80/mc146818rtc.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/vr.h>
+#include <cpu/amd/geode_post_code.h>
 #include "chip.h"
+#include "cs5536.h"

+extern void setup_i8259(void);

-#define PIN_OPT_IDE		(1ULL<<0)	/* 0 for flash, 1 for IDE */
+struct msrinit {
+	uint32_t msrnum;
+	msr_t msr;
+};
+
+/*	Master Configuration Register for Bus Masters.*/
+struct msrinit SB_MASTER_CONF_TABLE[] = {
+	{USB2_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000}},
+	{ATA_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00048f000}},
+	{AC97_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000}},
+	{MDD_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00000f000}},
+	{0,{0,0}}
+};
+
+/*	5536 Clock Gating*/
+struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
+/* MSR		  Setting*/
+	{GLIU_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
+	{GLPCI_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{GLCP_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
+	{MDD_SB_GLD_MSR_PM,		{.hi=0,.lo=0x050554111}}, /*  SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/
+	{ATA_SB_GLD_MSR_PM,		{.hi=0,.lo=0x000000005}},
+	{AC97_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{0,{0,0}}
+};
+
+struct acpiinit {
+	uint16_t ioreg;
+	uint32_t regdata;
+};

-/* Intended value for LBAR_FLSH0: 4KiB, enabled, MMIO, NAND, @0x20000000 */
-/* NOTE: no longer used, prune at some point */
-/* OOPS: steve's changes don't work, so we have to keep this */
-msr_t flsh0 = { .hi=0xFFFFF007, .lo=0x20000000};
+struct acpiinit acpi_init_table[] = {
+	{ACPI_IO_BASE + 0x00, 0x01000000},
+	{ACPI_IO_BASE + 0x08, 0},
+	{ACPI_IO_BASE + 0x0C, 0},
+	{ACPI_IO_BASE + 0x1C, 0},
+	{ACPI_IO_BASE + 0x18, 0x0FFFFFFFF},
+	{ACPI_IO_BASE + 0x00, 0x0000FFFF},
+	{PMS_IO_BASE + PM_SCLK, 0x000000E00},
+	{PMS_IO_BASE + PM_SED,	0x000004601},
+	{PMS_IO_BASE + PM_SIDD, 0x000008C02},
+	{PMS_IO_BASE + PM_WKD,	0x0000000A0},
+	{PMS_IO_BASE + PM_WKXD, 0x0000000A0},
+	{0,0,0}
+};
+
+struct FLASH_DEVICE {
+	unsigned char fType;		/* Flash type: NOR or NAND */
+	unsigned char fInterface;	/* Flash interface: I/O or Memory */
+	unsigned long fMask;		/* Flash size/mask */
+};
+
+struct FLASH_DEVICE FlashInitTable[] = {
+	{ FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K },	/* CS0, or Flash Device 0 */
+	{ FLASH_TYPE_NONE, 0, 0 },	/* CS1, or Flash Device 1 */
+	{ FLASH_TYPE_NONE, 0, 0 },	/* CS2, or Flash Device 2 */
+	{ FLASH_TYPE_NONE, 0, 0 },	/* CS3, or Flash Device 3 */
+};
+
+#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
+
+uint32_t FlashPort[] = {
+	MDD_LBAR_FLSH0,
+	MDD_LBAR_FLSH1,
+	MDD_LBAR_FLSH2,
+	MDD_LBAR_FLSH3
+	};
+
+
+/* ***************************************************************************/
+/* **/
+/* *	pmChipsetInit*/
+/* **/
+/* *	Program ACPI LBAR and initialize ACPI registers.*/
+/* **/
+/* ***************************************************************************/
+static void pmChipsetInit(void) {
+	uint32_t val = 0;
+	uint16_t port;
+
+	port =	(PMS_IO_BASE + 0x010);
+	val =  0x0E00		; /*  1ms*/
+	outl(val, port);
+
+	/*	PM_WKXD*/
+	/*	Make sure bits[3:0]=0000b to clear the*/
+	/*	saved Sx state*/
+	port =	(PMS_IO_BASE + 0x034);
+	val =  0x0A0		; /*  5ms*/
+	outl(val, port);
+
+	/*	PM_WKD*/
+	port =	(PMS_IO_BASE + 0x030);
+	outl(val, port);
+
+	/*	PM_SED*/
+	port =	(PMS_IO_BASE + 0x014);
+/*	mov		eax, 0x057642	; 100ms, works*/
+	val =  0x04601		; /*  5ms*/
+	outl(val, port);
+
+	/*	PM_SIDD*/
+	port =	(PMS_IO_BASE + 0x020);
+/*	mov		eax, 0x0AEC84	; 200ms, works*/
+	val =  0x08C02		; /*  10ms*/
+	outl(val, port);
+}

-static void
-enable_ide_nand_flash(){
+
+/***************************************************************************
+ *
+ *	ChipsetFlashSetup
+ *
+ *	Flash LBARs need to be setup before VSA init so the PCI BARs have
+ *	correct size info.	Call this routine only if flash needs to be
+ *	configured (don't call it if you want IDE).
+ *
+ **************************************************************************/
+static void ChipsetFlashSetup(void){
    msr_t msr;
-	printk_err("cs5536: %s\n", __FUNCTION__);
-#if 1
-	printk_err("WARNING: using deprecated flash enable mechanism\n");
-	/* steve took this one out ... not sure if needed or not */
-	msr = rdmsr(MDD_LBAR_FLSH0);
-
-	if ( ((msr.hi) & 7) != 7) {
-		printk_err("MDD_LBAR_FLSH0 was 0x%08x%08x\n", msr.hi,msr.lo);
-		wrmsr(MDD_LBAR_FLSH0, flsh0);
-	}
-	msr = rdmsr(MDD_LBAR_FLSH0);
-	printk_err("MDD_LBAR_FLSH0 is 0x%08x%08x\n", msr.hi,msr.lo);
-#endif
-	msr = rdmsr(MDD_PIN_OPT);
-	if (msr.lo & PIN_OPT_IDE) {
-		printk_err("MDD_PIN_OPT was 0x%08x%08x\n", msr.hi,msr.lo);
-		msr.lo &= ~PIN_OPT_IDE;
-		wrmsr(MDD_PIN_OPT, msr);
-	}
-	msr = rdmsr(MDD_PIN_OPT);
-	printk_err("MDD_PIN_OPT is 0x%08x%08x\n", msr.hi,msr.lo);
-
-	msr = rdmsr(MDD_NANDF_DATA);
-	if (msr.lo != 0x00100010) {
-		printk_err("MDD_NANDF_DATA was 0x%08x%08x\n", msr.hi,msr.lo);
-		msr.lo = 0x00100010;
-		wrmsr(MDD_NANDF_DATA, msr);
-	}
-	msr = rdmsr(MDD_NANDF_DATA);
-	printk_err("MDD_NANDF_DATA is 0x%08x%08x\n", msr.hi,msr.lo);
-
-	msr = rdmsr(MDD_NADF_CNTL);
-	if (msr.lo != 0x0010) {
-		printk_err("MDD_NADF_CNTL was 0x%08x%08x\n", msr.hi,msr.lo);
-		msr.lo = 0x0010;
-		wrmsr(MDD_NADF_CNTL, msr);
-	}
-	msr = rdmsr(MDD_NADF_CNTL);
-	printk_err("MDD_NADF_CNTL is 0x%08x%08x\n", msr.hi,msr.lo);
-	printk_err("cs5536: EXIT %s\n", __FUNCTION__);
-}
-
-#if 0
-/* note: this is a candidate for inclusion in src/devices/pci_device.c */
-void
-setup_irq(unsigned irq, char *name, unsigned level, unsigned bus, unsigned device, unsigned fn){
-	if (irq)  {
-		unsigned devfn = PCI_DEVFN(device,fn);
-		device_t dev  = dev_find_slot(bus, devfn);
-		if (dev) {
-			pci_write_config8(dev, PCI_INTERRUPT_LINE, irq);
-			if (level)
-				pci_level_irq(irq);
+	int i;
+	int numEnabled = 0;
+
+	printk_debug("ChipsetFlashSetup: Start\n");
+	for (i = 0; i < FlashInitTableLen; i++) {
+		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
+			printk_debug("Enable CS%d\n", i);
+			/* we need to configure the memory/IO mask */
+			msr = rdmsr(FlashPort[i]);
+			msr.hi = 0;	/* start with the "enabled" bit clear */
+			if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
+				msr.hi |= 0x00000002;
+			else
+				msr.hi &= ~0x00000002;
+			if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
+				msr.hi |= 0x00000004;
+			else
+				msr.hi &= ~0x00000004;
+			msr.hi |= FlashInitTable[i].fMask;
+			printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
+			wrmsr(FlashPort[i], msr);
+
+			/* now write-enable the device */
+			msr = rdmsr(MDD_NORF_CNTRL);
+			msr.lo |= (1 << i);
+			printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
+			wrmsr(MDD_NORF_CNTRL, msr);
+
+			/* update the number enabled */
+			numEnabled++;
    	}
-		else
-			printk_err("%s: Can't find %s at 0x%x\n", __FUNCTION__, name, devfn);
    }
+
+	printk_debug("ChipsetFlashSetup: Finish\n");
+
+}
+/* ***************************************************************************/
+/* **/
+/* *	enable_ide_nand_flash_header */
+/*		Run after VSA init to enable the flash PCI device header */
+/* **/
+/* ***************************************************************************/
+static void enable_ide_nand_flash_header(){
+	/* Tell VSA to use FLASH PCI header. Not IDE header.*/
+	outl(0x80007A40, 0xCF8);
+	outl(0xDEADBEEF, 0xCFC);
 }
-#endif

-static void southbridge_init(struct device *dev)
-{
-	struct southbridge_amd_cs5536_config  *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
-	const unsigned char slots_cpu[4] = {11, 0, 0, 0};
-	const unsigned char slots_sb[4] = {11, 5, 10, 10};
- 	msr_t msr;
-	int i;
-	/*
-	 * struct device *gpiodev;
-	 * unsigned short gpiobase = MDD_GPIO;
-	 */

-	printk_err("cs5536: %s\n", __FUNCTION__);
-	setup_i8259(); 
+#define RTC_CENTURY 0x32
+#define RTC_DOMA	0x3D
+#define RTC_MONA	0x3E
+
+static void lpc_init(struct southbridge_amd_cs5536_config *sb){
+	msr_t msr;

if (sb->lpc_serirq_enable) {
    	msr.lo = sb->lpc_serirq_enable;
-		msr.hi  = 0;
-		wrmsr(MDD_LPC_SIRQ, msr);
-	}
-	if (sb->lpc_irq) {
-		msr.lo = sb->lpc_irq;
    	msr.hi = 0;
    	wrmsr(MDD_IRQM_LPC, msr);
+		if (sb->lpc_serirq_polarity) {
+			msr.lo = sb->lpc_serirq_polarity << 16;
+			msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */
+			msr.hi = 0;
+			wrmsr(MDD_LPC_SIRQ, msr);
+		}
    }

-	if (sb->enable_gpio0_inta){
-	  msr = rdmsr(MDD_IRQM_ZHIGH);
-		msr.lo |= 0x10;
-		wrmsr(MDD_IRQM_ZHIGH, msr);
-		/* todo: look the device up. But we know that gpiobase is 0x6100 */
-		/* oh gosh, all the defines from AMD assume 6100. Don't bother looking up! */
-		outl(GPIOL_0_SET|GPIOL_1_SET|GPIOL_3_SET, GPIOL_INPUT_ENABLE);
-		outl(GPIOL_0_SET,GPIOL_EVENTS_ENABLE);
-		/* magic stuff */
-		outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
-		outl(GPIOL_0_SET, GPIO_MAPPER_X);
-	}
-
-	if (sb->enable_uarta){
-		printk_err("cs5536: %s: enable uarta, msr MDD_IRQM_YHIGH(%x) \n",
-				 __FUNCTION__, MDD_IRQM_YHIGH);
+	/* Allow DMA from LPC */
+	msr = rdmsr(MDD_DMA_MAP);
+	msr.lo = 0x7777;
+	wrmsr(MDD_DMA_MAP, msr);
+
+	/* enable the RTC/CMOS century byte at address 32h */
+	msr = rdmsr(MDD_RTC_CENTURY_OFFSET);
+	msr.lo = RTC_CENTURY;
+	wrmsr(MDD_RTC_CENTURY_OFFSET, msr);
+
+	/* enable the RTC/CMOS day of month and month alarms */
+	msr = rdmsr(MDD_RTC_DOMA_IND);
+	msr.lo = RTC_DOMA;
+	wrmsr(MDD_RTC_DOMA_IND, msr);
+
+	msr = rdmsr(MDD_RTC_MONA_IND);
+	msr.lo = RTC_MONA;
+	wrmsr(MDD_RTC_MONA_IND, msr);
+
+	rtc_init(0);
+
+	isa_dma_init();
+}
+
+
+static void uarts_init(struct southbridge_amd_cs5536_config *sb){
+	msr_t msr;
+	uint16_t addr;
+	uint32_t gpio_addr;
+	device_t dev;
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+	gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
+	gpio_addr &= ~1; /* clear IO bit */
+	printk_debug("GPIO_ADDR: %08X\n", gpio_addr);
+
+	/* This could be extended to support IR modes */
+
+	/* COM1 */
+	if (sb->com1_enable){
+		/* Set the address */
+		switch (sb->com1_address){
+			case 0x3F8:
+			addr = 7;
+			break;
+
+			case 0x3E8:
+			addr = 6;
+			break;
+
+			case 0x2F8:
+			addr = 5;
+			break;
+
+			case 0x2E8:
+			addr = 4;
+			break;
+		}
+		msr = rdmsr(MDD_LEG_IO);
+		msr.lo |= addr << 16;
+		wrmsr(MDD_LEG_IO,msr);
+
+		/* Set the IRQ */
    	msr = rdmsr(MDD_IRQM_YHIGH);
-		msr.lo |= 0x04000000;
+		msr.lo |= sb->com1_irq << 24;
    	wrmsr(MDD_IRQM_YHIGH, msr);
+
+		/* GPIO8 - UART1_TX */
+		/* Set: Output Enable  (0x4) */
+		outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+		/* Set: OUTAUX1 Select (0x10) */
+		outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
+
+		/* GPIO8 - UART1_RX */
+		/* Set: Input Enable   (0x20) */
+		outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+		/* Set: INAUX1 Select  (0x34) */
+		outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
+
+		/* Set: GPIO 8 + 9 Pull Up	   (0x18) */
+		outl(GPIOL_8_SET | GPIOL_9_SET, gpio_addr + GPIOL_PULLUP_ENABLE);
+
+		/* enable COM1 */
+		/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
+		msr.lo = (1 << 4) | (1 << 1);
+		msr.hi = 0;
+		wrmsr(MDD_UART1_CONF, msr);
+
    }
+	else{
+		/* Reset and disable COM1 */
+		msr = rdmsr(MDD_UART1_CONF);
+		msr.lo = 1;					// reset
+		wrmsr(MDD_UART1_CONF, msr);
+		msr.lo = 0;					// disabled
+		wrmsr(MDD_UART1_CONF, msr);
+
+		/* Disable the IRQ */
+		msr = rdmsr(MDD_LEG_IO);
+		msr.lo |= ~(0xF << 16);
+		wrmsr(MDD_LEG_IO,msr);
+	}
+
+	/* COM2 */
+	if (sb->com2_enable){
+		switch (sb->com2_address){
+			case 0x3F8:
+			addr = 7;
+			break;
+
+			case 0x3E8:
+			addr = 6;
+			break;
+
+			case 0x2F8:
+			addr = 5;
+			break;
+
+			case 0x2E8:
+			addr = 4;
+			break;
+		}
+		msr = rdmsr(MDD_LEG_IO);
+		msr.lo |= addr << 20;
+		wrmsr(MDD_LEG_IO,msr);
+
+
+		/* Set the IRQ */
+		msr = rdmsr(MDD_IRQM_YHIGH);
+		msr.lo |= sb->com2_irq << 28;
+		wrmsr(MDD_IRQM_YHIGH, msr);
+
+		/* GPIO3 - UART2_RX */
+		/* Set: Output Enable  (0x4) */
+		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+		/* Set: OUTAUX1 Select (0x10) */
+		outl(GPIOL_3_SET,gpio_addr + GPIOL_OUT_AUX1_SELECT);
+
+		/* GPIO4 - UART2_TX */
+		/* Set: Input Enable   (0x20) */
+		outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+		/* Set: INAUX1 Select  (0x34) */
+		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
+
+		/* Set: GPIO 3 + 3 Pull Up	   (0x18) */
+		outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE);
+
+		/* enable COM2 */
+		/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
+		msr.lo = (1 << 4) | (1 << 1);
+		msr.hi = 0;
+		wrmsr(MDD_UART2_CONF, msr);

-	printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
-	if (sb->enable_ide_nand_flash) {
-		enable_ide_nand_flash();
    }
+	else{
+		/* Reset and disable COM2 */
+		msr = rdmsr(MDD_UART2_CONF);
+		msr.lo = 1;					// reset
+		wrmsr(MDD_UART2_CONF, msr);
+		msr.lo = 0;					// disabled
+		wrmsr(MDD_UART2_CONF, msr);
+
+		/* Disable the IRQ */
+		msr = rdmsr(MDD_LEG_IO);
+		msr.lo |= ~(0xF << 20);
+		wrmsr(MDD_LEG_IO,msr);
+	}
+}
+
+
+
+#define HCCPARAMS		0x08
+#define IPREG04			0xA0
+	#define USB_HCCPW_SET	(1 << 1)
+#define UOCCAP			0x00
+	#define APU_SET			(1 << 15)
+#define UOCMUX			0x04
+	#define PMUX_HOST		0x02
+	#define PMUX_DEVICE		0x03
+	#define PUEN_SET		(1 << 2)
+#define UDCDEVCTL		0x404
+	#define UDC_SD_SET		(1 << 10)
+#define UOCCTL			0x0C
+	#define PADEN_SET		(1 << 7)

-#if 0
- 	/* irq handling */
- 	setup_irq(sb->audio_irq, "audio", 1, 0, 0xf, 2);
- 	setup_irq(sb->usbf4_irq, "usb f4", 1, 0, 0xf, 4);
- 	setup_irq(sb->usbf5_irq, "usb f5", 1, 0, 0xf, 5);
- 	setup_irq(sb->usbf6_irq, "usb f6", 1, 0, 0xf, 6);
- 	setup_irq(sb->usbf7_irq, "usb f7", 1, 0, 0xf, 7);
-#else
-	/* CPU (80000800 = 00.01.00) */
-	pci_assign_irqs(0, 0x01, slots_cpu);	/* bus=0, device=0x01, slots={11,0,0,0} */
- 	
-	/* Southbridge (80007800 = 00.0F.00) */
-	pci_assign_irqs(0, 0x0F, slots_sb);	/* bus=0, device=0x0F, slots={11,5,10,10} */
-#endif
-
-	if (sb->enable_USBP4_host) {
-		unsigned long val;
-		unsigned long uocmux;
-
-		outl(0x80007F10, 0xCF8);
-		outl(0x0EFC00000, 0xCFC);
-
-		uocmux = *((unsigned long *) 0x0EFC00004);
-		uocmux &= ~3;
-		uocmux |= 2;

-		*((unsigned long *) 0x0EFC00004) = uocmux;
+static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
+{
+	uint32_t * bar;
+	msr_t msr;
+	device_t dev;
+
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
+	if(dev){
+
+		/* Serial Short Detect Enable */
+		msr = rdmsr(USB2_SB_GLD_MSR_CONF);
+		msr.hi |= USB2_UPPER_SSDEN_SET;
+		wrmsr(USB2_SB_GLD_MSR_CONF, msr);
+
+		/* write to clear diag register */
+		wrmsr(USB2_SB_GLD_MSR_DIAG,rdmsr(USB2_SB_GLD_MSR_DIAG));
+
+		bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+		/* Make HCCPARAMS writeable */
+		*(bar + IPREG04) |= USB_HCCPW_SET;
+
+		/* ; EECP=50h, IST=01h, ASPC=1 */
+		*(bar + HCCPARAMS) = 0x00005012;
+	}
+
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+	if(dev){
+		bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+		*(bar + UOCMUX) &= PUEN_SET;
+
+		/* Host or Device? */
+		if (sb->enable_USBP4_device) {
+			*(bar + UOCMUX) |= PMUX_DEVICE;
+		}
+		else{
+			*(bar + UOCMUX) |= PMUX_HOST;
+		}
+
+		/* Overcurrent configuration */
+		if (sb->enable_USBP4_overcurrent) {
+			*(bar + UOCCAP) |= sb->enable_USBP4_overcurrent;
+		}
+	}
+
+	/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device,
+	 *	then perform the following sequence:
+	 *
+	 * - set SD bit in DEVCTRL udc register
+	 * - set PADEN (former OTGPADEN) bit in uoc register
+	 * - set APU bit in uoc register */
+	if (sb->enable_USBP4_device) {
+		dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+		if(dev){
+			bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+			*(bar + UDCDEVCTL) |= UDC_SD_SET;
+
+		}
+
+		dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+		if(dev){
+			bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+			*(bar + UOCCTL) |= PADEN_SET;
+			*(bar + UOCCAP) |= APU_SET;
+		}
+	}
+
+	/* Disable virtual PCI UDC and OTG headers */
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+	if(dev){
+		pci_write_config8(dev, 0x7C, 0xDEADBEEF);
+	}
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+	if(dev){
+		pci_write_config8(dev, 0x7C, 0xDEADBEEF);
+	}
+}
+
+/* ***************************************************************************/
+/* **/
+/* *	ChipsetInit */
+/*			Called from northbridge init (Pre-VSA). */
+/* **/
+/* ***************************************************************************/
+void chipsetinit (void){
+	device_t dev;
+	msr_t msr;
+	uint32_t msrnum;
+	struct southbridge_amd_cs5536_config  *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
+	struct msrinit *csi;
+
+	outb( P80_CHIPSET_INIT, 0x80);
+
+	/* we hope NEVER to be in linuxbios when S3 resumes
+	if (! IsS3Resume()) */
+	{
+		struct acpiinit *aci = acpi_init_table;
+		for(; aci->ioreg; aci++) {
+			outl(aci->regdata, aci->ioreg);
+			inl(aci->ioreg);
+		}
+
+		pmChipsetInit();
+	}
+
+
+	/* set hd IRQ */
+	outl( GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	outl( GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+
+	/*	Allow IO read and writes during a ATA DMA operation.*/
+	/*	 This could be done in the HD rom but do it here for easier debugging.*/
+	msrnum = ATA_SB_GLD_MSR_ERR;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~0x100;
+	wrmsr(msrnum, msr);
+
+	/*	Enable Post Primary IDE.*/
+	msrnum = GLPCI_SB_CTRL;
+	msr = rdmsr(msrnum);
+	msr.lo |=  GLPCI_CRTL_PPIDE_SET;
+	wrmsr(msrnum, msr);
+
+
+	csi = SB_MASTER_CONF_TABLE;
+	for(; csi->msrnum; csi++){
+		msr.lo = csi->msr.lo;
+		msr.hi = csi->msr.hi;
+		wrmsr(csi->msrnum, msr); // MSR - see table above
+	}
+
+	/*	Flash BAR size Setup*/
+	printk_err("%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not ");
+	if (sb->enable_ide_nand_flash == 1)
+		ChipsetFlashSetup();
+
+	/* */
+	/*	Set up Hardware Clock Gating*/
+	/* */
+	{
+		csi = CS5536_CLOCK_GATING_TABLE;
+		for(; csi->msrnum; csi++){
+			msr.lo = csi->msr.lo;
+			msr.hi = csi->msr.hi;
+			wrmsr(csi->msrnum, msr);	// MSR - see table above
+		}
+	}
+}
+
+static void southbridge_init(struct device *dev)
+{
+	struct southbridge_amd_cs5536_config  *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
+	int i;
+	/*
+	 * struct device *gpiodev;
+	 * unsigned short gpiobase = MDD_GPIO;
+	 */
+
+	printk_err("cs5536: %s\n", __FUNCTION__);
+	setup_i8259();
+	lpc_init(sb);
+	uarts_init(sb);
+
+	if (sb->enable_gpio_int_route){
+		vrWrite((VRC_MISCELLANEOUS <<  8) + PCI_INT_AB, (sb->enable_gpio_int_route & 0xFFFF));
+		vrWrite((VRC_MISCELLANEOUS <<  8) + PCI_INT_CD, (sb->enable_gpio_int_route >> 16));
+	}
+
+	printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
+	if (sb->enable_ide_nand_flash == 1) {
+		enable_ide_nand_flash_header();
    }

+	enable_USB_port4(sb);
+
    /* disable unwanted virtual PCI devices */
    for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
    	printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]);
    	outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
-		outl(0xDEADBEEF,                  0xCFC);
+		outl(0xDEADBEEF,				  0xCFC);
    }
 }

@@ -173,7 +599,8 @@
 static void southbridge_enable(struct device *dev)
 {
    printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev);
- }
+
+}

static void cs5536_pci_dev_enable_resources(device_t dev)
 {
@@ -183,23 +610,23 @@
 }

static struct device_operations southbridge_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.read_resources	  = pci_dev_read_resources,
+	.set_resources	  = pci_dev_set_resources,
    .enable_resources = cs5536_pci_dev_enable_resources,
-	.init             = southbridge_init,
-//	.enable           = southbridge_enable,
-	.scan_bus         = scan_static_bus,
+	.init			  = southbridge_init,
+//	.enable			  = southbridge_enable,
+	.scan_bus		  = scan_static_bus,
 };

static struct pci_driver cs5536_pci_driver __pci_driver = {
-	.ops 	= &southbridge_ops,
+	.ops	= &southbridge_ops,
    .vendor = PCI_VENDOR_ID_AMD,
    .device = PCI_DEVICE_ID_AMD_CS5536_ISA
 };

struct chip_operations southbridge_amd_cs5536_ops = {
-	CHIP_NAME("AMD Geode CS5536 Southbridge")
-	/* This only called when this device is listed in the 
+	CHIP_NAME("AMD cs5536")
+	/* This only called when this device is listed in the
    * static device tree.
    */
    .enable_dev = southbridge_enable,
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.h
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536.h	2007-04-30 15:14:24.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.h	2007-04-30 15:14:24.000000000 -0600
@@ -1,4 +1,475 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	 02110-1301 USA
+*/
+
 #ifndef _CS5536_H
 #define _CS5536_H

-#endif
+#define Cx5536_ID	 (	0x208F1022)
+
+/*	SouthBridge Equates */
+#define CS5536_GLINK_PORT_NUM	0x02			/* port of the SouthBridge */
+#define NB_PCI			((2	<< 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
+#define MSR_SB			((CS5536_GLINK_PORT_NUM << 23) + NB_PCI)	/* address to the SouthBridge */
+#define SB_SHIFT		20						/* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
+
+#define CS5536_DEV_NUM	0x0F		/* default PCI device number for CS5536 */
+#define SMBUS_IO_BASE	0x6000
+#define GPIO_IO_BASE	0x6100
+#define MFGPT_IO_BASE	0x6200
+#define ACPI_IO_BASE	0x9C00
+#define PMS_IO_BASE		0x9D00
+
+#define CS5535_IDSEL	0x02000000	 // IDSEL = AD25, device #15
+#define CHIPSET_DEV_NUM	15
+#define IDSEL_BASE		11			 // bit 11 = device 1
+
+/* Cs5536 as follows. */
+/*	SB_GLIU */
+/*	port0 - GLIU */
+/*	port1 - GLPCI */
+/*	port2 - USB Controller #2 */
+/*	port3 - ATA-5 Controller */
+/*	port4 - MDD */
+/*	port5 - AC97 */
+/*	port6 - USB Controller #1 */
+/*	port7 - GLCP */
+
+#define MSR_SB_GLIU		((9 << 14) + MSR_SB)		/* 51024xxx or 510*xxxx	- fake out just like GL0 on CPU. */
+#define MSR_SB_GLPCI	(MSR_SB)			/* 5100xxxx - don't go to the GLIU */
+#define MSR_SB_USB2		((2 << SB_SHIFT) + MSR_SB)	/* 5120xxxx */
+#define MSR_SB_ATA		((3 << SB_SHIFT) + MSR_SB)	/* 5130xxxx */
+#define MSR_SB_MDD		((4 << SB_SHIFT) + MSR_SB)	/* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
+#define MSR_SB_AC97		((5 << SB_SHIFT) + MSR_SB)	/* 5150xxxx */
+#define MSR_SB_USB1		((6 << SB_SHIFT) + MSR_SB)	/* 5160xxxx */
+#define MSR_SB_GLCP		((7 << SB_SHIFT) + MSR_SB)	/* 5170xxxx */
+
+/* */
+/* GLIU*/
+/* */
+#define GLIU_SB_GLD_MSR_CAP		(MSR_SB_GLIU + 0x00)
+#define GLIU_SB_GLD_MSR_CONF	(MSR_SB_GLIU + 0x01)
+#define GLIU_SB_GLD_MSR_PM		(MSR_SB_GLIU + 0x04)
+
+/* */
+/*	USB1*/
+/* */
+#define USB1_SB_GLD_MSR_CAP		(MSR_SB_USB1 + 0x00)
+#define USB1_SB_GLD_MSR_CONF	(MSR_SB_USB1 + 0x01)
+#define USB1_SB_GLD_MSR_PM		(MSR_SB_USB1 + 0x04)
+
+/* */
+/*	USB2*/
+/* */
+#define USB2_SB_GLD_MSR_CAP			(MSR_SB_USB2 + 0x00)
+#define USB2_SB_GLD_MSR_CONF		(MSR_SB_USB2 + 0x01)
+	#define	USB2_UPPER_SSDEN_SET		(1 << 3 )				/* Bit 35 */
+#define USB2_SB_GLD_MSR_PM			(MSR_SB_USB2 + 0x04)
+#define USB2_SB_GLD_MSR_DIAG		(MSR_SB_USB2 + 0x05)
+#define USB2_SB_GLD_MSR_OHCI_BASE	(MSR_SB_USB2 + 0x08)
+#define USB2_SB_GLD_MSR_EHCI_BASE	(MSR_SB_USB2 + 0x09)
+#define USB2_SB_GLD_MSR_DEVCTL_BASE	(MSR_SB_USB2 + 0x0A)
+#define USB2_SB_GLD_MSR_UOC_BASE	(MSR_SB_USB2 + 0x0B) /* Option controller base */
+
+/* */
+/*	ATA*/
+/* */
+#define ATA_SB_GLD_MSR_CAP		(MSR_SB_ATA + 0x00)
+#define ATA_SB_GLD_MSR_CONF		(MSR_SB_ATA + 0x01)
+#define ATA_SB_GLD_MSR_ERR		(MSR_SB_ATA + 0x03)
+#define ATA_SB_GLD_MSR_PM		(MSR_SB_ATA + 0x04)
+
+/* */
+/*	AC97*/
+/* */
+#define AC97_SB_GLD_MSR_CAP		(MSR_SB_AC97 + 0x00)
+#define AC97_SB_GLD_MSR_CONF	(MSR_SB_AC97 + 0x01)
+#define AC97_SB_GLD_MSR_PM		(MSR_SB_AC97 + 0x04)
+
+/* */
+/*	GLPCI*/
+/* */
+#define GLPCI_SB_GLD_MSR_CAP	(MSR_SB_GLPCI + 0x00)
+#define GLPCI_SB_GLD_MSR_CONF	(MSR_SB_GLPCI + 0x01)
+#define GLPCI_SB_GLD_MSR_PM		(MSR_SB_GLPCI + 0x04)
+#define GLPCI_SB_CTRL			(MSR_SB_GLPCI + 0x10)
+#define		GLPCI_CRTL_PPIDE_SET	(1 << 17)
+/* */
+/*	GLCP*/
+/* */
+#define GLCP_SB_GLD_MSR_CAP		(MSR_SB_GLCP + 0x00)
+#define GLCP_SB_GLD_MSR_CONF	(MSR_SB_GLCP + 0x01)
+#define GLCP_SB_GLD_MSR_PM		(MSR_SB_GLCP + 0x04)
+#define GLCP_SB_CLKOFF			(MSR_SB_GLCP + 0x10)
+
+/*	*/
+/*	MDD*/
+/* */
+#define MDD_SB_GLD_MSR_CAP		(MSR_SB_MDD + 0x00)
+#define MDD_SB_GLD_MSR_CONF		(MSR_SB_MDD + 0x01)
+#define MDD_SB_GLD_MSR_PM		(MSR_SB_MDD + 0x04)
+#define LBAR_EN					(0x01)
+#define IO_MASK					(0x1f)
+#define MEM_MASK				(0x0FFFFF)
+#define MDD_LBAR_IRQ			(MSR_SB_MDD + 0x08)
+#define MDD_LBAR_KEL1	(MSR_SB_MDD + 0x09)
+#define MDD_LBAR_KEL2	(MSR_SB_MDD + 0x0A)
+#define MDD_LBAR_SMB	(MSR_SB_MDD + 0x0B)
+#define MDD_LBAR_GPIO	(MSR_SB_MDD + 0x0C)
+#define MDD_LBAR_MFGPT	(MSR_SB_MDD + 0x0D)
+#define MDD_LBAR_ACPI	(MSR_SB_MDD + 0x0E)
+#define MDD_LBAR_PMS	(MSR_SB_MDD + 0x0F)
+
+#define MDD_LBAR_FLSH0	(MSR_SB_MDD + 0x010)
+#define MDD_LBAR_FLSH1	(MSR_SB_MDD + 0x011)
+#define MDD_LBAR_FLSH2	(MSR_SB_MDD + 0x012)
+#define MDD_LBAR_FLSH3	(MSR_SB_MDD + 0x013)
+#define MDD_LEG_IO		(MSR_SB_MDD + 0x014)
+#define MDD_PIN_OPT		(MSR_SB_MDD + 0x015)
+#define MDD_SOFT_IRQ	(MSR_SB_MDD + 0x016)
+#define MDD_SOFT_RESET	(MSR_SB_MDD + 0x017)
+#define MDD_NORF_CNTRL	(MSR_SB_MDD + 0x018)
+#define MDD_NORF_T01	(MSR_SB_MDD + 0x019)
+#define MDD_NORF_T23	(MSR_SB_MDD + 0x01A)
+#define MDD_NANDF_DATA	(MSR_SB_MDD + 0x01B)
+#define MDD_NADF_CNTL	(MSR_SB_MDD + 0x01C)
+#define MDD_AC_DMA		(MSR_SB_MDD + 0x01E)
+#define MDD_KEL_CNTRL	(MSR_SB_MDD + 0x01F)
+
+#define MDD_IRQM_YLOW	(MSR_SB_MDD + 0x020)
+#define MDD_IRQM_YHIGH	(MSR_SB_MDD + 0x021)
+#define MDD_IRQM_ZLOW	(MSR_SB_MDD + 0x022)
+#define MDD_IRQM_ZHIGH	(MSR_SB_MDD + 0x023)
+#define MDD_IRQM_PRIM	(MSR_SB_MDD + 0x024)
+#define MDD_IRQM_LPC	(MSR_SB_MDD + 0x025)
+#define MDD_IRQM_LXIRR	(MSR_SB_MDD + 0x026)
+#define MDD_IRQM_HXIRR	(MSR_SB_MDD + 0x027)
+
+#define MDD_MFGPT_IRQ	(MSR_SB_MDD + 0x028)
+#define MDD_MFGPT_NR	(MSR_SB_MDD + 0x029)
+#define MDD_MFGPT_RES0	(MSR_SB_MDD + 0x02A)
+#define MDD_MFGPT_RES1	(MSR_SB_MDD + 0x02B)
+
+#define MDD_FLOP_S3F2	(MSR_SB_MDD + 0x030)
+#define MDD_FLOP_S3F7	(MSR_SB_MDD + 0x031)
+#define MDD_FLOP_S372	(MSR_SB_MDD + 0x032)
+#define MDD_FLOP_S377	(MSR_SB_MDD + 0x033)
+
+#define MDD_PIC_S		(MSR_SB_MDD + 0x034)
+#define MDD_PIT_S		(MSR_SB_MDD + 0x036)
+#define MDD_PIT_CNTRL	(MSR_SB_MDD + 0x037)
+
+#define MDD_UART1_MOD	(MSR_SB_MDD + 0x038)
+#define MDD_UART1_DON	(MSR_SB_MDD + 0x039)
+#define MDD_UART1_CONF	(MSR_SB_MDD + 0x03A)
+#define MDD_UART2_MOD	(MSR_SB_MDD + 0x03C)
+#define MDD_UART2_DON	(MSR_SB_MDD + 0x03D)
+#define MDD_UART2_CONF	(MSR_SB_MDD + 0x03E)
+
+#define MDD_DMA_MAP		(MSR_SB_MDD + 0x040)
+#define MDD_DMA_SHAD1		(MSR_SB_MDD + 0x041)
+#define MDD_DMA_SHAD2		(MSR_SB_MDD + 0x042)
+#define MDD_DMA_SHAD3		(MSR_SB_MDD + 0x043)
+#define MDD_DMA_SHAD4		(MSR_SB_MDD + 0x044)
+#define MDD_DMA_SHAD5		(MSR_SB_MDD + 0x045)
+#define MDD_DMA_SHAD6		(MSR_SB_MDD + 0x046)
+#define MDD_DMA_SHAD7		(MSR_SB_MDD + 0x047)
+#define MDD_DMA_SHAD8		(MSR_SB_MDD + 0x048)
+#define MDD_DMA_SHAD9		(MSR_SB_MDD + 0x049)
+
+#define MDD_LPC_EADDR	(MSR_SB_MDD + 0x04C)
+#define MDD_LPC_ESTAT	(MSR_SB_MDD + 0x04D)
+#define MDD_LPC_SIRQ	(MSR_SB_MDD + 0x04E)
+#define MDD_LPC_RES		(MSR_SB_MDD + 0x04F)
+
+#define MDD_PML_TMR				(MSR_SB_MDD + 0x050)
+#define MDD_RTC_RAM_LO_CK		(MSR_SB_MDD + 0x054)
+#define MDD_RTC_DOMA_IND		(MSR_SB_MDD + 0x055)
+#define MDD_RTC_MONA_IND		(MSR_SB_MDD + 0x056)
+#define MDD_RTC_CENTURY_OFFSET	(MSR_SB_MDD + 0x057)
+
+
+/* ***********************************************************/
+/*	LBUS Device Equates - */
+/* ***********************************************************/
+
+/* */
+/*	SMBus*/
+/* */
+
+#define	SMB_SDA		0x00
+#define	SMB_STS		0x01
+#define		SMB_STS_SLVSTP	(0x01 << 7)
+#define		SMB_STS_SDAST	(0x01 << 6)
+#define		SMB_STS_BER		(0x01 << 5)
+#define		SMB_STS_NEGACK	(0x01 << 4)
+#define		SMB_STS_STASTR	(0x01 << 3)
+#define		SMB_STS_NMATCH	(0x01 << 2)
+#define		SMB_STS_MASTER	(0x01 << 1)
+#define		SMB_STS_XMIT	(0x01 << 0)
+
+#define	SMB_CTRL_STS	0x02
+#define		SMB_CSTS_TGSCL	(0x01 << 5)
+#define		SMB_CSTS_TSDA	(0x01 << 4)
+#define		SMB_CSTS_GCMTCH	(0x01 << 3)
+#define		SMB_CSTS_MATCH	(0x01 << 2)
+#define		SMB_CSTS_BB		(0x01 << 1)
+#define		SMB_CSTS_BUSY	(0x01 << 0)
+
+#define	SMB_CTRL1	0x03
+#define		SMB_CTRL1_STASTRE	(0x01 << 7)
+#define		SMB_CTRL1_NMINTE	(0x01 << 6)
+#define		SMB_CTRL1_GCMEN		(0x01 << 5)
+#define		SMB_CTRL1_ACK		(0x01 << 4)
+#define		SMB_CTRL1_RSVD		(0x01 << 3)
+#define		SMB_CTRL1_INTEN		(0x01 << 2)
+#define		SMB_CTRL1_STOP		(0x01 << 1)
+#define		SMB_CTRL1_START		(0x01 << 0)
+
+#define	SMB_ADD		0x04
+#define		SMB_ADD_SAEN		(0x01 << 7)
+
+#define	SMB_CTRL2	0x05
+#define		SMB_CTRL2_ENABLE	(0x01 << 0)
+
+#define	SMB_CTRL3	0x06
+
+/* */
+/*	GPIO*/
+/* */
+
+#define GPIOL_0_SET		(1 << 0)
+#define GPIOL_1_SET		(1 << 1)
+#define GPIOL_2_SET		(1 << 2)
+#define GPIOL_3_SET		(1 << 3)
+#define GPIOL_4_SET		(1 << 4)
+#define GPIOL_5_SET		(1 << 5)
+#define GPIOL_6_SET		(1 << 6)
+#define GPIOL_7_SET		(1 << 7)
+#define GPIOL_8_SET		(1 << 8)
+#define GPIOL_9_SET		(1 << 9)
+#define GPIOL_10_SET	(1 << 10)
+#define GPIOL_11_SET	(1 << 11)
+#define GPIOL_12_SET	(1 << 12)
+#define GPIOL_13_SET	(1 << 13)
+#define GPIOL_14_SET	(1 << 14)
+#define GPIOL_15_SET	(1 << 15)
+
+#define GPIOL_0_CLEAR	(1 << 16)
+#define GPIOL_1_CLEAR	(1 << 17)
+#define GPIOL_2_CLEAR	(1 << 18)
+#define GPIOL_3_CLEAR	(1 << 19)
+#define GPIOL_4_CLEAR	(1 << 20)
+#define GPIOL_5_CLEAR	(1 << 21)
+#define GPIOL_6_CLEAR	(1 << 22)
+#define GPIOL_7_CLEAR	(1 << 23)
+#define GPIOL_8_CLEAR	(1 << 24)
+#define GPIOL_9_CLEAR	(1 << 25)
+#define GPIOL_10_CLEAR	(1 << 26)
+#define GPIOL_11_CLEAR	(1 << 27)
+#define GPIOL_12_CLEAR	(1 << 28)
+#define GPIOL_13_CLEAR	(1 << 29)
+#define GPIOL_14_CLEAR	(1 << 30)
+#define GPIOL_15_CLEAR	(1 << 31)
+
+#define GPIOH_16_SET	(1 << 0)
+#define GPIOH_17_SET	(1 << 1)
+#define GPIOH_18_SET	(1 << 2)
+#define GPIOH_19_SET	(1 << 3)
+#define GPIOH_20_SET	(1 << 4)
+#define GPIOH_21_SET	(1 << 5)
+#define GPIOH_22_SET	(1 << 6)
+#define GPIOH_23_SET	(1 << 7)
+#define GPIOH_24_SET	(1 << 8)
+#define GPIOH_25_SET	(1 << 9)
+#define GPIOH_26_SET	(1 << 10)
+#define GPIOH_27_SET	(1 << 11)
+#define GPIOH_28_SET	(1 << 12)
+#define GPIOH_29_SET	(1 << 13)
+#define GPIOH_30_SET	(1 << 14)
+#define GPIOH_31_SET	(1 << 15)
+
+#define GPIOH_16_CLEAR	(1 << 16)
+#define GPIOH_17_CLEAR	(1 << 17)
+#define GPIOH_18_CLEAR	(1 << 18)
+#define GPIOH_19_CLEAR	(1 << 19)
+#define GPIOH_20_CLEAR	(1 << 20)
+#define GPIOH_21_CLEAR	(1 << 21)
+#define GPIOH_22_CLEAR	(1 << 22)
+#define GPIOH_23_CLEAR	(1 << 23)
+#define GPIOH_24_CLEAR	(1 << 24)
+#define GPIOH_25_CLEAR	(1 << 25)
+#define GPIOH_26_CLEAR	(1 << 26)
+#define GPIOH_27_CLEAR	(1 << 27)
+#define GPIOH_28_CLEAR	(1 << 28)
+#define GPIOH_29_CLEAR	(1 << 29)
+#define GPIOH_30_CLEAR	(1 << 30)
+#define GPIOH_31_CLEAR	(1 << 31)
+
+
+/*	GPIO LOW Bank Bit Registers*/
+#define GPIOL_OUTPUT_VALUE			(0x00)
+#define GPIOL_OUTPUT_ENABLE			(0x04)
+#define GPIOL_OUT_OPENDRAIN			(0x08)
+#define GPIOL_OUTPUT_INVERT_ENABLE	(0x0C)
+#define GPIOL_OUT_AUX1_SELECT		(0x10)
+#define GPIOL_OUT_AUX2_SELECT		(0x14)
+#define GPIOL_PULLUP_ENABLE			(0x18)
+#define GPIOL_PULLDOWN_ENABLE		(0x1C)
+#define GPIOL_INPUT_ENABLE			(0x20)
+#define GPIOL_INPUT_INVERT_ENABLE	(0x24)
+#define GPIOL_IN_FILTER_ENABLE		(0x28)
+#define GPIOL_IN_EVENTCOUNT_ENABLE	(0x2C)
+#define GPIOL_READ_BACK				(0x30)
+#define GPIOL_IN_AUX1_SELECT		(0x34)
+#define GPIOL_EVENTS_ENABLE			(0x38)
+#define GPIOL_LOCK_ENABLE			(0x3C)
+#define GPIOL_IN_POSEDGE_ENABLE		(0x40)
+#define GPIOL_IN_NEGEDGE_ENABLE		(0x44)
+#define GPIOL_IN_POSEDGE_STATUS		(0x48)
+#define GPIOL_IN_NEGEDGE_STATUS		(0x4C)
+
+/*	GPIO  High Bank Bit Registers*/
+#define GPIOH_OUTPUT_VALUE			(0x80)
+#define GPIOH_OUTPUT_ENABLE			(0x84)
+#define GPIOH_OUT_OPENDRAIN			(0x88)
+#define GPIOH_OUTPUT_INVERT_ENABLE	(0x8C)
+#define GPIOH_OUT_AUX1_SELECT		(0x90)
+#define GPIOH_OUT_AUX2_SELECT		(0x94)
+#define GPIOH_PULLUP_ENABLE			(0x98)
+#define GPIOH_PULLDOWN_ENABLE		(0x9C)
+#define GPIOH_INPUT_ENABLE			(0x0A0)
+#define GPIOH_INPUT_INVERT_ENABLE	(0x0A4)
+#define GPIOH_IN_FILTER_ENABLE		(0x0A8)
+#define GPIOH_IN_EVENTCOUNT_ENABLE	(0x0AC)
+#define GPIOH_READ_BACK				(0x0B0)
+#define GPIOH_IN_AUX1_SELECT		(0x0B4)
+#define GPIOH_EVENTS_ENABLE			(0x0B8)
+#define GPIOH_LOCK_ENABLE			(0x0BC)
+#define GPIOH_IN_POSEDGE_ENABLE		(0x0C0)
+#define GPIOH_IN_NEGEDGE_ENABLE		(0x0C4)
+#define GPIOH_IN_POSEDGE_STATUS		(0x0C8)
+#define GPIOH_IN_NEGEDGE_STATUS		(0x0CC)
+
+/*	Input Conditioning Function Registers*/
+#define GPIO_00_FILTER_AMOUNT		(0x50)
+#define GPIO_00_FILTER_COUNT		(0x52)
+#define GPIO_00_EVENT_COUNT			(0x54)
+#define GPIO_00_EVENTCOMPARE_VALUE	(0x56)
+#define GPIO_01_FILTER_AMOUNT		(0x58)
+#define GPIO_01_FILTER_COUNT		(0x5A)
+#define GPIO_01_EVENT_COUNT			(0x5C)
+#define GPIO_01_EVENTCOMPARE_VALUE	(0x5E)
+#define GPIO_02_FILTER_AMOUNT		(0x60)
+#define GPIO_02_FILTER_COUNT		(0x62)
+#define GPIO_02_EVENT_COUNT			(0x64)
+#define GPIO_02_EVENTCOMPARE_VALUE	(0x66)
+#define GPIO_03_FILTER_AMOUNT		(0x68)
+#define GPIO_03_FILTER_COUNT		(0x6A)
+#define GPIO_03_EVENT_COUNT			(0x6C)
+#define GPIO_03_EVENTCOMPARE_VALUE	(0x6E)
+#define GPIO_04_FILTER_AMOUNT		(0x70)
+#define GPIO_04_FILTER_COUNT		(0x72)
+#define GPIO_04_EVENT_COUNT			(0x74)
+#define GPIO_04_EVENTCOMPARE_VALUE	(0x76)
+#define GPIO_05_FILTER_AMOUNT		(0x78)
+#define GPIO_05_FILTER_COUNT		(0x7A)
+#define GPIO_05_EVENT_COUNT			(0x7C)
+#define GPIO_05_EVENTCOMPARE_VALUE	(0x7E)
+#define GPIO_06_FILTER_AMOUNT		(0x0D0)
+#define GPIO_06_FILTER_COUNT		(0x0D2)
+#define GPIO_06_EVENT_COUNT			(0x0D4)
+#define GPIO_06_EVENTCOMPARE_VALUE	(0x0D6)
+#define GPIO_07_FILTER_AMOUNT		(0x0D8)
+#define GPIO_07_FILTER_COUNT		(0x0DA)
+#define GPIO_07_EVENT_COUNT			(0x0DC)
+#define GPIO_07_EVENTCOMPARE_VALUE	(0x0DE)
+
+/*	R/W GPIO Interrupt &PME Mapper Registers*/
+#define GPIO_MAPPER_X		(0x0E0)
+#define GPIO_MAPPER_Y		(0x0E4)
+#define GPIO_MAPPER_Z		(0x0E8)
+#define GPIO_MAPPER_W		(0x0EC)
+#define GPIO_FE_SELECT_0	(0x0F0)
+#define GPIO_FE_SELECT_1	(0x0F1)
+#define GPIO_FE_SELECT_2	(0x0F2)
+#define GPIO_FE_SELECT_3	(0x0F3)
+#define GPIO_FE_SELECT_4	(0x0F4)
+#define GPIO_FE_SELECT_5	(0x0F5)
+#define GPIO_FE_SELECT_6	(0x0F6)
+#define GPIO_FE_SELECT_7	(0x0F7)
+
+/*	Event Counter Decrement Registers*/
+#define GPIOL_IN_EVENT_DECREMENT	(0x0F8)
+#define GPIOH_IN_EVENT_DECREMENT	(0x0FC)
+
+/*	This is for 286reset compatibility. 0xCange to mat0xc 5535 virtualized stuff.*/
+#define FUNC0		(0x90)
+
+
+/*	PMC register*/
+#define PM_SSD		(0x00)
+#define PM_SCXA		(0x04)
+#define PM_SCYA		(0x08)
+#define PM_SODA		(0x0C)
+#define PM_SCLK		(0x10)
+#define PM_SED		(0x14)
+#define PM_SCXD		(0x18)
+#define PM_SCYD		(0x1C)
+#define PM_SIDD		(0x20)
+#define PM_WKD		(0x30)
+#define PM_WKXD		(0x34)
+#define PM_RD		(0x38)
+#define PM_WKXA		(0x3C)
+#define PM_FSD		(0x40)
+#define PM_TSD		(0x44)
+#define PM_PSD		(0x48)
+#define PM_NWKD		(0x4C)
+#define PM_AWKD		(0x50)
+#define PM_SSC		(0x54)
+
+
+/* FLASH device macros */
+#define FLASH_TYPE_NONE	0	/* No flash device installed */
+#define FLASH_TYPE_NAND 1	/* NAND device */
+#define FLASH_TYPE_NOR	2	/* NOR device */
+
+#define FLASH_IF_MEM	1	/* Memory or memory-mapped I/O interface for Flash device */
+#define FLASH_IF_IO	2	/* I/O interface for Flash device */
+
+/* Flash Memory Mask values */
+#define FLASH_MEM_DEFAULT	0x00000000
+#define FLASH_MEM_4K		0xFFFFF000
+#define FLASH_MEM_8K		0xFFFFE000
+#define FLASH_MEM_16K		0xFFFFC000
+#define FLASH_MEM_128K		0xFFFE0000
+#define FLASH_MEM_512K		0xFFFC0000
+#define FLASH_MEM_4M		0xFFC00000
+#define FLASH_MEM_8M		0xFF800000
+#define FLASH_MEM_16M		0xFF000000
+
+/* Flash IO Mask values */
+#define FLASH_IO_DEFAULT	0x00000000
+#define FLASH_IO_16B		0x0000FFF0
+#define FLASH_IO_32B		0x0000FFE0
+#define FLASH_IO_64B		0x0000FFC0
+#define FLASH_IO_128B		0x0000FF80
+#define FLASH_IO_256B		0x0000FF00
+
+
+#endif /* _CS5536_H */
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_early_setup.c	2007-04-30 15:14:24.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c	2007-04-30 15:14:24.000000000 -0600
@@ -1,23 +1,31 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/

/*
- *
  * cs5536_early_setup.c:	Early chipset initialization for CS5536 companion device
- *
- *
- * This file implements the initialization sequence documented in section 4.2 of
- * AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
- *
+ *	This file implements the initialization sequence documented in section 4.2 of
+ *	AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
  */

-#define CS5536_GLINK_PORT_NUM	0x02	/* the geode link port number to the CS5536 */       
-#define CS5536_DEV_NUM 		0x0F	/* default PCI device number for CS5536 */
-
 /**
  * @brief Setup PCI IDSEL for CS5536
- *
- * 
  */
-
 static void cs5536_setup_extmsr(void)
 {
    msr_t msr;
@@ -25,11 +33,11 @@
    /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
    msr.hi = msr.lo = 0x00000000;
    if (CS5536_GLINK_PORT_NUM <= 4) {
-		msr.lo = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 1) * 8);
+		msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
    } else {
-		msr.hi = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 5) * 8);
+		msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
    }
-	wrmsr(0x5000201e, msr);
+	wrmsr(GLPCI_ExtMSR, msr);
 }

static void cs5536_setup_idsel(void)
@@ -42,56 +50,58 @@
 {
    msr_t msr;

-	msr = rdmsr(0x51600005);
+	msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
    //USB Serial short detect bit.
    if (msr.hi & 0x10) {
-		/* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
-		 * SERSHRT error bit */
+		/* We need to preserve bits 32,33,35 and not clear any BIST
+		 * error, but clear the SERSHRT error bit */
+
    	msr.hi &= 0xFFFFFFFB;
-		wrmsr(0x51600005, msr);
+		wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr);
    }
 }

-static int cs5536_setup_iobase(void)
+static void cs5536_setup_iobase(void)
 {
    msr_t msr;
-
    /* setup LBAR for SMBus controller */
-	__builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
+	msr.hi = 0x0000f001;
+	msr.lo = SMBUS_IO_BASE;
+	wrmsr(MDD_LBAR_SMB, msr);
+
    /* setup LBAR for GPIO */
-	__builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
+	msr.hi = 0x0000f001;
+	msr.lo = GPIO_IO_BASE;
+	wrmsr(MDD_LBAR_GPIO, msr);
+
    /* setup LBAR for MFGPT */
-	__builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
+	msr.hi = 0x0000f001;
+	msr.lo = MFGPT_IO_BASE;
+	wrmsr(MDD_LBAR_MFGPT, msr);
+
    /* setup LBAR for ACPI */
-	__builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
+	msr.hi = 0x0000f001;
+	msr.lo = ACPI_IO_BASE;
+	wrmsr(MDD_LBAR_ACPI, msr);
+
    /* setup LBAR for PM Support */
-	__builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
+	msr.hi = 0x0000f001;
+	msr.lo = PMS_IO_BASE;
+	wrmsr(MDD_LBAR_PMS, msr);
 }

-static void cs5536_setup_power_bottun(void)
+static void cs5536_setup_power_button(void)
 {
-	/* not implemented yet */
-#if 0
-	pwrBtn_setup:
-	;
-	;	Power Button Setup
-	;
-	;mov	eax, 0C0020000h				; 4 seconds + lock
-	mov	eax, 040020000h				; 4 seconds no lock
-	mov	dx, PMLogic_BASE + 40h
-	out	dx, eax
+	/*	Power Button Setup */
+	outl(0x40020000, PMS_IO_BASE + 0x40);

-	; setup GPIO24, it is the external signal for 5536 vsb_work_aux
+	/* setup GPIO24, it is the external signal for 5536 vsb_work_aux
    ; which controls all voltage rails except Vstandby & Vmem.
    ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
-	; If GPIO24 is not enabled then soft-off will not work.
-	mov	dx, GPIOH_OUT_AUX1_SELECT
-	mov	eax, GPIOH_24_SET
-	out	dx, eax
-	mov	dx, GPIOH_OUTPUT_ENABLE
-	out	dx, eax
+	; If GPIO24 is not enabled then soft-off will not work. */
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);

-#endif
 }

static void cs5536_setup_gpio(void)
@@ -99,155 +109,97 @@
    uint32_t val;

/* setup GPIO pins 14/15 for SDA/SCL */
-	val = (1<<14 | 1<<15);
-	/* Output Enable */
-	outl(0x3fffc000, 0x6100 + 0x04);
-	//outl(val, 0x6100 + 0x04);
-	/* Output AUX1 */
-	outl(0x3fffc000, 0x6100 + 0x10);
-	//outl(val, 0x6100 + 0x10);
-	/* Input Enable */
-	//outl(0x0f5af0a5, 0x6100 + 0x20);
-	outl(0x3fffc000, 0x6100 + 0x20);
-	//outl(val, 0x6100 + 0x20);
-	/* Input AUX1 */
-	//outl(0x3ffbc004, 0x6100 + 0x34);
-	outl(0x3fffc000, 0x6100 + 0x34);
-	//outl(val, 0x6100 + 0x34);
-
-#if 0
-	/* changes proposed by Ollie; we will test this later. */
-	/* setup GPIO pins 14/15 for SDA/SCL */
    val = GPIOL_15_SET | GPIOL_14_SET;
    /* Output Enable */
-	//outl(0x3fffc000, 0x6100 + 0x04);
-	outl(val, 0x6100 + 0x04);
+	outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
    /* Output AUX1 */
-	//outl(0x3fffc000, 0x6100 + 0x10);
-	outl(val, 0x6100 + 0x10);
+	outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
    /* Input Enable */
-	//outl(0x3fffc000, 0x6100 + 0x20);
-	outl(val, 0x6100 + 0x20);
+	outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
    /* Input AUX1 */
-	//outl(0x3fffc000, 0x6100 + 0x34);
-	outl(val, 0x6100 + 0x34);
-#endif
+	outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
 }

static void cs5536_disable_internal_uart(void)
 {
-	/* not implemented yet */
-#if 0
-	; The UARTs default to enabled.
-	; Disable and reset them and configure them later. (SIO init)
-	mov	ecx, MDD_UART1_CONF
-	RDMSR
-	mov	eax, 1h					; reset
-	WRMSR
-	mov	eax, 0h					; disabled
-	WRMSR
-
-	mov	ecx, MDD_UART2_CONF
-	RDMSR
-	mov	eax, 1h					; reset
-	WRMSR
-	mov	eax, 0h					; disabled
-	WRMSR
-
-#endif
+	msr_t msr;
+	/* ; The UARTs default to enabled.
+	; Disable and reset them and configure them later. (SIO init) */
+	msr = rdmsr(MDD_UART1_CONF);
+	msr.lo = 1;					// reset
+	wrmsr(MDD_UART1_CONF, msr);
+	msr.lo = 0;					// disabled
+	wrmsr(MDD_UART1_CONF, msr);
+
+	msr = rdmsr(MDD_UART2_CONF);
+	msr.lo = 1;					// reset
+	wrmsr(MDD_UART2_CONF, msr);
+	msr.lo = 0;					// disabled
+	wrmsr(MDD_UART2_CONF, msr);
 }

static void cs5536_setup_cis_mode(void)
 {
    msr_t msr;

-	/* setup CPU interface serial to mode C on both sides */
-	msr = __builtin_rdmsr(0x51000010);
+	/* setup CPU interface serial to mode B to match CPU */
+	msr = rdmsr(GLPCI_SB_CTRL);
    msr.lo &= ~0x18;
    msr.lo |= 0x10;
-	__builtin_wrmsr(0x51000010, msr.lo, msr.hi);
-	//Only do this if we are building for 5536
-	__builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
+	wrmsr(GLPCI_SB_CTRL, msr);
 }

-static void dummy(void)
-{
-}

/* see page 412 of the cs5536 companion book */
-static int cs5536_setup_onchipuart(void)
+static void cs5536_setup_onchipuart(void)
 {
-	unsigned long m;
-	/* 
+	msr_t msr;
+
+	/* Setup early for polling only mode.
     * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
-	 *    GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
+	 *	  GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
     * 2. Enable UART IO space in MDD
-	 *    MSR 0x51400014 bit 18:16
+	 *	  MSR 0x51400014 bit 18:16
     * 3. Enable UART controller
-	 *    MSR 0x5140003A bit 0, 1
-	 * 4. IRQ routing on IRQ Mapper
-	 *    MSR 0x51400021 bit [27:24]
+	 *	  MSR 0x5140003A bit 0, 1
     */
-	msr_t msr;
- 
-        /*  Bit 1 = DEVEN (device enable)
-         *  Bit 4 = EN_BANKS (allow access to the upper banks)
-         */
- 
-        msr.lo = (1 << 4) | (1 << 1);
-	msr.hi = 0;
-	/*  This enables COM2, but that should be done elsewhere
-	wrmsr(0x5140003e, msr);
-	 */
-

-	/* enable COM1 */
-	wrmsr(0x5140003a, msr);
    /* GPIO8 - UART1_TX */
    /* Set: Output Enable  (0x4) */
-	m = inl(GPIOL_OUTPUT_ENABLE);
-	m |= GPIOL_8_SET;
-	m &= ~GPIOL_8_CLEAR;
-	outl(m,GPIOL_OUTPUT_ENABLE);
+	outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
    /* Set: OUTAUX1 Select (0x10) */
-	m = inl(GPIOL_OUT_AUX1_SELECT);
-	m |= GPIOL_8_SET;
-	m &= ~GPIOL_8_CLEAR;
-	outl(m,GPIOL_OUT_AUX1_SELECT);
-	/* Set: Pull Up        (0x18) */
-	m = inl(GPIOL_PULLUP_ENABLE);
-	m |= GPIOL_8_SET;
-	m &= ~GPIOL_8_CLEAR;
+	outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
    /* GPIO9 - UART1_RX */
-	/* Set: Pull Up        (0x18) */
-	m |= GPIOL_9_SET;
-	m &= ~GPIOL_9_CLEAR;
-	outl(m,GPIOL_PULLUP_ENABLE);
    /* Set: Input Enable   (0x20) */
-	m = inl(GPIOL_INPUT_ENABLE);
-	m |= GPIOL_9_SET;
-	m &= ~GPIOL_9_CLEAR;
-	outl(m,GPIOL_INPUT_ENABLE);
+	outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
    /* Set: INAUX1 Select  (0x34) */
-	m = inl(GPIOL_IN_AUX1_SELECT);
-	m |= GPIOL_9_SET;
-	m &= ~GPIOL_9_CLEAR;
-	outl(m,GPIOL_IN_AUX1_SELECT);
+	outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);

+	/* set address to 3F8 */
    msr = rdmsr(MDD_LEG_IO);
    msr.lo |= 0x7 << 16;
    wrmsr(MDD_LEG_IO,msr);
+
+	/*	Bit 1 = DEVEN (device enable)
+	 *	Bit 4 = EN_BANKS (allow access to the upper banks
+	 */
+	msr.lo = (1 << 4) | (1 << 1);
+	msr.hi = 0;
+
+	/* enable COM1 */
+	wrmsr(MDD_UART1_CONF, msr);
 }

-/* note: you can't do prints in here in most cases, 
- * and we don't want to hang on serial, so they are 
- * commented out 
+/* note: you can't do prints in here in most cases,
+ * and we don't want to hang on serial, so they are
+ * commented out
  */
-static int cs5536_early_setup(void)
+static void cs5536_early_setup(void)
 {
    msr_t msr;

cs5536_setup_extmsr();
+	cs5536_setup_cis_mode();

msr = rdmsr(GLCP_SYS_RSTPLL);
    if (msr.lo & (0x3f << 26)) {
@@ -262,9 +214,8 @@
    cs5536_setup_iobase();
    //print_debug("Setup gpio\r\n");
    cs5536_setup_gpio();
-	//print_debug("Setup cis_mode\r\n");
-	cs5536_setup_cis_mode();
    //print_debug("Setup smbus\r\n");
    cs5536_enable_smbus();
-	dummy();
+	//print_debug("Setup power button\r\n");
+	cs5536_setup_power_button();
 }
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_smbus.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_early_smbus.c	2007-04-30 15:14:24.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_smbus.c	2007-04-30 15:14:24.000000000 -0600
@@ -1,45 +1,215 @@
-#include "cs5536_smbus.h"
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/
+
+#include "cs5536.h"
+
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
+#define SMBUS_TIMEOUT (1000)

-#define SMBUS_IO_BASE 0x6000

/* initialization for SMBus Controller */
-static int cs5536_enable_smbus(void)
+static void cs5536_enable_smbus(void)
 {
-	unsigned char val;
-
-	/* reset SMBUS controller */
-	outb(0, SMBUS_IO_BASE + SMB_CTRL2);

/* Set SCL freq and enable SMB controller */
-	val = inb(SMBUS_IO_BASE + SMB_CTRL2);
-	val |= ((0x20 << 1) | SMB_CTRL2_ENABLE);
-	outb(val, SMBUS_IO_BASE + SMB_CTRL2);
+	/*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);*/
+	outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);

/* Setup SMBus host controller address to 0xEF */
-	val = inb(SMBUS_IO_BASE + SMB_ADD);
-	val |= (0xEF | SMB_ADD_SAEN);
-	outb(val, SMBUS_IO_BASE + SMB_ADD); 
+	outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD);
+
 }

-static int smbus_read_byte(unsigned device, unsigned address)
+static void smbus_delay(void)
 {
-        return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1);
+	/* inb(0x80); */
+}
+
+
+static int smbus_wait(unsigned smbus_io_base) {
+	unsigned long loops = SMBUS_TIMEOUT;
+	unsigned char val;
+
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_STS);
+		if ((val & SMB_STS_SDAST) != 0)
+			break;
+		if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
+			/*printk_debug("SMBUS WAIT ERROR %x\n", val);*/
+			return SMBUS_ERROR;
+		}
+	} while(--loops);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }

-#if 0
-static int smbus_recv_byte(unsigned device)
+/* generate a smbus start condition */
+static int smbus_start_condition(unsigned smbus_io_base)
 {
-        return do_smbus_recv_byte(SMBUS_IO_BASE, device);
+	unsigned char val;
+
+	/* issue a START condition */
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
+
+	/* check for bus conflict */
+	val = inb(smbus_io_base + SMB_STS);
+	if ((val & SMB_STS_BER) != 0)
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
 }

-static int smbus_send_byte(unsigned device, unsigned char val)
+static int smbus_check_stop_condition(unsigned smbus_io_base)
 {
-        return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
+	unsigned char val;
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	/* check for SDA status */
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_CTRL1);
+		if ((val & SMB_CTRL1_STOP) == 0) {
+			break;
+		}
+		outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
+	} while(--loops);
+	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }

+static int smbus_stop_condition(unsigned smbus_io_base)
+{
+	outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
+	return smbus_wait(smbus_io_base);
+}

-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+static int smbus_ack(unsigned smbus_io_base, int state)
 {
-        return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
+	unsigned char val = inb(smbus_io_base + SMB_CTRL1);
+
+/*	if (state) */
+		outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+/*	else
+		outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+*/
+	return 0;
 }
-#endif
+
+static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
+{
+	unsigned char val;
+
+	/* send the slave address */
+	outb(device, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER)	!= 0) ||
+		((val & SMB_STS_NEGACK) != 0)) {
+		/* printk_debug("SEND SLAVE ERROR (%x)\n", val);*/
+		return SMBUS_ERROR;
+	}
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
+{
+	unsigned char val;
+
+	/* send the command */
+	outb(command, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER)	!= 0) ||
+		((val & SMB_STS_NEGACK) != 0))
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static unsigned char smbus_get_result(unsigned smbus_io_base)
+{
+	return inb(smbus_io_base + SMB_SDA);
+}
+
+static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
+{
+	unsigned char error = 0;
+
+	if ((smbus_check_stop_condition(smbus_io_base))) {
+		error = 1;
+		goto err;
+	}
+
+	if ((smbus_start_condition(smbus_io_base))) {
+		error = 2;
+		goto err;
+	}
+
+	if ((smbus_send_slave_address(smbus_io_base, device))) {
+		error = 3;
+		goto err;
+	}
+
+	smbus_ack(smbus_io_base, 1 );
+
+	if ((smbus_send_command(smbus_io_base, address))) {
+		error = 4;
+		goto err;
+	}
+
+	if ((smbus_start_condition(smbus_io_base))) {
+		error = 5;
+		goto err;
+	}
+
+	if ((smbus_send_slave_address(smbus_io_base, device | 0x01))) {
+		error = 6;
+		goto err;
+	}
+
+	if ((smbus_stop_condition(smbus_io_base))) {
+		error = 7;
+		goto err;
+	}
+
+	return smbus_get_result(smbus_io_base);
+
+
+err:
+	print_debug("SMBUS READ ERROR:");
+		print_debug_hex8(error);
+		print_debug(" device:");
+		print_debug_hex8(device);
+		print_debug("\r\n");
+	/* stop, clean up the error, and leave */
+	smbus_stop_condition(smbus_io_base);
+	outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
+	outb(0x0, smbus_io_base + SMB_STS);
+	return 0xFF;
+}
+
+static inline int smbus_read_byte(unsigned device, unsigned address)
+{
+		return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_ide.c	2007-04-30 15:14:24.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c	2007-04-30 15:14:24.000000000 -0600
@@ -1,3 +1,22 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	 02110-1301 USA
+*/
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -5,26 +24,45 @@
 #include <device/pci_ops.h>
 #include "cs5536.h"

+#define IDE_CFG	  0x40
+  #define CHANEN  (1L <<  1)
+  #define PWB	  (1L << 14)
+  #define CABLE	  (1L << 16)
+#define IDE_DTC	  0x48
+#define IDE_CAST  0x4C
+#define IDE_ETC	  0x50
+
 static void ide_init(struct device *dev)
 {
+	uint32_t ide_cfg;
+
    printk_spew("cs5536_ide: %s\n", __FUNCTION__);
+	/* GPIO and IRQ setup are handled in the main chipset code. */
+
+	// Enable the channel and Post Write Buffer
+	// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
+	ide_cfg = pci_read_config32(dev, IDE_CFG);
+	ide_cfg |= CHANEN | PWB;
+	pci_write_config8(dev, IDE_CFG, ide_cfg);
 }

static void ide_enable(struct device *dev)
 {
+
    printk_spew("cs5536_ide: %s\n", __FUNCTION__);
+
 }

static struct device_operations ide_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.read_resources	  = pci_dev_read_resources,
+	.set_resources	  = pci_dev_set_resources,
    .enable_resources = pci_dev_enable_resources,
-	.init             = ide_init,
-	.enable           = ide_enable,
+	.init			  = ide_init,
+	.enable			  = 0,
 };

static struct pci_driver ide_driver __pci_driver = {
-	.ops 	= &ide_ops,
+	.ops	= &ide_ops,
    .vendor = PCI_VENDOR_ID_AMD,
    .device = PCI_DEVICE_ID_AMD_CS5536_IDE,
 };
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus.h
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_smbus.h	2007-04-30 15:14:43.000000000 -0600
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,180 +0,0 @@
-//#include <device/smbus_def.h>
-#define SMBUS_ERROR -1
-#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
-#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
-
-#define	SMB_SDA		0x00
-#define SMB_STS		0x01
-#define SMB_CTRL_STS	0x02
-#define	SMB_CTRL1	0x03
-#define SMB_ADD		0x04
-#define SMB_CTRL2	0x05
-#define	SMB_CTRL3	0x06
-
-#define SMB_STS_SLVSTP	(0x01 << 7)
-#define SMB_STS_SDAST	(0x01 << 6)
-#define	SMB_STS_BER	(0x01 << 5)
-#define SMB_STS_NEGACK	(0x01 << 4)
-#define	SMB_STS_STASTR	(0x01 << 3)
-#define SMB_STS_NMATCH	(0x01 << 2)
-#define	SMB_STS_MASTER	(0x01 << 1)
-#define SMB_STS_XMIT	(0x01 << 0)
-
-#define	SMB_CSTS_TGSCL	(0x01 << 5)
-#define SMB_CSTS_TSDA	(0x01 << 4)
-#define	SMB_CSTS_GCMTCH	(0x01 << 3)
-#define SMB_CSTS_MATCH	(0x01 << 2)
-#define	SMB_CSTS_BB	(0x01 << 1)
-#define SMB_CSTS_BUSY	(0x01 << 0)
-
-#define	SMB_CTRL1_STASTRE (0x01 << 7)
-#define SMB_CTRL1_NMINTE  (0x01 << 6)
-#define	SMB_CTRL1_GCMEN   (0x01 << 5)
-#define SMB_CTRL1_ACK     (0x01 << 4)
-#define	SMB_CTRL1_RSVD    (0x01 << 3)
-#define SMB_CTRL1_INTEN   (0x01 << 2)
-#define	SMB_CTRL1_STOP    (0x01 << 1)
-#define SMB_CTRL1_START   (0x01 << 0)
-
-#define	SMB_ADD_SAEN	  (0x01 << 7)
-
-#define	SMB_CTRL2_ENABLE  0x01
-
-#define SMBUS_TIMEOUT (100*1000*10)
-#define SMBUS_STATUS_MASK 0xfbff
-
-#define SMBUS_IO_BASE 0x6000
-
-static void smbus_delay(void)
-{
-    	outb(0x80, 0x80);
-}
-
-/* generate a smbus start condition */
-static int smbus_start_condition(unsigned smbus_io_base)
-{
-	unsigned char val;
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-
-	/* issue a START condition */
-	val = inb(smbus_io_base + SMB_CTRL1);
-	outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
-
-	/* check for bus conflict */
-	val = inb(smbus_io_base + SMB_STS);
-	if ((val & SMB_STS_BER) != 0)
-		return SMBUS_ERROR;
-
-	/* check for SDA status */
-	do {
-		smbus_delay();
-		val = inw(smbus_io_base + SMB_STS);
-		if ((val & SMB_STS_SDAST) != 0) {
-			break;
-		}
-	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_check_stop_condition(unsigned smbus_io_base)
-{
-	unsigned char val;
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	/* check for SDA status */
-	do {
-		smbus_delay();
-		val = inw(smbus_io_base + SMB_CTRL1);
-		if ((val & SMB_CTRL1_STOP) == 0) {
-			break;
-		}
-	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_stop_condition(unsigned smbus_io_base)
-{
-	unsigned char val;
-	val = inb(smbus_io_base + SMB_CTRL1);
-	outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
-}
-
-static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
-{
-	unsigned char val;
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-                        
-	/* send the slave address */
-	outb(device, smbus_io_base + SMB_SDA);
-
-	/* check for bus conflict and NACK */
-	val = inb(smbus_io_base + SMB_STS);
-	if (((val & SMB_STS_BER)    != 0) ||
-	    ((val & SMB_STS_NEGACK) != 0))
-		return SMBUS_ERROR;
-
-	/* check for SDA status */
-	do {
-		smbus_delay();
-		val = inw(smbus_io_base + SMB_STS);
-		if ((val & SMB_STS_SDAST) != 0) {
-			break;
-		}
-	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;	
-}
-
-static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
-{
-        unsigned char val;
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-
-	/* send the command */
-	outb(command, smbus_io_base + SMB_SDA);
-
-	/* check for bus conflict and NACK */
-	val = inb(smbus_io_base + SMB_STS);
-	if (((val & SMB_STS_BER)    != 0) ||
-	    ((val & SMB_STS_NEGACK) != 0))
-		return SMBUS_ERROR;
-
-	/* check for SDA status */
-	do {
-		smbus_delay();
-		val = inw(smbus_io_base + SMB_STS);
-		if ((val & SMB_STS_SDAST) != 0) {
-			break;
-		}
-	} while(--loops);
-	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;	
-}
-
-static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
-{
-	unsigned char val, val1;
-
-	smbus_check_stop_condition(smbus_io_base);
-
-	smbus_start_condition(smbus_io_base);
-
-	smbus_send_slave_address(smbus_io_base, device);
-
-	smbus_send_command(smbus_io_base, address);
-
-	smbus_start_condition(smbus_io_base);
-
-	smbus_send_slave_address(smbus_io_base, device | 0x01);
-
-	/* send NACK to slave */
-	val = inb(smbus_io_base + SMB_CTRL1);
-	outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-
-	val = inb(smbus_io_base + SMB_SDA);
-
-	//smbus_stop_condition(smbus_io_base);
-
-	return val;
-}
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
@@ -43,11 +43,10 @@
 #define SMBUS_TIMEOUT (100*1000*10)
 #define SMBUS_STATUS_MASK 0xfbff

-#define SMBUS_IO_BASE 0x6000

static void smbus_delay(void)
 {
-	outb(0x80, 0x80);
+	inb(0x80);
 }

static int smbus_wait(unsigned smbus_io_base) {

[LinuxBIOS] [patch 4/4] AMD Geode GX/LX: CS5536 Southbridge

[Peter Stuge]

Sorry, I don't think I'm qualified to comment on anything but trivial
things.

On Tue, May 01, 2007 at 04:48:31PM -0600, Marc Jones wrote:
> -#define PCI_DEVICE_ID_AMD_CS5536_IDE	0x2092
> +#define PCI_DEVICE_ID_AMD_CS5536_IDE_OLD	0x2092

There must be a better name.
> +/*	This is for 286reset compatibility. 0xCange to mat0xc 5535 virtualized stuff.*/

?

//Peter

[LinuxBIOS] [patch 4/4] AMD Geode GX/LX: CS5536 Southbridge

[Uwe Hermann]

On Tue, May 01, 2007 at 04:48:31PM -0600, Marc Jones wrote:
> Index: LinuxBIOSv2/src/southbridge/amd/cs5536/Config.lb
>
> --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/Config.lb	2007-04-30 15:14:24.000000000 -0600
> +++ LinuxBIOSv2/src/southbridge/amd/cs5536/Config.lb	2007-04-30 15:14:24.000000000 -0600
> @@ -1,4 +1,22 @@
> +#/*
> +#* This file is part of the LinuxBIOS project.
> +#*
> +#*
> +#* This program is free software; you can redistribute it and/or modify
> +#* it under the terms of the GNU General Public License version 2 as
> +#* published by the Free Software Foundation.
> +#*
> +#* This program is distributed in the hope that it will be useful,
> +#* but WITHOUT ANY WARRANTY; without even the implied warranty of
> +#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +#* GNU General Public License for more details.
> +#*
> +#* You should have received a copy of the GNU General Public License
> +#* along with this program; if not, write to the Free Software
> +#* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +#*/

Missing copyright holder.
> +/* ***************************************************************************/
> +/* **/
> +/* *	ChipsetInit */
> +/*			Called from northbridge init (Pre-VSA). */
> +/* **/
> +/* ***************************************************************************/

More cosmetics -- please use Doxygen-style comments if possible. We're
trying to consistently use Doxygen comments in all of LinuxBIOS (at
least in the next version, LinuxBIOSv3).
> struct chip_operations southbridge_amd_cs5536_ops = {
> CHIP_NAME("AMD Geode CS5536 Southbridge")
> /* This only called when this device is listed in the
> CHIP_NAME("AMD cs5536")

Why the name change?
> Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h
>
> --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
> +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600

[...]
> static void smbus_delay(void)
>  {
> outb(0x80, 0x80);
> inb(0x80);
>
> }

Why? Please document this in the code (what, how, why). Did you perform
measurements? Why did the outb() not work?

Uwe.

[LinuxBIOS] [patch 4/4] AMD Geode GX/LX: CS5536 Southbridge

[Corey Osgood]

Uwe Hermann wrote:
> On Tue, May 01, 2007 at 04:48:31PM -0600, Marc Jones wrote:
> > Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h
> >
> > --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
> > +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
>
> [...]
> > static void smbus_delay(void)
> >  {
> > outb(0x80, 0x80);
> > inb(0x80);
> >
> > }
>
> Why? Please document this in the code (what, how, why). Did you perform
> measurements? Why did the outb() not work?

There may be other reasons, but outb and inb both provide enough of a
delay for smbus use. By using inb, you don't clear a potentially helpful
post code.
> > Index: LinuxBIOSv2/src/mainboard/amd/norwich/auto.c
> >
> > --- /dev/null	1970-01-01 00:00:00.000000000 +0000
> > +++ LinuxBIOSv2/src/mainboard/amd/norwich/auto.c	2007-05-01

01:32:02.000000000 -0600
> [...]
> > +#define POST_CODE(x) outb(x, 0x80)
>
> Why this? We have a post_code() function in src/console/console.c.

Isn't src/console/console.c for post ram init?

-Corey

[LinuxBIOS] [patch 4/4] AMD Geode GX/LX: CS5536 Southbridge

[Marc Jones]

Corey is correct on both comments.

All BIOS use port 80 as the debug port (including LinuxBIOS). An out to 
port 80 is noisy, especially in a bios debug environment. What makes it 
a delay is that it is a serializing read/write (it can't be pre-fetchand 
and can't be in the cache etc). In this particular case it is an 
arbitrary delay to wait for smbus devices to respond. I say arbitrary 
because it will change as the pci and glbus (internal geode bus) speeds 
change based on memory and pci loading. An inb is as good an arbitrary 
delay as an outb.

I don't think that this delay should there at all but I wasn't prepared 
to rewrite the entire section. It would be equivalent to poll the SMBus 
controllers IO register.

I think it would be in the best interest of LinuxBIOS to not have any 
outb(0x80, 0x80) delays. Either they should be inb if it can be an 
arbitrary delay or they should be changed to TSC based delays. See 
\LinuxBIOSv2\src\x86\tsc\delay_tysc.c

</soapbox>

Marc

Corey Osgood wrote:
> Uwe Hermann wrote:
> > On Tue, May 01, 2007 at 04:48:31PM -0600, Marc Jones wrote:
> > > Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h
> > >
> > > --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
> > > +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
> >
> > [...]
> > > static void smbus_delay(void)
> > >  {
> > > outb(0x80, 0x80);
> > > inb(0x80);
> > >
> > > }
> >
> > Why? Please document this in the code (what, how, why). Did you perform
> > measurements? Why did the outb() not work?
>
> There may be other reasons, but outb and inb both provide enough of a
> delay for smbus use. By using inb, you don't clear a potentially helpful
> post code.
> > > Index: LinuxBIOSv2/src/mainboard/amd/norwich/auto.c
> > >
> > > --- /dev/null	1970-01-01 00:00:00.000000000 +0000
> > > +++ LinuxBIOSv2/src/mainboard/amd/norwich/auto.c	2007-05-01
>
> 01:32:02.000000000 -0600
> > [...]
> > > +#define POST_CODE(x) outb(x, 0x80)
> >
> > Why this? We have a post_code() function in src/console/console.c.
>
> Isn't src/console/console.c for post ram init?
>
> -Corey

[LinuxBIOS] [patch 4/4] AMD Geode GX/LX: CS5536 Southbridge

[Marc Jones]

Uwe Hermann wrote:
> On Tue, May 01, 2007 at 04:48:31PM -0600, Marc Jones wrote:
> > Index: LinuxBIOSv2/src/southbridge/amd/cs5536/Config.lb
> >
> > --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/Config.lb	2007-04-30 15:14:24.000000000 -0600
> > +++ LinuxBIOSv2/src/southbridge/amd/cs5536/Config.lb	2007-04-30 15:14:24.000000000 -0600
> > @@ -1,4 +1,22 @@
> > +#/*
> > +#* This file is part of the LinuxBIOS project.
> > +#*
> > +#*
> > +#* This program is free software; you can redistribute it and/or modify
> > +#* it under the terms of the GNU General Public License version 2 as
> > +#* published by the Free Software Foundation.
> > +#*
> > +#* This program is distributed in the hope that it will be useful,
> > +#* but WITHOUT ANY WARRANTY; without even the implied warranty of
> > +#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > +#* GNU General Public License for more details.
> > +#*
> > +#* You should have received a copy of the GNU General Public License
> > +#* along with this program; if not, write to the Free Software
> > +#* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> > +#*/
>
> Missing copyright holder.
> > +/* ***************************************************************************/
> > +/* **/
> > +/* *	ChipsetInit */
> > +/*			Called from northbridge init (Pre-VSA). */
> > +/* **/
> > +/* ***************************************************************************/
>
> More cosmetics -- please use Doxygen-style comments if possible. We're
> trying to consistently use Doxygen comments in all of LinuxBIOS (at
> least in the next version, LinuxBIOSv3).
> > struct chip_operations southbridge_amd_cs5536_ops = {
> > CHIP_NAME("AMD Geode CS5536 Southbridge")
> > /* This only called when this device is listed in the
> > CHIP_NAME("AMD cs5536")
>
> Why the name change?

Oversite on my part. I missed that in the merge  to code that changed 
from when I started. - fixing.
> > Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h
> >
> > --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
> > +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h	2007-04-30 15:14:24.000000000 -0600
>
> [...]
> > static void smbus_delay(void)
> >  {
> > outb(0x80, 0x80);
> > inb(0x80);
> >
> > }
>
> Why? Please document this in the code (what, how, why). Did you perform
> measurements? Why did the outb() not work?
>
> Uwe.

[Uwe Hermann]

Hi Marc!

On Tue, May 01, 2007 at 04:48:27PM -0600, Marc Jones wrote:
> Hello LinuxBIOS Community,
>
> My name is Marc Jones and I work for the AMD embedded group. Jordan
> Crouse and I have been working with Ron Minnich on a Geode LX LinuxBIOS
> implementation for the AMD Norwich development platform.

This is great news! Thanks a lot for your work!
> Our implementation has been split into four patches: cpu, northbridge,
> southbridge, and mainboard. All four are required to build the Norwich
> platform. Ron and I expect this to break the current OLPC mainboards. We
> will work on fixing then soon (Note that OLPC went from GX to LX so an
> update was required regardless).

The LX-based OLPC should become another subdirectory of olpc/, just like
rev_a and btest, right? I'd rather not touch the existing directories if
the changes are that massive. This way we wouldn't break any targets
(just add a new one), correct?
> In addition to the patches you will need the Geode LX VSA binary that is
> located here:
>
> http://www.amd.com/files/connectivitysolutions/geode/geode_lx/lx_vsa.36k.bin...

Where's the source code? SCNR :)

I assume the source is not publically available? That would sure be
great! If not, what exact usage rights come with the binary?

Also, is the VSA binary needed for _any_ LinuxBIOS usage on the LX, or
just to enable certain features? In other words, can we do _anything_
with the LX without the VSA binary?

Uwe.

[Peter Stuge]

Hey Marc, welcome to the list!

On Tue, May 01, 2007 at 04:48:27PM -0600, Marc Jones wrote:
> Our implementation has been split into four patches: cpu,
> northbridge, southbridge,

These three patches all contain systematic whitespace breakage and
some code cleanups. Could you separate that from the actual code
changes and provide separate patches?

(It could be that your development tools introduce whitespace and
formatting changes rather than you doing it on purpose. Please fix
your tools in that case.)
> and mainboard.

This is all new files, so I think it looks good.

On Wed, May 02, 2007 at 01:32:12AM +0200, Uwe Hermann wrote:
> > In addition to the patches you will need the Geode LX VSA binary
> > that is located here:
> >
> > http://www.amd.com/files/connectivitysolutions/geode/geode_lx/lx_vsa.36k.bin...
>
> Where's the source code? SCNR :)
>
> I assume the source is not publically available? That would sure be
> great!

I guess it's all assembly anyway, but I agree having the source would
be better than only having the blob.

What are your thoughts on this, AMD?

Thanks!

//Peter

[Marc Jones]

Uwe,
See my answers below.

Uwe Hermann wrote:
> Hi Marc!
>
> On Tue, May 01, 2007 at 04:48:27PM -0600, Marc Jones wrote:
> > Hello LinuxBIOS Community,
> >
> > My name is Marc Jones and I work for the AMD embedded group. Jordan
> > Crouse and I have been working with Ron Minnich on a Geode LX LinuxBIOS
> > implementation for the AMD Norwich development platform.
>
> This is great news! Thanks a lot for your work!

You are welcome.
> > Our implementation has been split into four patches: cpu, northbridge,
> > southbridge, and mainboard. All four are required to build the Norwich
> > platform. Ron and I expect this to break the current OLPC mainboards. We
> > will work on fixing then soon (Note that OLPC went from GX to LX so an
> > update was required regardless).
>
> The LX-based OLPC should become another subdirectory of olpc/, just like
> rev_a and btest, right? I'd rather not touch the existing directories if
> the changes are that massive. This way we wouldn't break any targets
> (just add a new one), correct?

This will break the olpc targets but they were already suffering from 
bitrot in the division of northbridge and chipset code. Ron and I agreed 
to move ahead and to bring them up to speed when we can. The priority 
will be the LX version since the rev a/b are already out of date and 
will not see production.
> > In addition to the patches you will need the Geode LX VSA binary that is
> > located here:
> >
> > http://www.amd.com/files/connectivitysolutions/geode/geode_lx/lx_vsa.36k.bin...
>
> Where's the source code? SCNR :)
>
> I assume the source is not publically available? That would sure be
> great! If not, what exact usage rights come with the binary?

The VSA binary source is LGPL and is available at: 
http://dev.laptop.org/git.do?p=geode-vsa
This is just a temporary home until we can port it to open source/linux 
tools and find the code a home. It currently builds with Microsoft MASM 
and C. We are trying to move to GCC. We post the binary since most OSD 
can't build it.
> Also, is the VSA binary needed for _any_ LinuxBIOS usage on the LX, or
> just to enable certain features? In other words, can we do _anything_
> with the LX without the VSA binary?

VSA is not required. An example is the OLPC Open Firmware + custom Linux 
image.
> Uwe.

Marc

[Peter Stuge]

On Tue, May 01, 2007 at 06:10:54PM -0600, Marc Jones wrote:
> The VSA binary source is LGPL

Awesome!
> and is available at: http://dev.laptop.org/git.do?p=geode-vsa

git.do seems broken. I get a PHP error.
> This is just a temporary home until we can port it to open
> source/linux tools and find the code a home. It currently builds
> with Microsoft MASM and C. We are trying to move to GCC. We post
> the binary since most OSD can't build it.

You can earn a lot of free credit by also mentioning the source. :)
> > Also, is the VSA binary needed for _any_ LinuxBIOS usage on the
> > LX, or just to enable certain features? In other words, can we
> > do _anything_ with the LX without the VSA binary?
>
> VSA is not required. An example is the OLPC Open Firmware + custom
> Linux image.

Could you expand on what benfits this VSA blob lead to?

And how does it hook into LinuxBIOS?

Is the blob really only a VSM, and there is already generic VSA
support in LinuxBIOS?

Etc.

//Peter

[Corey Osgood]

Peter Stuge wrote:
> On Tue, May 01, 2007 at 06:10:54PM -0600, Marc Jones wrote:
> > The VSA binary source is LGPL
>
> Awesome!

Agreed :)
> > and is available at: http://dev.laptop.org/git.do?p=geode-vsa
>
> git.do seems broken. I get a PHP error.

Works fine here, with FF 2.0

-Corey

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Jordan Crouse]

On 02/05/07 02:50 +0200, Peter Stuge wrote:
> > and is available at: http://dev.laptop.org/git.do?p=geode-vsa
>
> git.do seems broken. I get a PHP error.

I think dev.laptop.org has been sick on and off today - I just tried it,
and it seems to be up.

Jordan

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Peter Stuge]

On Tue, May 01, 2007 at 07:14:08PM -0600, Jordan Crouse wrote:
> On 02/05/07 02:50 +0200, Peter Stuge wrote:
> > > and is available at: http://dev.laptop.org/git.do?p=geode-vsa
> >
> > git.do seems broken. I get a PHP error.
>
> I think dev.laptop.org has been sick on and off today - I just
> tried it, and it seems to be up.

Yeah, works now. Had a quick look at some assembly, it could probably
build with nasm without much effort. Oh well. :)

//Peter

[Marc Jones]

Peter Stuge wrote:
> On Tue, May 01, 2007 at 06:10:54PM -0600, Marc Jones wrote:
> > The VSA binary source is LGPL
>
> Awesome!
> > and is available at: http://dev.laptop.org/git.do?p=geode-vsa
>
> git.do seems broken. I get a PHP error.
> > This is just a temporary home until we can port it to open
> > source/linux tools and find the code a home. It currently builds
> > with Microsoft MASM and C. We are trying to move to GCC. We post
> > the binary since most OSD can't build it.
>
> You can earn a lot of free credit by also mentioning the source. :)
> > > Also, is the VSA binary needed for _any_ LinuxBIOS usage on the
> > > LX, or just to enable certain features? In other words, can we
> > > do _anything_ with the LX without the VSA binary?
> >
> > VSA is not required. An example is the OLPC Open Firmware + custom
> > Linux image.
>
> Could you expand on what benfits this VSA blob lead to?
>
> And how does it hook into LinuxBIOS?
>
> Is the blob really only a VSM, and there is already generic VSA
> support in LinuxBIOS?
>
> Etc.
>
> //Peter

The VSA code main responsibility is to virtualize the pci config space 
for the internal devices (video, usb, ide, etc.) The posted binary and 
source code is VSA and contains several VSMs, sysmanager, legacy, and lx 
graphics. LinuxBIOS already had support for VSA from the olpc port. The 
same mechanism is used. VSA is treated as a payload that is run before 
LinuxBIOS pci initialization. See src\cpu\model_lc\vsmsetup.c (it should 
probably be renamed vsasetup.c but that is a minor detail)

Marc

[LinuxBIOS] [patch 0/4] AMD Geode LX VSA and VSMs

[Peter Stuge]

On Wed, May 02, 2007 at 01:25:46PM -0600, Marc Jones wrote:
> The posted binary and source code is VSA and contains several VSMs,
> sysmanager, legacy, and lx graphics.

Would it make sense to move parts or all of the VSM code into the
operating system?

(Not in it's current form of course. Yes, I know it means having to
re-implement each VSM in each OS.)
> LinuxBIOS already had support for VSA from the olpc port. The same
> mechanism is used. VSA is treated as a payload that is run before
> LinuxBIOS pci initialization. See src\cpu\model_lc\vsmsetup.c (it
> should probably be renamed vsasetup.c but that is a minor detail)

Thanks for explaining this a bit more! :)

//Peter

[LinuxBIOS] AMD Geode LX VSA and VSMs

[Jordan Crouse]

On 02/05/07 21:43 +0200, Peter Stuge wrote:
> On Wed, May 02, 2007 at 01:25:46PM -0600, Marc Jones wrote:
> > The posted binary and source code is VSA and contains several VSMs,
> > sysmanager, legacy, and lx graphics.
>
> Would it make sense to move parts or all of the VSM code into the
> operating system?

Thats what OFW does for OLPC - and its fraught with danger.  Case in 
point?  A few days ago, the amount of video memory was doubled in OFW,
to 16MB.  But since the PCI spoofing happens in the kernel, it didn't 
get the message that the video memory changed, and the PCI BAR was still
sized to 8MB, and X goes boom.

This is intelligence (or insanity, depending on your point of view),
that very much belongs in the firmware - the kernel shouldn't need to 
know how any of this works.

Jordan

[LinuxBIOS] AMD Geode LX VSA and VSMs

[Stefan Reinauer]

* Jordan Crouse  [070503 17:39]:
> Thats what OFW does for OLPC - and its fraught with danger.  Case in 
> point?  A few days ago, the amount of video memory was doubled in OFW,
> to 16MB.  But since the PCI spoofing happens in the kernel, it didn't 
> get the message that the video memory changed, and the PCI BAR was still
> sized to 8MB, and X goes boom.

With VSA, is the PCI spoofing done in system management mode?
> This is intelligence (or insanity, depending on your point of view),
> that very much belongs in the firmware - the kernel shouldn't need to 
> know how any of this works.

I completely agree on that. While having component (drivers) and
architecture specific knowledge in the kernel definitely makes sense,
such board specific details do not belong in the kernel, or it will make
the kernel very hard to maintain.

The fact that drivers and scheduler and memory management are all part
of a big hunk in Linux is really nasty already. I believe Tannenbaum was
right with his words. Today even more than back when he was discussing
with Linus.

Stefan

[LinuxBIOS] AMD Geode LX VSA and VSMs

[Peter Stuge]

On Thu, May 03, 2007 at 06:47:04PM +0200, Stefan Reinauer wrote:
> With VSA, is the PCI spoofing done in system management mode?

Yes.
> such board specific details do not belong in the kernel,

Isn't it "just" platform specific?

//Peter

[LinuxBIOS] AMD Geode LX VSA and VSMs

[ron minnich]

On 5/3/07, Stefan Reinauer  wrote:
> I completely agree on that. While having component (drivers) and
> architecture specific knowledge in the kernel definitely makes sense,
> such board specific details do not belong in the kernel, or it will make
> the kernel very hard to maintain.

yes, I recall that when I proposed putting this kind of mother-board
specific stuff in Linux, at the first linuxbios summit in 2005, people
were ready to shoot me. This is the kind of stuff that has appeared in
the OLPC kernel. And, it makes ports of other OSes -- in my case, Plan
9 and Inferno -- a major pain in the neck. Doable, but not at all fun.

ron

[LinuxBIOS] AMD Geode LX VSA and VSMs

[Peter Stuge]

On Thu, May 03, 2007 at 09:39:27AM -0600, Jordan Crouse wrote:
> > Would it make sense to move parts or all of the VSM code into the
> > operating system?
>
> Thats what OFW does for OLPC - and its fraught with danger.  Case
> in point?  A few days ago, the amount of video memory was doubled
> in OFW, to 16MB.  But since the PCI spoofing happens in the kernel,
> it didn't get the message that the video memory changed, and the
> PCI BAR was still sized to 8MB, and X goes boom.

Oh, no, that's not what I meant.

I meant that the code in the kernel would be completely native to the
hardware. No spoofing.
> This is intelligence (or insanity, depending on your point of
> view),

I'm in the latter camp. :p (Even though I understand many of the
benefits.)
> that very much belongs in the firmware - the kernel shouldn't need
> to know how any of this works.

Well it does have drivers and drivers know the hardware behavior so
it can't be all wrong. Life would of course suck if the native
hardware interface is "suboptimal."

I guess this is also why I'm interested in what devices are provided
by the VSMs.

//Peter

[LinuxBIOS] AMD Geode LX VSA and VSMs

[Jordan Crouse]

On 04/05/07 02:09 +0200, Peter Stuge wrote:
> On Thu, May 03, 2007 at 09:39:27AM -0600, Jordan Crouse wrote:
> > > Would it make sense to move parts or all of the VSM code into the
> > > operating system?
> >
> > Thats what OFW does for OLPC - and its fraught with danger.  Case
> > in point?  A few days ago, the amount of video memory was doubled
> > in OFW, to 16MB.  But since the PCI spoofing happens in the kernel,
> > it didn't get the message that the video memory changed, and the
> > PCI BAR was still sized to 8MB, and X goes boom.
>
> Oh, no, that's not what I meant.
>
> I meant that the code in the kernel would be completely native to the
> hardware. No spoofing.

So what would handle the several dozen MSRs needed to set up routing -
some of which are for essential devices that don't have drivers?   And
we would have to invent a new bus just for Geode devices (some of which
share code with other entities - amd74xxx IDE for example), because without
PCI, you wouldn't be able to match vendor/device IDs, or control the
devices, or assign I/O or memory resources in virtual space, at least 
not easily.

So basically it would take the Geode from a pretty well supported platform
to one that would be completely custom and on the fringe, and certainly
not suitable for the mainstream kernel.  I think the SMM handler is a small
price to pay. :)

Jordan

[LinuxBIOS] AMD Geode LX VSA and VSMs

[Peter Stuge]

On Thu, May 03, 2007 at 06:28:27PM -0600, Jordan Crouse wrote:
> > I meant that the code in the kernel would be completely native
> > to the hardware. No spoofing.
>
> So what would handle the several dozen MSRs needed to set up
> routing - some of which are for essential devices that don't
> have drivers?

Good question. I guess most of the world depends on PCI today?

There's HT, but I've understood that it works a lot like PCI.

There's VIA's V-Link too. Will be interesting to see how that
works out in the C7 port. (Sorry Corey, don't know anything
except that it's a proprietary north-south interconnect.)
> And we would have to invent a new bus just for Geode
> devices (some of which share code with other entities - amd74xxx
> IDE for example),

Well, the new bus was invented by the hardware designers.
(NatSemi or maybe even Cyrix I guess.)

It's interesting because it's a first. The Geodes are really
different.
> because without PCI, you wouldn't be able to match vendor/device
> IDs, or control the devices, or assign I/O or memory resources in
> virtual space, at least not easily.

Yes, I guess it would be a completely new architecture, since that's
what the hardware is after all, except that it's still x86. :)
> So basically it would take the Geode from a pretty well supported
> platform to one that would be completely custom and on the fringe,
> and certainly not suitable for the mainstream kernel.  I think the
> SMM handler is a small price to pay. :)

I understand that completely. If geode-vsa is as critical as you say
then there is certainly no other option in the foreseeable future.

(But someone (Tom?) wrote something to give me the impression that
the LX would actually run well also without geode-vsa?)

//Peter

[Uwe Hermann]

On Tue, May 01, 2007 at 06:10:54PM -0600, Marc Jones wrote:
> > > In addition to the patches you will need the Geode LX VSA binary that is
> > > located here:
> > >
> > > http://www.amd.com/files/connectivitysolutions/geode/geode_lx/lx_vsa.36k.bin...
> >
> > Where's the source code? SCNR :)
> >
> > I assume the source is not publically available? That would sure be
> > great! If not, what exact usage rights come with the binary?
>
> The VSA binary source is LGPL and is available at: 
> http://dev.laptop.org/git.do?p=geode-vsa

Wow! Now I'm impressed. This is really great news!

Uwe.

[Stefan Reinauer]

* Uwe Hermann  [070503 12:01]:
> > The VSA binary source is LGPL and is available at: 
> > http://dev.laptop.org/git.do?p=geode-vsa
>
> Wow! Now I'm impressed. This is really great news!

This code has been out for quite a while, and it is really great stuff
although it will be hard for most LinuxBIOS developers to compile it
themselfes. It means that we can build binary images in the build system
and have them prepacked with the VSA code though, making deployment of
LinuxBIOS for the Geode LX platform very easy for the users.

OFW does not use the VSA at all anymore (as far as I know, please
correct me if I am wrong), since running the modules was slowing down
the boot process quite a bit (compared to the rest of the boot time at
least)
So one question is in my mind: Can we implement the setup done by VSA 
as native LinuxBIOS code, and does it make sense? What are the draw
backs in such a scenario?

Stefan

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Jordan Crouse]

On 03/05/07 18:42 +0200, Stefan Reinauer wrote:
> Uwe Hermann  [070503 12:01]:
> > > The VSA binary source is LGPL and is available at: 
> > > http://dev.laptop.org/git.do?p=geode-vsa
> >
> > Wow! Now I'm impressed. This is really great news!
>
> This code has been out for quite a while, and it is really great stuff
> although it will be hard for most LinuxBIOS developers to compile it
> themselfes. It means that we can build binary images in the build system
> and have them prepacked with the VSA code though, making deployment of
> LinuxBIOS for the Geode LX platform very easy for the users.
>
> OFW does not use the VSA at all anymore (as far as I know, please
> correct me if I am wrong), since running the modules was slowing down
> the boot process quite a bit (compared to the rest of the boot time at
> least)

Reports of VSA slowness have been greatly exaggerated.  the main concern
is that its not compilable by mere mortals, so it can't be changed 
and optimized.  Once we have the VSA code ported to GNU tools, that will
be much easier.

Also, remember that the whole process was made easier by the fact that
OFW+OLPC is a very specialized platform - it just isn't intended to
change - so much so that we can hard code PCI BAR assignments and sizes.
Its a bit more difficult to implement this sort of process when you have
to worry about half a dozen different platforms that might implement 
slightly different models and scenarios.
> So one question is in my mind: Can we implement the setup done by VSA 
> as native LinuxBIOS code, and does it make sense? What are the draw
> backs in such a scenario?

In a sanely operating system, you really need the SMM to handle the PCI
interaction - using a PCI spoofing system like OLPC does is useful for a
heavily embedded platform, but it really falls down for typical systems -
having something solid responding to CF8/CFC is way more re-assuring.
Once you agree to this, then most of VSA starts to make sense.  I agree,
a single binary blob that can't be hacked on is frustrating, but the
effort to change that is in progress.  I think that once its all GNUified,
everybody will be happy with it.

Jordan

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Richard Smith]

Jordan Crouse wrote:
> Also, remember that the whole process was made easier by the fact that
> OFW+OLPC is a very specialized platform - it just isn't intended to
> change - so much so that we can hard code PCI BAR assignments and sizes.
> Its a bit more difficult to implement this sort of process when you have
> to worry about half a dozen different platforms that might implement 
> slightly different models and scenarios.

Jordan speaks true.  The OLPC is much more of an embedded system than a 
normal PC.  Taking advantage of that has allowed us to do some of the 
things that you just can't do on a general purpose mainboard.

Very little of the OFW early init is dynamic.  Its essentially a big 
table that we just blast into the MSR's.  We can do that because we own 
the hardware platform and can guarantee what hardware will be present.

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Carl-Daniel Hailfinger]

On 03.05.2007 18:55, Jordan Crouse wrote:
> In a sanely operating system, you really need the SMM to handle the PCI
> interaction - using a PCI spoofing system like OLPC does is useful for a
> heavily embedded platform, but it really falls down for typical systems -
> having something solid responding to CF8/CFC is way more re-assuring.
> Once you agree to this, then most of VSA starts to make sense.  I agree,
> a single binary blob that can't be hacked on is frustrating, but the
> effort to change that is in progress.  I think that once its all GNUified,
> everybody will be happy with it.

The concept of code not under the control of the operating system is
frightening some low-latency audio/video folks. If the operating system
uses some operations heavily which trigger SMM execution, extended
periods of switched off interrupts may result.
OTOH, systems which need SMM should probably not be used anyway if
latency is critical.

Regards,
Carl-Daniel

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Stefan Reinauer]

* Carl-Daniel Hailfinger  [070503 19:16]:
> The concept of code not under the control of the operating system is
> frightening some low-latency audio/video folks. If the operating system
> uses some operations heavily which trigger SMM execution, extended
> periods of switched off interrupts may result.

Yes, anyone doing real time systems has a problem with this.
> OTOH, systems which need SMM should probably not be used anyway if
> latency is critical.

They can not. This is the reason a lot of people are using LinuxBIOS
rather than legacy bios.

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Carl-Daniel Hailfinger]

On 03.05.2007 19:17, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger  [070503 19:16]:
> > The concept of code not under the control of the operating system is
> > frightening some low-latency audio/video folks. If the operating system
> > uses some operations heavily which trigger SMM execution, extended
> > periods of switched off interrupts may result.
>
> Yes, anyone doing real time systems has a problem with this.
> > OTOH, systems which need SMM should probably not be used anyway if
> > latency is critical.
>
> They can not. This is the reason a lot of people are using LinuxBIOS
> rather than legacy bios.

How do we deal with fan control, then? Most recent mainboards use
SMM for fan control. Once you forbid SMM, you have to trust the OS
to perform fan control correctly, which will fail if the machine
crashes or locks up.

Regards,
Carl-Daniel

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Richard Smith]

Carl-Daniel Hailfinger wrote:
> How do we deal with fan control, then? Most recent mainboards use
> SMM for fan control. Once you forbid SMM, you have to trust the OS
> to perform fan control correctly, which will fail if the machine
> crashes or locks up.

Fans are mechanical and will always fail.  If your hardware dies because 
your fan is off its a hardware flaw not a software issue.

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Carl-Daniel Hailfinger]

On 03.05.2007 19:29, Richard Smith wrote:
> Carl-Daniel Hailfinger wrote:
> > How do we deal with fan control, then? Most recent mainboards use
> > SMM for fan control. Once you forbid SMM, you have to trust the OS
> > to perform fan control correctly, which will fail if the machine
> > crashes or locks up.
>
> Fans are mechanical and will always fail.  If your hardware dies because 
> your fan is off its a hardware flaw not a software issue.

Agreed. In the not too distant past, there were processors from
at least one major vendor which failed permanently if the attached
fan failed. Thermal diodes were not that common in past mainstream
x86 processors, and even those processors which had such diodes
did not necessarily slow down/halt on overheat conditions.

The Geode will probably never get hot enough for failure, but
a top-of-the line x86 processor with >120W TDP might have problems.

@AMD: Do we need to enable any specific features/MSRs in Athlon64
processors for overheating protection or is that functionality
always available?

Regards,
Carl-Daniel

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Marc Jones]

Carl-Daniel Hailfinger wrote:
> On 03.05.2007 19:17, Stefan Reinauer wrote:
> > Carl-Daniel Hailfinger  [070503 19:16]:
> > > The concept of code not under the control of the operating system is
> > > frightening some low-latency audio/video folks. If the operating system
> > > uses some operations heavily which trigger SMM execution, extended
> > > periods of switched off interrupts may result.
> >
> > Yes, anyone doing real time systems has a problem with this.
> > > OTOH, systems which need SMM should probably not be used anyway if
> > > latency is critical.
> >
> > They can not. This is the reason a lot of people are using LinuxBIOS
> > rather than legacy bios.
>
> How do we deal with fan control, then? Most recent mainboards use
> SMM for fan control. Once you forbid SMM, you have to trust the OS
> to perform fan control correctly, which will fail if the machine
> crashes or locks up.
>
> Regards,
> Carl-Daniel

In the legacy/APM world power management and fan control were mostly 
done in SMM.

In the ACPI world that has been moved to the OS. Proper drivers and 
applications and SMM all play a part but SMM's role is greatly reduced 
and latency much less of an issue. You might also want to look at the 
OpenIPMI project to see how some of this is being done now.
http://openipmi.sourceforge.net/IPMI.pdf

Marc

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Carl-Daniel Hailfinger]

On 03.05.2007 19:45, Marc Jones wrote:
> In the legacy/APM world power management and fan control were mostly 
> done in SMM.
>
> In the ACPI world that has been moved to the OS. Proper drivers and 
> applications and SMM all play a part but SMM's role is greatly reduced 
> and latency much less of an issue. You might also want to look at the 
> OpenIPMI project to see how some of this is being done now.
> http://openipmi.sourceforge.net/IPMI.pdf

Thanks for the pointer! However, the paper suggests that an extra
controller/processor is needed for IPMI. Do we have such a thing
on recent x86 mainboards?

Regards,
Carl-Daniel

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Ward Vandewege]

On Thu, May 03, 2007 at 08:37:55PM +0200, Carl-Daniel Hailfinger wrote:
> On 03.05.2007 19:45, Marc Jones wrote:
> > In the legacy/APM world power management and fan control were mostly 
> > done in SMM.
> >
> > In the ACPI world that has been moved to the OS. Proper drivers and 
> > applications and SMM all play a part but SMM's role is greatly reduced 
> > and latency much less of an issue. You might also want to look at the 
> > OpenIPMI project to see how some of this is being done now.
> > http://openipmi.sourceforge.net/IPMI.pdf
>
> Thanks for the pointer! However, the paper suggests that an extra
> controller/processor is needed for IPMI. Do we have such a thing
> on recent x86 mainboards?

Some do. It's usually an optional component for server boards.

I have had fairly extensive dealing with IPMI on Supermicro and Tyan boards,
and to be honest, these things are pathetic. There are IPMI 'standards' (v1,
v1.5, v2), which never seem to be implemented properly. In my experience, the
IPMI cards lock up, crash, become unresponsive, and are so poorly implemented
that they often require the use of - even buggier - proprietary tools to even
talk to the things; the free software ipmitool is a great piece of software,
but it's hard having to work around IPMI implemenations that are broken in
undocumented and unpredictable ways. Hence, getting ipmitool to work with a
particular IPMI card is very much a game of hit and miss.

And don't get me started on IPMI cards sharing physical network connections
with the mainboard - in some implementations they piggyback on the onboard
ethernet controller and just pick up whatever traffic they need from the
wire, whereas on other boards they actually have a separate ethernet
controller on the same socket (!). Of course one can configure the mac and ip
address for the IPMI card in *all* the implementations I've seen, leading to
interesting situations where sometimes the mac address for the IPMI card
*has* to be the same as the one for the onboard ethernet interface, and
sometimes it *may not* be the same.

Best of all - the whole point of IPMI is out of band management of machines.
Get this: I've seen machines crash *and take the IPMI daughterboard with
them*. IPMI daugtherboards obviously rely on some parts of the host system to
remain in a non-locked up state, which kind of goes against the whole point
of having IPMI in the first place...

On paper, IPMI is a great idea. The implementations I've seen suck royally.
Proprietary software...

Thanks,
Ward.

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Peter Stuge]

On Thu, May 03, 2007 at 03:01:29PM -0400, Ward Vandewege wrote:
[.. IPMI experience ..]
> On paper, IPMI is a great idea. The implementations I've seen suck
> royally.

Too bad. :(

I am appreciating the PowerPC coprocessor in some IBM eServers that
speaks serial, also when the server is powered off, even more now.

//Peter

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Stefan Reinauer]

* Peter Stuge  [070504 02:18]:
> > On paper, IPMI is a great idea. The implementations I've seen suck
> > royally.
>
> Too bad. :(
>
> I am appreciating the PowerPC coprocessor in some IBM eServers that
> speaks serial, also when the server is powered off, even more now.

Sun has these too, on the boards made by Newisys.

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Ward Vandewege]

On Fri, May 04, 2007 at 09:25:46PM +0200, Stefan Reinauer wrote:
> Peter Stuge  [070504 02:18]:
> > > On paper, IPMI is a great idea. The implementations I've seen suck
> > > royally.
> >
> > Too bad. :(
> >
> > I am appreciating the PowerPC coprocessor in some IBM eServers that
> > speaks serial, also when the server is powered off, even more now.
>
> Sun has these too, on the boards made by Newisys.

Yeah. There's a whole different class of hardware like HP's ILO, Dell's DRAC,
and IBM and Sun's offerings mentioned above. These things are much more
serious than IPMI, but often not quite bug free (HP's ILO for instance
doesn't do Explicit Congestion Notification right, and the web interface is,
well, not the most reliable...). But they are more reliable than any IPMI
imlementation I've seen, that's for sure. They still suffer from the fact
that they are little proprietary machines that behave in sometimes
unpredictable ways, and that can not be fixed by anyone but the manufacturer.
Proprietary software...

Thanks,
Ward.

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Uwe Hermann]

On Thu, May 03, 2007 at 03:01:29PM -0400, Ward Vandewege wrote:
> > Thanks for the pointer! However, the paper suggests that an extra
> > controller/processor is needed for IPMI. Do we have such a thing
> > on recent x86 mainboards?
>
> Some do. It's usually an optional component for server boards.
>
> I have had fairly extensive dealing with IPMI on Supermicro and Tyan boards,
> and to be honest, these things are pathetic. There are IPMI 'standards' (v1,
> v1.5, v2), which never seem to be implemented properly. In my experience, the
> IPMI cards lock up, crash, become unresponsive, and are so poorly implemented
> that they often require the use of - even buggier - proprietary tools to even
> talk to the things; the free software ipmitool is a great piece of software,
> but it's hard having to work around IPMI implemenations that are broken in
> undocumented and unpredictable ways. Hence, getting ipmitool to work with a
> particular IPMI card is very much a game of hit and miss.
>
> And don't get me started on IPMI cards sharing physical network connections
> with the mainboard - in some implementations they piggyback on the onboard
> ethernet controller and just pick up whatever traffic they need from the
> wire, whereas on other boards they actually have a separate ethernet
> controller on the same socket (!). Of course one can configure the mac and ip
> address for the IPMI card in *all* the implementations I've seen, leading to
> interesting situations where sometimes the mac address for the IPMI card
> *has* to be the same as the one for the onboard ethernet interface, and
> sometimes it *may not* be the same.
>
> Best of all - the whole point of IPMI is out of band management of machines.
> Get this: I've seen machines crash *and take the IPMI daughterboard with
> them*. IPMI daugtherboards obviously rely on some parts of the host system to
> remain in a non-locked up state, which kind of goes against the whole point
> of having IPMI in the first place...
>
> On paper, IPMI is a great idea. The implementations I've seen suck royally.
> Proprietary software...

This text looks suspiciously well-suited for the wiki, hint hint ;)

Uwe.

[Carl-Daniel Hailfinger]

On 03.05.2007 18:42, Stefan Reinauer wrote:
> > > The VSA binary source is LGPL [...]
>
> OFW does not use the VSA at all anymore (as far as I know, please
> correct me if I am wrong), since running the modules was slowing down
> the boot process quite a bit (compared to the rest of the boot time at
> least)

According to Mitch Bradley, switching away from VSA saved ~10 seconds
during early bootup.
> So one question is in my mind: Can we implement the setup done by VSA 
> as native LinuxBIOS code, and does it make sense? What are the draw
> backs in such a scenario?

I'd like to split the VSA into "useful" chunks and "unneeded" chunks.
VGA/sound emulation is now unnecessary since Linux has drivers for
the native hardware. Bootloaders might want VGA, though.
However, PCI emulation makes some things much easier IMO.

Regards,
Carl-Daniel

[Stefan Reinauer]

* Carl-Daniel Hailfinger  [070503 19:03]:
> According to Mitch Bradley, switching away from VSA saved ~10 seconds
> during early bootup.

This makes me think there was something pretty much broken.
The GX1 I have here does not even need 10s before it starts loading the
OS, and it has VSA in place (not LinuxBIOS though)
> I'd like to split the VSA into "useful" chunks and "unneeded" chunks.
> VGA/sound emulation is now unnecessary since Linux has drivers for
> the native hardware. Bootloaders might want VGA, though.
> However, PCI emulation makes some things much easier IMO.

So do distributions. Loading a geodefb in a non-embedded platform is
most likely not going to happen, unless someone tunes the system.

[Carl-Daniel Hailfinger]

On 03.05.2007 19:10, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger  [070503 19:03]:
> > According to Mitch Bradley, switching away from VSA saved ~10 seconds
> > during early bootup.
>
> This makes me think there was something pretty much broken.
> The GX1 I have here does not even need 10s before it starts loading the
> OS, and it has VSA in place (not LinuxBIOS though)

I may have misunderstood his mail back then.
However, switching from LinuxBIOS(+)VSA to OFW(-)VSA reduced time from
poweron to active display by ~13 seconds.
> > I'd like to split the VSA into "useful" chunks and "unneeded" chunks.
> > VGA/sound emulation is now unnecessary since Linux has drivers for
> > the native hardware. Bootloaders might want VGA, though.
> > However, PCI emulation makes some things much easier IMO.
>
> So do distributions. Loading a geodefb in a non-embedded platform is
> most likely not going to happen, unless someone tunes the system.

Can we detect that something uses VGA and enable the VGA VSA on demand?

Regards,
Carl-Daniel

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Jordan Crouse]

On 03/05/07 19:21 +0200, Carl-Daniel Hailfinger wrote:
> Can we detect that something uses VGA and enable the VGA VSA on demand?

There will be no VSA VGA support ever.  We can't redistribute it.

Jordan

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Stefan Reinauer]

* Jordan Crouse  [070503 19:50]:
> On 03/05/07 19:21 +0200, Carl-Daniel Hailfinger wrote:
> > Can we detect that something uses VGA and enable the VGA VSA on demand?
>
> There will be no VSA VGA support ever.  We can't redistribute it.

How does that impact the use of the VGA output?

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Peter Stuge]

On Fri, May 04, 2007 at 10:10:55AM +0200, Stefan Reinauer wrote:
> > There will be no VSA VGA support ever.  We can't redistribute it.
>
> How does that impact the use of the VGA output?

Graphics requires a native Geode framebuffer driver.
There's one at least for Linux.

//Peter

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Stefan Reinauer]

* Peter Stuge  [070504 17:26]:
> On Fri, May 04, 2007 at 10:10:55AM +0200, Stefan Reinauer wrote:
> > > There will be no VSA VGA support ever.  We can't redistribute it.
> >
> > How does that impact the use of the VGA output?
>
> Graphics requires a native Geode framebuffer driver.
> There's one at least for Linux.

But that is the same with or without VSA, is it not?

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Peter Stuge]

On Fri, May 04, 2007 at 09:29:20PM +0200, Stefan Reinauer wrote:
> > > > There will be no VSA VGA support ever.  We can't redistribute it.
> > >
> > > How does that impact the use of the VGA output?
> >
> > Graphics requires a native Geode framebuffer driver.
> > There's one at least for Linux.
>
> But that is the same with or without VSA, is it not?

With a VGA VSM vesafb could be used.

//Peter

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Stefan Reinauer]

* Peter Stuge  [070505 02:27]:
> > But that is the same with or without VSA, is it not?
>
> With a VGA VSM vesafb could be used.

I thought vesafb requires bios callbacks?

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Jordan Crouse]

On 06/05/07 11:45 +0200, Stefan Reinauer wrote:
> Peter Stuge  [070505 02:27]:
> > > But that is the same with or without VSA, is it not?
> >
> > With a VGA VSM vesafb could be used.
>
> I thought vesafb requires bios callbacks?

It does.  But why use vesafb, when you can use a native Geode framebuffer?
Its faster, it can handle non VESA modes, and it understands how to power
down the system much more efficiently.  Plus, we have the potential to
accelerate the drawing functions, which is a plus when you get up to very
large dimensions like 1940x1600.

Jordan

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Peter Stuge]

On Sun, May 06, 2007 at 10:00:12AM -0600, Jordan Crouse wrote:
> > > > But that is the same with or without VSA, is it not?
> > >
> > > With a VGA VSM vesafb could be used.
> >
> > I thought vesafb requires bios callbacks?
>
> It does.  But why use vesafb, when you can use a native Geode
> framebuffer?

Yes, absolutely. Native is always better.

//Peter

[Hamish Guthrie]

> According to Mitch Bradley, switching away from VSA saved ~10 seconds
> during early bootup.

Interesting - a while ago when I implemented VSA code into LinuxBIOS on 
a GX platform, my entire boot time was 9.5 seconds, which by this 
calculation means that LinuxBIOS and loading a kernel would have taken 
-0.5 seconds. Serious though, I found a negligible impact on boot times 
with/without VSA code.

I do not buy that argument.

Hamish

[Tom Sylla]

Uwe Hermann wrote:
> The LX-based OLPC should become another subdirectory of olpc/, just like
> rev_a and btest, right? I'd rather not touch the existing directories if
> the changes are that massive. This way we wouldn't break any targets
> (just add a new one), correct?

For those not following OLPC closely, OFW has replaced LB as the 
bootloader on OLPC, starting with B3 (the first LX version). OFW-only 
was prototyped on B2, too (GX).

Making an B3 OLPC target might be sort of an interesting exercise, but 
it won't really end up getting used for anything.

[Uwe Hermann]

On Wed, May 02, 2007 at 12:18:12AM -0400, Tom Sylla wrote:
> Uwe Hermann wrote:
> > The LX-based OLPC should become another subdirectory of olpc/, just like
> > rev_a and btest, right? I'd rather not touch the existing directories if
> > the changes are that massive. This way we wouldn't break any targets
> > (just add a new one), correct?
>
> For those not following OLPC closely, OFW has replaced LB as the 
> bootloader on OLPC, starting with B3 (the first LX version). OFW-only 
> was prototyped on B2, too (GX).
>
> Making an B3 OLPC target might be sort of an interesting exercise, but 
> it won't really end up getting used for anything.

Maybe it won't get shipped, but that doesn't mean it won't get used.
OLPC-users/-developers can flash any firmware they like, correct?

Uwe.

[Richard Smith]

Uwe Hermann wrote:
> Maybe it won't get shipped, but that doesn't mean it won't get used.
> OLPC-users/-developers can flash any firmware they like, correct?

Yes. After you request and receive a developer key.

[Stefan Reinauer]

* Richard Smith  [070503 17:37]:
> Uwe Hermann wrote:
> > Maybe it won't get shipped, but that doesn't mean it won't get used.
> > OLPC-users/-developers can flash any firmware they like, correct?
>
> Yes. After you request and receive a developer key.

Where/how can this be done?

[Richard Smith]

Stefan Reinauer wrote:
> > > Maybe it won't get shipped, but that doesn't mean it won't get used.
> > > OLPC-users/-developers can flash any firmware they like, correct?
> >
> > Yes. After you request and receive a developer key.
>
> Where/how can this be done?

Currently not necessary because the security code is not in place.  But 
  Somewhere in the B3 - B4. It will start showing up.

The infrastructure for requesting this is also not yet setup.  But 
eventualy it will be filling out a web form and then waiting some period 
  and it will show up in e-mail.

[Gregg C Levine]

Hello!
Welcome to the list, Marc Jones and to you Jordan Crouse as well.
Next question, regarding the Norwich platform, how would I be able to obtain
one when it's ready?

Essentially I am an embedded programmer, by trade, but of course some would
call it for fun, and am looking at a new platform to work with. The Geode
happens to be an interesting processor design.
--
Gregg C Levine [e-mail]
"The Force will be with you. Always." Obi-Wan Kenobi
> -----Original Message-----
> From: [e-mail]

[mailto:[e-mail]] On
> Behalf Of Marc Jones
> Sent: Tuesday, May 01, 2007 6:48 PM
> To: [e-mail]
> Subject: [LinuxBIOS] [patch 0/4] AMD Geode LX support for LinuxBIOS
>
> Hello LinuxBIOS Community,
>
> My name is Marc Jones and I work for the AMD embedded group. Jordan
> Crouse and I have been working with Ron Minnich on a Geode LX LinuxBIOS
> implementation for the AMD Norwich development platform. The Norwich
> platform should be a good starting point for all current and future
> Geode LX platforms.
>
> Our implementation has been split into four patches: cpu, northbridge,
> southbridge, and mainboard. All four are required to build the Norwich
> platform. Ron and I expect this to break the current OLPC mainboards. We
> will work on fixing then soon (Note that OLPC went from GX to LX so an
> update was required regardless).
>
> In addition to the patches you will need the Geode LX VSA binary that is
> located here:

http://www.amd.com/files/connectivitysolutions/geode/geode_lx/lx_vsa.36k.bin
.gz
> You might find it helpful to use BuildROM to build the Norwich platform.
> BuildROM builds LinuxBIOS, builds a payload (etherboot, filo, or
> memtest), and bundles in the LX VSA to make one ROM image. Jordan Crouse
> will be sending out patches and instructions for buildROM soon.
>
> I look forward to working with you all.
>
> Marc

[LinuxBIOS] AMD Geode LX support for LinuxBIOS

[Jordan Crouse]

On 01/05/07 22:51 -0400, Gregg C Levine wrote:
> Hello!
> Welcome to the list, Marc Jones and to you Jordan Crouse as well.
> Next question, regarding the Norwich platform, how would I be able to obtain
> one when it's ready?

The norwich is an internal development platform - it is a good starting
point because its the most complete and versatile Geode platform we have -
it supports virtually every single option available in commercial Geode
platforms.  We chose it because it provides a good basis for other developers
to add their own mainboards - its always easier to remove the options
you don't have, then to try to figure out how to enable new ones.

If you are interested in a Geode platform, there are many alternatives 
available.  This catalog is a good start:

http://wwwd.amd.com/catalog/salescat.nsf/shopsearchview?SearchView&Query...

Thats not the only list, there are other commercial Geodes available, 
like this, for example:

http://linutop.com/shop

And more are coming every day.  Now that the support is out there, we're
in a position to support Geode vendors if they are interested in adapting
the code to their platforms.  The more testers, the better.. :)

Jordan

[Uwe Hermann]

Hi,

I ran abuild on all the targets after applying the four patches. Here
are the results. Apart from the boards which are currently not building
correctly, these new boards will be broken if the patches are applied as is:

Processing mainboard/amd/rumba (i386: ok, we're amd64)
macro MSR_SB already defined

Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64)
POST_CODE undeclared

Processing mainboard/lippert/frontrunner (i386: ok, we're amd64)
/home/uwe/lb/LinuxBIOSv2/src/northbridge/amd/gx2/grphinit.c:24: error: redefinition of "vrRead"
/home/uwe/lb/LinuxBIOSv2/src/include/cpu/amd/vr.h:494: error: previous definition of "vrRead" was here
make[1]: *** [grphinit.o] Error 1

Processing mainboard/olpc/btest (i386: ok, we're amd64)
macro MSR_SB already defined

Processing mainboard/olpc/rev_a (i386: ok, we're amd64)
macro MSR_SB already defined

Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64)
POST_CODE undeclared

We should fix the patches to not break the other targets.

Uwe.