Asus M2V-MX SE: Resume from S3 broken: `CBFS: ERROR: No file header found at 0x0 - try next aligned address: 0x40.`
Dear coreboot folks,
using coreboot with the attached configuration (with CBMEM) on the Asus M2V-MX SE [1], resume from S3 does not work for me.
$ more serial.log […] [ 818.013737] PM: Syncing filesystems ... done. [ 818.021643] (NULL device *): firmware: agent loaded rt2870.bin into memory [ 818.028721] Freezing user space processes ... (elapsed 0.01 seconds) done. [ 818.050706] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. [ 818.070691] Suspending console(s) (use no_console_suspend to debug)
coreboot-4.0-5045-g0fd505b Tue Dec 17 00:36:07 CET 2013 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x0, freq=0x5, needs_reset=0x1 dev2 old_freq=0x0, freq=0x5, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 01K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 01ht reset - soft reset
coreboot-4.0-5045-g0fd505b Tue Dec 17 00:36:07 CET 2013 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change toggle LDTSTP# done Current fid_cur: 0x2, fid_max: 0xa Requested fid_new: 0xa FidVid table step fidvid: 0xa toggle LDTSTP# done toggle LDTSTP# done Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cfee0 Device error Device error Enabling dual channel memory Unbuffered 400MHz 400MHz set_ecc: ECC disabled Interleaved RAM end at 0x00200000 kB Ram3 IN TEST WAKEUP 400Wakeup! before resume errata #125 before exit errata - timer enabled before exit errata - after mdelay pcidev is 8000c290 after exit errata Exiting memory from self refresh: done DQS RESTORE FROM NVRAM: c2000 Loading 113222 of size 4 to nvram pos:0 Loading 18181718 of size 4 to nvram pos:4 Loading 17171617 of size 4 to nvram pos:8 Loading 16 of size 1 to nvram pos:12 Loading 202520 of size 4 to nvram pos:13 Loading 14141413 of size 4 to nvram pos:17 Loading 16141415 of size 4 to nvram pos:21 Loading 14 of size 1 to nvram pos:25 Loading 29 of size 1 to nvram pos:26 Loading 0 of size 1 to nvram pos:27 Loading 0 of size 1 to nvram pos:28 Loading 0 of size 1 to nvram pos:29 Loading 113222 of size 4 to nvram pos:30 Loading 18171717 of size 4 to nvram pos:34 Loading 16161717 of size 4 to nvram pos:38 Loading 17 of size 1 to nvram pos:42 Loading 202520 of size 4 to nvram pos:43 Loading 14151514 of size 4 to nvram pos:47 Loading 15151414 of size 4 to nvram pos:51 Loading 14 of size 1 to nvram pos:55 Loading 2c of size 1 to nvram pos:56 Loading 0 of size 1 to nvram pos:57 Loading 0 of size 1 to nvram pos:58 Loading 0 of size 1 to nvram pos:59 Loading 7410809b of size 4 to nvram pos:60 Mem running ! Ram4 v_esp=000cff28 IN TEST WAKEUP 400IN TEST WAKEUP 400CBMEM region 7dec0000-7dffffff (cbmem_reinit) IN TEST WAKEUP 400Will copy coreboot region to: 7dedc200 Copying data from cache to RAM -- switching to use RAM as stack... Done Disabling cache as ram now Clearing initial memory region: Loading image. CBFS: ERROR: No file header found at 0x0 - try next aligned address: 0x40.
It then just hangs there.
$ sudo ./cbmem -l CBMEM table of contents: ID START LENGTH 0. FREE SPACE 7dfe4200 0001be00 1. GDT 7dec0200 00000200 2. CONSOLE 7dec0400 00010000 3. TIME STAMP 7ded0400 00000200 4. ACPI 7ded0600 0000b400 5. SMBIOS 7dedba00 00000800 6. ACPI RESUME 7dedc200 00100000 7. COREBOOT 7dfdc200 00008000 $ sudo cbmem -t # truncated with the error message 10 entries total:
10:start of ramstage Could not open /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq: No such file or directory
Thanks,
Paul
Hi Paul,
I think I have seen your previous log that get_top_of_mem() was missing. maybe someone broke it some time ago. I did not try with this board since I have the new fm2 board.
The get_top_of_ram() is in early_car.c in southbridge/via/k8t890
It has still CONFIG_HAVE_ACPI_RESUME I seen some efforts of removing this... Not sure what is the state now.
Please check if you dont see the messages WARNING: you need to define get_top_of_ram()
The top of ram mechanism is quite simple. Since this chipset has integrated VGA it is not possible to just read TOP or TOM2 MSR. Instead during the initialization a top of ram is written via backup_top_of_ram() to the NVRAM at offset K8T890_NVRAM_TOP_OF_RAM.
You could also check if you are not hitting some errata of the CPU or if CBMEM console does not interfere.
Thanks
Rudolf
On 18.12.2013 09:43, Paul Menzel wrote:
Dear coreboot folks,
using coreboot with the attached configuration (with CBMEM) on the Asus M2V-MX SE [1], resume from S3 does not work for me.
$ more serial.log […] [ 818.013737] PM: Syncing filesystems ... done. [ 818.021643] (NULL device *): firmware: agent loaded rt2870.bin into memory [ 818.028721] Freezing user space processes ... (elapsed 0.01 seconds) done. [ 818.050706] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. [ 818.070691] Suspending console(s) (use no_console_suspend to debug) coreboot-4.0-5045-g0fd505b Tue Dec 17 00:36:07 CET 2013 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x0, freq=0x5, needs_reset=0x1 dev2 old_freq=0x0, freq=0x5, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 01K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 01ht reset - soft reset coreboot-4.0-5045-g0fd505b Tue Dec 17 00:36:07 CET 2013 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change toggle LDTSTP# done Current fid_cur: 0x2, fid_max: 0xa Requested fid_new: 0xa FidVid table step fidvid: 0xa toggle LDTSTP# done toggle LDTSTP# done Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cfee0 Device error Device error Enabling dual channel memory Unbuffered 400MHz 400MHz set_ecc: ECC disabled Interleaved RAM end at 0x00200000 kB Ram3 IN TEST WAKEUP 400Wakeup! before resume errata #125 before exit errata - timer enabled before exit errata - after mdelay pcidev is 8000c290 after exit errata Exiting memory from self refresh: done DQS RESTORE FROM NVRAM: c2000 Loading 113222 of size 4 to nvram pos:0 Loading 18181718 of size 4 to nvram pos:4 Loading 17171617 of size 4 to nvram pos:8 Loading 16 of size 1 to nvram pos:12 Loading 202520 of size 4 to nvram pos:13 Loading 14141413 of size 4 to nvram pos:17 Loading 16141415 of size 4 to nvram pos:21 Loading 14 of size 1 to nvram pos:25 Loading 29 of size 1 to nvram pos:26 Loading 0 of size 1 to nvram pos:27 Loading 0 of size 1 to nvram pos:28 Loading 0 of size 1 to nvram pos:29 Loading 113222 of size 4 to nvram pos:30 Loading 18171717 of size 4 to nvram pos:34 Loading 16161717 of size 4 to nvram pos:38 Loading 17 of size 1 to nvram pos:42 Loading 202520 of size 4 to nvram pos:43 Loading 14151514 of size 4 to nvram pos:47 Loading 15151414 of size 4 to nvram pos:51 Loading 14 of size 1 to nvram pos:55 Loading 2c of size 1 to nvram pos:56 Loading 0 of size 1 to nvram pos:57 Loading 0 of size 1 to nvram pos:58 Loading 0 of size 1 to nvram pos:59 Loading 7410809b of size 4 to nvram pos:60 Mem running ! Ram4 v_esp=000cff28 IN TEST WAKEUP 400IN TEST WAKEUP 400CBMEM region 7dec0000-7dffffff (cbmem_reinit) IN TEST WAKEUP 400Will copy coreboot region to: 7dedc200 Copying data from cache to RAM -- switching to use RAM as stack... Done Disabling cache as ram now Clearing initial memory region: Loading image. CBFS: ERROR: No file header found at 0x0 - try next aligned address: 0x40.It then just hangs there.
$ sudo ./cbmem -l CBMEM table of contents: ID START LENGTH 0. FREE SPACE 7dfe4200 0001be00 1. GDT 7dec0200 00000200 2. CONSOLE 7dec0400 00010000 3. TIME STAMP 7ded0400 00000200 4. ACPI 7ded0600 0000b400 5. SMBIOS 7dedba00 00000800 6. ACPI RESUME 7dedc200 00100000 7. COREBOOT 7dfdc200 00008000 $ sudo cbmem -t # truncated with the error message 10 entries total: 10:start of ramstage Could not open /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq: No such file or directoryThanks,
Paul
On 12/21/2013 07:44 PM, Rudolf Marek wrote:
Hi Paul,
I think I have seen your previous log that get_top_of_mem() was missing. maybe someone broke it some time ago. I did not try with this board since I have the new fm2 board.
The get_top_of_ram() is in early_car.c in southbridge/via/k8t890
It has still CONFIG_HAVE_ACPI_RESUME I seen some efforts of removing this... Not sure what is the state now.
Please check if you dont see the messages WARNING: you need to define get_top_of_ram()
The function is indeed missing from ramstage but that is not relevant here. In the logs I have seen, S3 resume path finds valid CBMEM region.
This is flagged as a warning because ramstage has no early access to CBMEM storage. For example, CBMEM console is first collected in low memory and later copied to CBMEM area.
The top of ram mechanism is quite simple. Since this chipset has integrated VGA it is not possible to just read TOP or TOM2 MSR. Instead during the initialization a top of ram is written via backup_top_of_ram() to the NVRAM at offset K8T890_NVRAM_TOP_OF_RAM.
Actually, get_top_of_ram() on this platform is a complex beast. With GFXUMA, this should be a simple function of total amount of memory installed, and this is managed without any nvram use on Intel platforms.
Second case, one without GFXUMA, is the complicated one. Probably doable without nvram too if it had pre-defined IO window allocation below 4GB.
I have some work started to get this, and EARLY_CBMEM_INIT or DYNAMIC_CBMEM for AMD platforms.
You could also check if you are not hitting some errata of the CPU or if CBMEM console does not interfere.
We did pickup some possible CBMEM console interference from SeaBIOS, but we did not hit that problem here.
Thanks
Rudolf
Kyösti
Dear coreboot folks,
the issue is still not solved, so here is an update.
First of all, my thanks go to Kyösti for helping me debug this issue in #coreboot on <irc.freenode.net>.
According to Kyösti there is fairly strong evidence of RAM / stack corruption during S3 resume.
Memtest 5.00b5 successfully passed twice run from GRUB 2 on hard disk with coreboot and SeaBIOS payload. I’ll still have to test resume from S3 with other memory modules.
Kyösti pushed a AMD K8/Fam 10h CAR rewrite to Gerrit [1]. Additionally he provided the attached diff [2] to capture a stacktrace. Please find my logs with `PRINT_IN_CAR` set to 0 and 1 attached.
Testing from other owners of the Asus M2V-MX SE would be very helpful as resume from suspend to RAM was supposedly working in the past for them.
Thanks,
Paul
[1] http://review.coreboot.org/#/c/4583/ [2] http://dpaste.com/1530246/ (Use `sp++` instead of `sp += 4`.)
On 01/01/2014 06:46 PM, Paul Menzel wrote:
Dear coreboot folks,
the issue is still not solved, so here is an update.
First of all, my thanks go to Kyösti for helping me debug this issue in #coreboot on <irc.freenode.net>.
According to Kyösti there is fairly strong evidence of RAM / stack corruption during S3 resume.
Memtest 5.00b5 successfully passed twice run from GRUB 2 on hard disk with coreboot and SeaBIOS payload. I’ll still have to test resume from S3 with other memory modules.
Kyösti pushed a AMD K8/Fam 10h CAR rewrite to Gerrit [1]. Additionally he provided the attached diff [2] to capture a stacktrace. Please find my logs with `PRINT_IN_CAR` set to 0 and 1 attached.
What the traces suggested is RAM access being unstable on S3 resume. With stack moved to RAM, we saw issues like returning to incorrect EIP from function calls and local variables getting wiped. A single build could fail at numerous different ways.
Leaving RAM un-cacheable (not setting variable MTRR of [0x0 - RAMTOP[ to write-back) when resuming from S3 seems to solve the problem of halting in middle of romstage. On S3 resume it now loads ramstage and fails at the time of MTRR (re-)programming. This is where it would set RAM to write-back cacheable.
Testing from other owners of the Asus M2V-MX SE would be very helpful as resume from suspend to RAM was supposedly working in the past for them.
And with different memory configuration and different CPU, those may work like they did before. And the particular configuration of memory you have may never have been tested for S3 resume until now.
We can compare memory controller parameters on power-on and S3 resume and hopefully we locate the significant difference in register programming there. JEDEC sequencing bringing DIMMs out of self-refresh needs to be investigated too.
Kyösti
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Kyösti Mälkki -
Paul Menzel -
Rudolf Marek