Intel i5000 Port - coreboot

26 Jan 2009

Hi List,
i've started a port of coreboot to the Intel i5000 Chipset
(http://www.intel.com/products/server/chipsets/5000p/5000p-overview.htm)
last week.
The board i'm developing is a Supermicro X7DB8, with one QuadCore E5335
Xeon. There's not much working right now, with exception of the SuperIO chip,
and basic CPU CAR setup (i'm using the Core2Duo code at the moment).
Currently work is going on at the FBDIMM setup and Memory Controller
initialization. I'm attaching the current diff, but you should consider
that as non-working code. I wouldn't send it to the list, if not Carl
Daniel would have requested me to do so :)
Index: southbridge/intel/i63xx/i63xx.c
===================================================================

--- southbridge/intel/i63xx/i63xx.c	(revision 0)
+++ southbridge/intel/i63xx/i63xx.c	(revision 0)
@@ -0,0 +1 @@
+#include<irq_tables.h>
Index: southbridge/intel/i63xx/Makefile
===================================================================
--- southbridge/intel/i63xx/Makefile	(revision 0)
+++ southbridge/intel/i63xx/Makefile	(revision 0)
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_63XX),y)
+
+STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i63xx/common.c
+
+STAGE0_CHIPSET_SRC +=
+
+
+endif
Index: Kconfig
===================================================================
--- Kconfig	(revision 1123)
+++ Kconfig	(working copy)
@@ -117,6 +117,8 @@
    boolean
 config NORTHBRIDGE_INTEL_I945
    boolean
+config NORTHBRIDGE_INTEL_I5000
+	boolean
# Southbridges:
 config SOUTHBRIDGE_AMD_CS5536
@@ -148,6 +150,8 @@
    boolean
 config SOUTHBRIDGE_INTEL_I82801GX
    boolean
+config SOUTHBRIDGE_INTEL_I5000
+	boolean
# Super I/Os:
 config SUPERIO_WINBOND_W83627HF
Index: mainboard/Kconfig
===================================================================
--- mainboard/Kconfig	(revision 1123)
+++ mainboard/Kconfig	(working copy)
@@ -43,6 +43,11 @@
    help
      Select this option for various systems from AMP.
+config VENDOR_SUPERMICRO
+	bool "Supermicro"
+	help
+	  Select this option for various systems from Supermicro.
+
 config VENDOR_ARTECGROUP
    bool "Artec Group"
    help
@@ -90,6 +95,7 @@
 source "mainboard/kontron/Kconfig"
 source "mainboard/pcengines/Kconfig"
 source "mainboard/via/Kconfig"
+source "mainboard/supermicro/Kconfig"
choice
    prompt "ROM chip size"
Index: mainboard/supermicro/Kconfig
===================================================================
--- mainboard/supermicro/Kconfig	(revision 0)
+++ mainboard/supermicro/Kconfig	(revision 0)
@@ -0,0 +1,40 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_SUPERMICRO
+
+config BOARD_SUPERMICRO_X7DB8
+	bool "X7DB8"
+	select ARCH_X86
+	select CPU_INTEL_CORE2
+	select NORTHBRIDGE_INTEL_I5000
+	select SOUTHBRIDGE_INTEL_I5000
+	select SUPERIO_WINBOND_W83627HF
+	help
+	  Supermicro X7DV8 Dual Xeon (Socket 771) Board
+
+endchoice
+
+config MAINBOARD_DIR
+       string
+       default supermicro/x7db8
+       depends BOARD_SUPERMICRO_X7DB8
Index: mainboard/supermicro/x7db8/initram.c
===================================================================
--- mainboard/supermicro/x7db8/initram.c	(revision 0)
+++ mainboard/supermicro/x7db8/initram.c	(revision 0)
@@ -0,0 +1,335 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define _MAINOBJECT
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+#include <i5000_mch.h>
+
+#define SERIAL_DEV      W83627HF_SP1
+#define SERIAL_IOBASE   0x3f8
+
+static u8 spd_banks[] = { 4, 8, 16, 32 };
+static u8 spd_cas[8] = { 9, 10, 11, 0, 0, 0, 0, 0 };
+static u8 spd_ras[8] = { 12, 13, 14, 15, 16, 17, 18, 19 };
+static u8 spd_width[8] = { 4, 8, 16, 32, 0, 0, 0, 0 };
+static u8 spd_ranks[8] = { 0, 1, 2, 0, 0, 0, 0, 0 };
+
+static u8 const gpiodata[] = {
+	0xcf, 0x79, 0x0c, 0xff, 0xff, 0xff, 0x00, 0xe7,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbf, 0x65,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x8a, 0x71, 0x00, 0x00,
+	0x06, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00,
+	0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+static int crc16 (u8 *ptr, int count)
+{
+    int crc, i;
+    crc = 0;
+    while (--count >= 0) {
+	    crc = crc ^ (int)*ptr++ << 8;
+	    for (i = 0; i < 8; ++i)
+		    if (crc & 0x8000)
+			    crc = crc << 1 ^ 0x1021;
+		    else
+			    crc = crc << 1;
+    }
+    return (crc & 0xFFFF);
+}
+
+static int spd_read_byte(const int branch, const int channel,
+			 const int dimm, const u8 addr, u8 *val)
+{
+	u16 status;
+	const int dev = branch ? 22 : 21;
+
+	pci_conf1_write_config32(PCI_BDF(0, dev, 0),
+				 channel ? I5000_MCH_SPDCMD1 : I5000_MCH_SPDCMD0,
+				 0xa8000000 | (dimm & 0x03) << 24 | addr << 16);
+
+	for(;;) {
+		status = pci_conf1_read_config16(
+			PCI_BDF(0, dev, 0),
+			channel ? I5000_MCH_SPD1 : I5000_MCH_SPD0);
+
+		if (status & I5000_MCH_SPD_SBE)
+			break;
+
+		if (status & I5000_MCH_SPD_BUSY)
+			continue;
+
+		if (status & I5000_MCH_SPD_RDO) {
+			*val = status & 0xff;
+			return 0;
+		}
+	}
+	return -1;
+}
+
+static void i5000_reset_fbdimm(void)
+{
+	/* Branch1 reset follows Branch0 */
+	pci_conf1_write_config8(PCI_BDF(0, 22, 0), I5000_MCH_FBDRST0, 4);
+	/* Assert SOFTCORERESET# and CORERESET# */
+	pci_conf1_write_config8(PCI_BDF(0, 21, 0), I5000_MCH_FBDRST0, 0);
+	/* Deassert SOFTCORERESET */
+	pci_conf1_write_config8(PCI_BDF(0, 21, 0), I5000_MCH_FBDRST0, 1);
+	/* Assert SOFTCORERESET# and CORERESET# */
+	pci_conf1_write_config8(PCI_BDF(0, 21, 0), I5000_MCH_FBDRST0, 0);
+	/* Deassert both lines */
+       	pci_conf1_write_config8(PCI_BDF(0, 21, 0), I5000_MCH_FBDRST0, 3);
+}
+
+static void i5000_setup_rcba(void)
+{
+	u32 gcs;
+
+	pci_conf1_write_config32(PCI_BDF(0, 31, 0), 0xf0,
+				 I5000_RCBA_BASE | I5000_RCBA_ENABLE);
+
+	gcs = *(u32 *)(I5000_RCBA(I5000_GCS));
+	gcs |= 1; /* Prevent BUC.TS from beeing changed */
+	gcs &= 0xfb; /* Forward BIOS Cycles to LPC */
+	*(u32 *)(I5000_RCBA(I5000_GCS)) = gcs;
+}
+
+static void i5000_setup_io(void)
+{
+	u16 tmp;
+
+	pci_conf1_write_config32(PCI_BDF(0, 30, 0), I5000_MCH_IOBASE_LIMIT, 0x10);
+
+	/* Enable PCI I/O */
+	tmp = pci_conf1_read_config16(PCI_BDF(0, 30, 0), 0x04);
+	tmp |= 0x01;
+	pci_conf1_write_config32(PCI_BDF(0, 30, 0), 0x04, tmp | 0x01);
+}
+
+static int i5000_init_amb(int branch, int channel, int dimm, int maxwait, int state)
+{
+	u32 pci_dev = PCI_BDF(0, branch ? 22 : 21, 0);
+	u32 fbdists, fbicmd;
+
+	if (channel) {
+		fbdists = I5000_MCH_FBDISTS1;
+		fbicmd = I5000_MCH_FBDICMD1;
+	} else {
+		fbdists = I5000_MCH_FBDISTS0;
+		fbicmd = I5000_MCH_FBDICMD0;
+	}
+
+/*	printk(BIOS_DEBUG, "%s: %d/%d/%d: %02x\n", __func__,
+	       branch, channel, dimm, state);
+*/
+	pci_conf1_write_config8(pci_dev, fbicmd, state);
+
+
+	while(maxwait--)
+		if(pci_conf1_read_config16(pci_dev, fbdists) == 0x1fff)
+			return 0;
+
+	printk(BIOS_ERR, "calibration failed (branch %d, channel %d, dimm %d, res 0x%04x)\n",
+	       branch, channel, dimm, pci_conf1_read_config16(pci_dev, fbdists));
+	return -1;
+}
+
+static void i5000_fbdimm_nextstate(const int branch, const int channel,
+				  const int dimm, const int state)
+{
+	pci_conf1_write_config8(PCI_BDF(0, branch ? 22 : 21, 0),
+				channel ? I5000_MCH_FBDHPC0 : I5000_MCH_FBDHPC0, state);
+}
+
+static int i5000_fbdimm_init(const int branch, const int channel, const int dimm)
+{
+
+	i5000_fbdimm_nextstate(branch, channel, dimm, 0x00);
+	i5000_fbdimm_nextstate(branch, channel, dimm, 0x10);
+
+	if (i5000_init_amb(branch, channel, dimm, 0xfffff, I5000_MCH_FBDIMM_TS0) == -1)
+		return -1;
+
+	if (i5000_init_amb(branch, channel, dimm, 0xfffff, I5000_MCH_FBDIMM_TS1) == -1)
+		return -1;
+
+	if (i5000_init_amb(branch, channel, dimm, 0xfffff, I5000_MCH_FBDIMM_TS2) == -1)
+		return -1;
+
+	if (i5000_init_amb(branch, channel, dimm, 0xfffff, I5000_MCH_FBDIMM_TS3) == -1)
+		return -1;
+
+	i5000_fbdimm_nextstate(branch, channel, dimm, 0x20);
+	i5000_fbdimm_nextstate(branch, channel, dimm, 0x30);
+
+	return 0;
+}
+
+int main(void)
+{
+	/* [BRANCH][CHANNEL][DIMM] */
+	u16 dimmsizes[2][2][4];
+	int branch, channel, dimm, addr, banks, cas, ras, ranks, width;
+	u8 spddata[0x80];
+	u16 type, vendor, device;
+	u32 mtr;
+	u16 totalmem = 0;
+	volatile int i;
+
+	post_code(POST_START_OF_MAIN);
+	printk(BIOS_DEBUG, "Initializing memory\n");
+
+	if (pci_conf1_read_config16(PCI_BDF(0, 0, 0), 0) != 0x8086) {
+		printk(BIOS_ERR, "Unknown chipset (vendor unknown)\n");
+		return -1;
+	}
+
+	type = pci_conf1_read_config16(PCI_BDF(0, 0, 0), 2);
+
+	switch(type) {
+	case I5000_MCH_ID_5000P:
+		printk(BIOS_INFO, "Intel 5000P MCH detected\n");
+		break;
+	case I5000_MCH_ID_5000Z:
+		printk(BIOS_INFO, "Intel 5000Z MCH detected\n");
+		break;
+	case I5000_MCH_ID_5000V:
+		printk(BIOS_INFO, "Intel 5000V MCH detected\n");
+		break;
+	case I5000_MCH_ID_5000X:
+		printk(BIOS_INFO, "Intel 5000X MCH detected\n");
+		break;
+	default:
+		printk(BIOS_ERR, "Unknown chipset!\n");
+		return 1;
+	}
+
+	i5000_setup_rcba();
+	i5000_setup_io();
+
+	/* Set GPIOBAE to 1180 */
+	pci_conf1_write_config16(PCI_BDF(0, 31, 0), 0x48, 0x1180);
+	/* Enable GPIO */
+	pci_conf1_write_config16(PCI_BDF(0, 31, 0), 0x4c,
+				 pci_conf1_read_config16(PCI_BDF(0, 31, 0), 0x4c) | 0x10);
+
+	/* Write (yet unknown) GPIO data */
+	for(i = 0; i < 64; i++)
+		outb(gpiodata[i], 0x1180+i);
+
+	for(i = 0; i < 0x20; i++) {
+		vendor = pci_conf1_read_config16(PCI_BDF(0, i, 0), 0x00);
+		device = pci_conf1_read_config16(PCI_BDF(0, i, 0), 0x02);
+
+		if (vendor == 0xffff || device == 0xffff)
+			continue;
+
+		printk(BIOS_INFO, "%02d: %04x:%04x CMD=0x%04x STS=0x%04x\n", i, vendor, device,
+		       pci_conf1_read_config16(PCI_BDF(0, i, 0), 0x04),
+		       pci_conf1_read_config16(PCI_BDF(0, i, 0), 0x06));
+	}
+
+	printk(BIOS_INFO, "detecting Memory:\n");
+
+	i5000_reset_fbdimm();
+
+	for(branch = 0; branch < 2; branch++) {
+		for(channel = 0; channel < 2; channel++) {
+			for(dimm = 0; dimm < 4; dimm++) {
+				for(addr = 0; addr < 0x80; addr++)
+					if (spd_read_byte(branch, channel, dimm, addr, spddata + addr) == -1)
+						break;
+
+				if (addr != 0x80)
+					break;
+
+				if (crc16(spddata, spddata[0] & 0x80 ? 117 : 126) != (spddata[127] << 8 | spddata[126])) {
+					printk(BIOS_INFO, "*** SPD has invalid checksum ***");
+					continue;
+				}
+
+				banks = spd_banks[spddata[4] & 0x03];
+				ras = spd_ras[(spddata[4] >> 5) & 0x07];
+				cas = spd_cas[(spddata[4] >> 2) & 0x07];
+				width = spd_width[spddata[7] & 0x07];
+				ranks = spd_ranks[(spddata[7] >> 3) & 0x07];
+
+				printk(BIOS_DEBUG, "Branch %d, Channel %d, DIMM %d: %d MB (RAS:%d CAS:%d BANKS:%d WIDTH:%d RANKS:%d)",
+				       branch, channel, dimm,
+				       (1 << (ras + cas + banks + ranks) >> 20), ras, cas, banks, width, ranks);
+
+				totalmem += (1 << (ras + cas + banks + ranks) >> 20);
+
+				mtr = ranks == 2 ? (1 << 4) : 0;
+				mtr |= banks == 8 ? (1 << 5) : 0;
+				mtr |= width == 8 ? (1 << 6) : 0;
+				mtr |= 0x100; /* We assume the DIMMs are compatible for now */
+
+				switch(ras) {
+				case 13:
+					break;
+				case 14:
+					mtr |= (1 << 2);
+					break;
+				case 15:
+					mtr |= (1 << 3);
+					break;
+				default:
+					printk(BIOS_ERR, "RAS %d not supported\n", ras);
+					break;
+				}
+
+				switch(cas) {
+				case 10:
+					break;
+				case 11:
+					mtr |= 1;
+					break;
+				case 12:
+					mtr |= (1 << 1);
+					break;
+				default:
+					printk(BIOS_ERR, "CAS %d not supported\n", ras);
+					break;
+				}
+
+				pci_conf1_write_config16(PCI_BDF(0, branch ? 22 : 21, 0), 0x80 | (dimm << 2), mtr);
+//				printk(BIOS_DEBUG, "Vendor/Dev: 0x%08x ", *(u32 *)0xfe000000);
+
+				if (i5000_fbdimm_init(branch, channel, dimm) == -1) {
+				}
+				printk(BIOS_INFO, "\n");
+			}
+		}
+	}
+	printk(BIOS_INFO, "Total Memory detected: %d MB\n", totalmem);
+	return 0;
+}
Index: mainboard/supermicro/x7db8/stage1.c
===================================================================
--- mainboard/supermicro/x7db8/stage1.c	(revision 0)
+++ mainboard/supermicro/x7db8/stage1.c	(revision 0)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+#include <i63xx.h>
+
+#define SERIAL_DEV W83627HF_SP1
+#define SERIAL_IOBASE 0x3f8
+
+void hardware_stage1(void)
+{
+	post_code(POST_STAGE1_MAIN);
+	/* Enable LPC decoding for: Super I/O and COM1 */
+	pci_conf1_write_config16(PCI_BDF(0, 0x1f, 0), I63XX_LPC_EN,
+				 I63XX_LPC_EN_CNF1 | I63XX_LPC_EN_COMA);
+	void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase);
+	w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
+}
+
+void mainboard_pre_payload(void)
+{
+}
Index: mainboard/supermicro/x7db8/i63xx.h
===================================================================
--- mainboard/supermicro/x7db8/i63xx.h	(revision 0)
+++ mainboard/supermicro/x7db8/i63xx.h	(revision 0)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef INTEL_63XX_H
+#define INTEL_63XX_H
+
+#define	I63XX_LPC_EN	0x82
+
+#define I63XX_LPC_EN_CNF1	0x1000
+#define I63XX_LPC_EN_MC		0x0800
+#define I63XX_LPC_EN_KBC	0x0400
+#define I63XX_LPC_EN_GAMEH	0x0200
+#define I63XX_LPC_EN_GAMEL	0x0100
+#define I63XX_LPC_EN_FDD	0x0008
+#define I63XX_LPC_EN_LPT	0x0004
+#define I63XX_LPC_EN_COMB	0x0002
+#define I63XX_LPC_EN_COMA	0x0001
+
+#define I63XX_LPC_GPIOBASE	0x48
+
+#endif
Index: mainboard/supermicro/x7db8/dts
===================================================================
--- mainboard/supermicro/x7db8/dts	(revision 0)
+++ mainboard/supermicro/x7db8/dts	(revision 0)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/{
+	mainboard_vendor = "Supermicro";
+	mainboard_name = "X7DB8";
+	cpus { };
+
+	domain@0 {
+		/config/("northbridge/intel/i5000/domain");
+		 pci@1f,0 {
+		 	/config/("southbridge/intel/i5000/i5000_lpc.dts");
+			ioport@2e {
+				  /config/("superio/winbond/w83627hf/dts");
+				  com1enable = "1";
+				  com1address = "0x3f8";
+				  com1irq = "4";
+			};
+		};
+	};
+};
+
Index: mainboard/supermicro/x7db8/i5000_mch.h
===================================================================
--- mainboard/supermicro/x7db8/i5000_mch.h	(revision 0)
+++ mainboard/supermicro/x7db8/i5000_mch.h	(revision 0)
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef INTEL_5000_MCH_H
+#define INTEL_5000_MCH_H
+
+#define I5000_MCH_FBDICMD0	0x46
+#define I5000_MCH_FBDICMD1	0x47
+#define I5000_MCH_FBDST		0x4b
+#define I5000_MCH_FBDHPC0	0x4f
+#define I5000_MCH_FBDRST0	0x53
+#define I5000_MCH_FBDISTS0	0x58
+#define I5000_MCH_FBDISTS1	0x5a
+#define I5000_MCH_AMBPRESENT	0x64
+#define I5000_MCH_MTR00		0x80
+#define I5000_MCH_MTR01		0x84
+#define I5000_MCH_MTR02		0x88
+#define I5000_MCH_MTR03		0x8c
+
+#define I5000_MCH_MC		0x40
+
+
+#define I5000_MCH_ID_5000P	0x25c8
+#define I5000_MCH_ID_5000Z	0x25d0
+#define I5000_MCH_ID_5000V	0x25d4
+#define I5000_MCH_ID_5000X	0x25d8
+
+#define I5000_MCH_SPD0	0x74
+#define I5000_MCH_SPD1	0x76
+
+
+#define I5000_MCH_SPD_RDO	0x8000
+#define I5000_MCH_SPD_WOD	0x4000
+#define I5000_MCH_SPD_SBE	0x2000
+#define I5000_MCH_SPD_BUSY	0x1000
+
+#define I5000_MCH_SPDCMD0	0x78
+#define I5000_MCH_SPDCMD1	0x7c
+
+#define I5000_MCH_MCA		0x58
+#define I5000_MCH_MCA_SCHDIMM	0x4000
+
+#define I5000_MCH_DDRFREQ	0x56
+#define I5000_MCH_DDRFREQ_11	0x00
+#define I5000_MCH_DDRFREQ_45	0x02
+#define I5000_MCH_DDRFREQ_54	0x03
+
+#define I5000_MCH_AMBSELECT	0x54
+#define I5000_MCH_MAXCH		0x56
+#define I5000_MCH_MAXDIMMPERCH	0x57
+
+#define I5000_RCBA_BASE		0xfed1c000
+#define I5000_RCBA_ENABLE	0x00000001
+
+#define I5000_RCBA(x) (I5000_RCBA_BASE | (x))
+#define I5000_GCS		0x3410
+
+#define I5000_MCH_IOBASE_LIMIT	0x1c
+
+#define I5000_MCH_FBDIMM_TS0	0x00
+#define I5000_MCH_FBDIMM_TS1	0x10
+#define I5000_MCH_FBDIMM_TS2	0x20
+#define I5000_MCH_FBDIMM_TS3	0x30
+#define I5000_MCH_FBDIMM_TS4	0x00
+#endif
Index: mainboard/supermicro/x7db8/irq_tables.h
===================================================================
--- mainboard/supermicro/x7db8/irq_tables.h	(revision 0)
+++ mainboard/supermicro/x7db8/irq_tables.h	(revision 0)
@@ -0,0 +1,74 @@
+/* This file was generated by getpir.c, do not modify!
+ * (but if you do, please run checkpir on it to verify)
+ *
+ * Contains the IRQ Routing Table dumped directly from your
+ * memory, which BIOS sets up.
+ *
+ * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
+ */
+
+#ifdef GETPIR
+#include "pirq_routing.h"
+#else
+#include <arch/x86/pirq_routing.h>
+#endif
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*31,	 /* There can be total 31 devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0,		 /* IRQs devoted exclusively to PCI usage */
+	0x8086,		 /* Vendor */
+	0x122e,		 /* Device */
+	0,		 /* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xc0,		 /* u8 checksum. This has to be set to some
+			    value that would give 0 after the sum of all
+			    bytes for this structure (including checksum) */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x02,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x03,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x04,(0x01<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}}, 0x1, 0x0},
+		{0x04,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x7, 0x0},
+		{0x03,(0x00<<3)|0x2, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x05,(0x01<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x2, 0x0},
+		{0x02,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x06,(0x00<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x8, 0x0},
+		{0x06,(0x00<<3)|0x1, {{0x00, 0xdef8}, {0x63, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x8, 0x0},
+		{0x01,(0x00<<3)|0x3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x07,(0x01<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x3, 0x0},
+		{0x00,(0x04<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x08,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x6, 0x0},
+		{0x00,(0x06<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x09,(0x00<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}}, 0x5, 0x0},
+		{0x00,(0x08<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x00,(0x10<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0},
+		{0x00,(0x11<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0},
+		{0x00,(0x13<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0},
+		{0x00,(0x15<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0},
+		{0x00,(0x16<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0},
+		{0x00,(0x1c<<3)|0x0, {{0x61, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x0a,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x4, 0x0},
+		{0x00,(0x1d<<3)|0x0, {{0x61, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x60, 0x1ef8}}, 0x0, 0x0},
+		{0x00,(0x1e<<3)|0x0, {{0x61, 0x1ef8}, {0x68, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0},
+		{0x0b,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x9, 0x0},
+		{0x0b,(0x01<<3)|0x0, {{0x62, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x60, 0x1ef8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
+
+unsigned long stage0_copy_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
Index: mainboard/supermicro/x7db8/Makefile
===================================================================
--- mainboard/supermicro/x7db8/Makefile	(revision 0)
+++ mainboard/supermicro/x7db8/Makefile	(revision 0)
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
+
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c
+
+STAGE2_MAINBOARD_SRC = 
+
+$(obj)/coreboot.vpd:
+	$(Q)printf "  BUILD   DUMMY VPD\n"
+	$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
+
Index: mainboard/supermicro/x7db8/cmos.layout
===================================================================
--- mainboard/supermicro/x7db8/cmos.layout	(revision 0)
+++ mainboard/supermicro/x7db8/cmos.layout	(revision 0)
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
Index: northbridge/intel/i5000/i5000.h
===================================================================
--- northbridge/intel/i5000/i5000.h	(revision 0)
+++ northbridge/intel/i5000/i5000.h	(revision 0)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_INTEL_I5000_H
+#define NORTHBRIDGE_INTEL_I5000_H
+
+#include <device/device.h>
+
+#endif
Index: northbridge/intel/i5000/northbridge
===================================================================
--- northbridge/intel/i5000/northbridge	(revision 0)
+++ northbridge/intel/i5000/northbridge	(revision 0)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "i5000_northbridge";
+};
Index: northbridge/intel/i5000/domain
===================================================================
--- northbridge/intel/i5000/domain	(revision 0)
+++ northbridge/intel/i5000/domain	(revision 0)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "i5000_domain";
+};
Index: northbridge/intel/i5000/Makefile
===================================================================
--- northbridge/intel/i5000/Makefile	(revision 0)
+++ northbridge/intel/i5000/Makefile	(revision 0)
@@ -0,0 +1,25 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Sven Schnelle svens@stackframe.org
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y)
+
+STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i5000/i5000.c
+
+endif
Index: northbridge/intel/i5000/i5000.c
===================================================================
--- northbridge/intel/i5000/i5000.c	(revision 0)
+++ northbridge/intel/i5000/i5000.c	(revision 0)
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2009 Sven Schnelle svens@stackframe.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <io.h>
+#include "i5000.h"
+#include <statictree.h>
+
+static int inb_cmos(int port)
+{
+}
+
+static void no_op(struct device *dev)
+{
+}
+
+static void i5000_read_resources(struct device *dev)
+{
+}
+
+static void i5000_ram_resources(struct device *dev)
+{
+}
+
+static void i5000_set_resources(struct device *dev)
+{
+}
+
+static void i5000_domain_read_resources(struct device *dev)
+{
+}
+
+static void i5000_domain_set_resources(struct device *dev)
+{
+}
+
+/* Here are the operations for when the northbridge is running a PCI domain. */
+/* See mainboard/emulation/qemu-x86 for an example of how these are used. */
+struct device_operations i5000_domain = {
+	.id = {.type = DEVICE_ID_PCI_DOMAIN,
+		{.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = pci_domain_scan_bus,
+	.phase4_read_resources	 = i5000_domain_read_resources,
+	.phase4_set_resources	 = i5000_domain_set_resources,
+	.phase5_enable_resources = enable_childrens_resources,
+	.phase6_init		 = no_op,
+	.ops_pci_bus		 = &pci_cf8_conf1,
+
+};
+
+/* Here are the operations for the northbridge. */
+struct device_operations i5000_northbridge = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = 0x8086,.device = 0x1237}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = NULL,
+	.phase4_read_resources	 = i5000_read_resources,
+	.phase4_set_resources	 = i5000_set_resources,
+	.phase5_enable_resources = no_op,
+	.phase6_init		 = no_op,
+	.ops_pci_bus		 = &pci_cf8_conf1,
+
+};

    