Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1745
-gerrit
commit c247c69ce76c5071a5c7d2e638df78ecf4ff81b7 Author: Duncan Laurie dlaurie@chromium.org Date: Sun Sep 9 20:12:32 2012 -0700
SPI: re-init SMM SPI driver after lockdown
If the driver is initialized before the lockdown then it will fail to work after the lockdown bit is set.
Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a Signed-off-by: Duncan Laurie dlaurie@chromium.org --- src/southbridge/intel/bd82x6x/finalize.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 7bd9f3f..1275725 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -23,6 +23,7 @@ #include <console/post_codes.h> #include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" +#include "spi.h"
void intel_pch_finalize_smm(void) { @@ -35,6 +36,9 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15));
+ /* Re-init SPI driver to handle locked BAR */ + spi_init(); + /* TCLOCKDN: TC Lockdown */ RCBA32_OR(0x0050, (1 << 31));