Hi, all. I downloaded flashrom from http://www.openbios.org/viewvc/trunk/util/flashrom.tar.gz?view=tar, also it was built correctly, when I scp it to an SIS530/SIS5595 board with debian-4.0r2, it just can't recognize my Winbond W49G002U EEPROM, here comes the verbose log:
Sis530:~# ./flashrom -c W49F002U Calibrating delay loop... OK. No coreboot table found. Found chipset "SIS5595", enabling flash write... OK. No EEPROM/flash device found. Sis530:~# ./flashrom -R flashrom r Sis530:~# ./flashrom --version flashrom r Sis530:~# ./flashrom -V -r Calibrating delay loop... 59M loops per second. OK. No coreboot table found. Found chipset "SIS5595", enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29LV040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At49F002(N), 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At49F002(N)T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for EN29F002(A)(N)T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for EN29F002(A)(N)B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0xff, id2 0xff Probing for MX29F002, 256 KB probe_29f002: id1 0xff, id2 0xff Probing for MX25L4005, 512 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L8005, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L3205, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for S25FL016A, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF040B, 512 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST29EE020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST28SF040A, 512 KB probe_28sf040: id1 0xff, id2 0xff Probing for SST39SF010A, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39VF020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL002, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for Pm49FL004, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for Pm25LV512, 64 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV010, 128 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV020, 256 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV040, 512 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV080B, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for W29C011, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C040P, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C020C, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W29EE011, 128 KB probe_w29ee011: id1 0xff, id2 0xff Probing for W49F002U, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W49V002A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W49V002FA, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040FA, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for W25x10, 128 KB generic_spi_command called, but no SPI chipset detected Probing for W25x20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for W25x40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for W25x80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M29F002B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F002T/NT, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F400BT, 512 KB probe_m29f400bt: id1 0xff, id2 0xff Probing for M50FLW040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080B, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW080, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW016, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M50LPW116, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W010B, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for M25P05-A, 64 KB generic_spi_command called, but no SPI chipset detected Probing for M25P10-A, 128 KB generic_spi_command called, but no SPI chipset detected Probing for M25P20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for M25P40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for M25P80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M25P16, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for M25P32, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for M25P64, 8192 KB generic_spi_command called, but no SPI chipset detected Probing for M25P128, 16384 KB generic_spi_command called, but no SPI chipset detected Probing for 82802ab, 512 KB probe_82802ab: id1 0xff, id2 0xff Probing for 82802ac, 1024 KB probe_82802ab: id1 0xff, id2 0xff Probing for F49B002UA, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for LHF00L04, 1024 KB probe_lhf00l04: id1 0xff, id2 0xff Probing for S29C51001T, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51002T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51004T, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C31004T, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for EON unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for MX unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for PMC unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for SST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for ST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected No EEPROM/flash device found. Sis530:~#
After quick reading of your source code, I saw this probing function: int probe_jedec(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; uint32_t largeid1, largeid2;
/* Issue JEDEC Product ID Entry command */ *(volatile uint8_t *)(bios + 0x5555) = 0xAA; myusec_delay(10); *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0x90; /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet, but it has been tested * to work reliably with 20 us. Allow a factor of 2 safety margin. */ myusec_delay(40);
/* Read product ID */ id1 = *(volatile uint8_t *)bios; id2 = *(volatile uint8_t *)(bios + 0x01); largeid1 = id1; largeid2 = id2;
/* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; id1 = *(volatile uint8_t *)(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; id2 = *(volatile uint8_t *)(bios + 0x101); largeid2 |= id2; }
/* Issue JEDEC Product ID Exit command */ *(volatile uint8_t *)(bios + 0x5555) = 0xAA; myusec_delay(10); *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0xF0; myusec_delay(40);
printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, largeid1, largeid2); if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id) return 1;
return 0; }
Seems flashrom routing got 0xff, 0xff on largeid1, largeid2. Has anybody tested this routing on SIS530? Thanks.
There is almost certainly an additional write control line on this board, and you will have to find it.
It's not too hard to do, let us know if you would like to try.
ron
On Sun, Mar 2, 2008 at 12:39 AM, ron minnich rminnich@gmail.com wrote:
There is almost certainly an additional write control line on this board, and you will have to find it.
It's not too hard to do, let us know if you would like to try.
ron
Sorry for my delay. I have a PCCHIP SIS530 board right in my hand, and datasheets for SIS530/SIS5595/W49F002U. but I haven't got any SCH or PCB files for this board, maybe I should read the W49F002U DS first?
when you talked about "an additional write control line on this board", do you mean it was not the problem caused by the BIOS chip? All SIS530/SIS5595 boards have the same problem? Would 'amiflash@Win32' or other flash routings have the same problem?
PS: the original BIOS chip for this board is ASD AE29F2008-12, It also can't be readed by flashrom(and the model was not listed in flashrom README file).
Can you guide me in a better direction? I will try my best on this test. Thanks.
On Mon, Mar 03, 2008 at 09:36:33AM +0800, Jun Ma wrote:
There is almost certainly an additional write control line on this board, and you will have to find it.
It's not too hard to do, let us know if you would like to try.
I have a PCCHIP SIS530 board right in my hand, and datasheets for SIS530/SIS5595/W49F002U.
Great! This is helpful.
but I haven't got any SCH or PCB files for this board, maybe I should read the W49F002U DS first?
Yes, that is a good start. Then probably the southbridge (5595?) to find out about GPIO pins.
when you talked about "an additional write control line on this board", do you mean it was not the problem caused by the BIOS chip?
Correct. Board vendors frequently connect a GPIO signal to the flash chip write protect input, in order to protect the flash chip from unintended writes.
All SIS530/SIS5595 boards have the same problem?
Each board vendor can use different GPIO signals, and some may choose to not use any GPIO but disable write protect by connecting it directly to logic 0 or 1, so that there is no "protection."
Would 'amiflash@Win32' or other flash routings have the same problem?
amiflash knows how to control this write protection, other flash routines may or may not. uniflash for example can call flash operations in the existing BIOS which know how to control the protection.
PS: the original BIOS chip for this board is ASD AE29F2008-12, It also can't be readed by flashrom(and the model was not listed in flashrom README file).
Ok, if it is not very different from the other supported flash chips it should not be very difficult to add.
Can you guide me in a better direction? I will try my best on this test.
In order to find out about the GPIO you can either: * Use a multimeter to check if any GPIO pin on the southbridge is connected to the flash chip write protect * Save all GPIO registers from booting with factory BIOS Compare with GPIO registers from booting with coreboot Set one GPIO register bit at a time and test if flashrom can identify the flash chip automatically. (That requires write to work correctly.)
Best regards
//Peter
when we worked out a board recently it was really easy.
David, Stefan and I did it.
What we did:
Use superiotoo to dump the superio. Look at GPIOs. Notice that one, and only one, GPIO was even enabled. And it was enabled as output.
So we looked at the output value, inverted it, and flashrom worked fine.
This was a few minutes of debugging. It took longer to modify superiotool to know about this particular superio than it took to figure out how to write enable flash :-)
You'll just need to dump the states of the GPIOs on the SiS part, see which ones are enabled, see which are enabled as outputs, and for a first try, just invert them all ... you can work out which one is controlling it bit by bit.
ron
What we did:
Use superiotoo to dump the superio. Look at GPIOs. Notice that one, and only one, GPIO was even enabled. And it was enabled as output.
So we looked at the output value, inverted it, and flashrom worked fine.
This was a few minutes of debugging. It took longer to modify superiotool to know about this particular superio than it took to figure out how to write enable flash :-)
You'll just need to dump the states of the GPIOs on the SiS part, see which ones are enabled, see which are enabled as outputs, and for a first try, just invert them all ... you can work out which one is controlling it bit by bit.
For my poor board with Super I/O chip ITE IT8770F, the superiotool outputs:
Sis530:~/superiotool# Sis530:~/superiotool# ./superiotool -V superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff No Super I/O found Sis530:~/superiotool#
I saw some comments here: /** * IT871[01]F and IT8708F use 0x87, 0x87 * IT8761F uses 0x87, 0x61, 0x55, 0x55/0xaa * IT86xxF series uses different ports * IT8661F uses 0x86, 0x61, 0x55/0xaa, 0x55/0xaa and 32 more writes * IT8673F uses 0x86, 0x80, 0x55/0xaa, 0x55/0xaa and 32 more writes */ static void enter_conf_mode_ite(uint16_t port) { outb(0x87, port); outb(0x01, port); outb(0x55, port); if (port == 0x2e) outb(0x55, port); else outb(0xaa, port); }
Not support IT8770F(I guessed)? also I haven't found any DS about IT8770F on internet, seems I am blind now..
On 03.03.2008 07:17, Jun Ma wrote:
What we did:
Use superiotoo to dump the superio. Look at GPIOs. Notice that one, and only one, GPIO was even enabled. And it was enabled as output.
So we looked at the output value, inverted it, and flashrom worked fine.
This was a few minutes of debugging. It took longer to modify superiotool to know about this particular superio than it took to figure out how to write enable flash :-)
You'll just need to dump the states of the GPIOs on the SiS part, see which ones are enabled, see which are enabled as outputs, and for a first try, just invert them all ... you can work out which one is controlling it bit by bit.
For my poor board with Super I/O chip ITE IT8770F, the superiotool outputs:
Sis530:~/superiotool# Sis530:~/superiotool# ./superiotool -V superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff No Super I/O found Sis530:~/superiotool#
I saw some comments here: /**
- IT871[01]F and IT8708F use 0x87, 0x87
- IT8761F uses 0x87, 0x61, 0x55, 0x55/0xaa
- IT86xxF series uses different ports
- IT8661F uses 0x86, 0x61, 0x55/0xaa, 0x55/0xaa and 32 more writes
- IT8673F uses 0x86, 0x80, 0x55/0xaa, 0x55/0xaa and 32 more writes
*/ static void enter_conf_mode_ite(uint16_t port) { outb(0x87, port); outb(0x01, port); outb(0x55, port); if (port == 0x2e) outb(0x55, port); else outb(0xaa, port); }
Not support IT8770F(I guessed)? also I haven't found any DS about IT8770F on internet, seems I am blind now..
Look for IT8661F. Someone wrote the IT8770F and the IT8761F are identical. But it is not easy to add support for it.
Regards, Carl-Daniel
but I haven't got any SCH or PCB files for this board, maybe I should read the W49F002U DS first?
Yes, that is a good start. Then probably the southbridge (5595?) to find out about GPIO pins.
when you talked about "an additional write control line on this board", do you mean it was not the problem caused by the BIOS chip?
Correct. Board vendors frequently connect a GPIO signal to the flash chip write protect input, in order to protect the flash chip from unintended writes.
[MJ] for my poor board SIS5595/W49F002U, there seems no WP# function, you can get DS from: http://www.winbond-usa.com/products/winbond_products/pdfs/Memory/w49f002u.pd...
Here are some discription about programming & hardware data protection on W49F002U :
Program Operation The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and two parameter blocks and/or boot block from "0" to "1") is needed before programming. The program operation is initiated by a 4-byte command code sequence (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (50 mS max. - TBP). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.
Hardware Data Protection The integrity of the data stored in the W49F002U is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation.
All SIS530/SIS5595 boards have the same problem?
Each board vendor can use different GPIO signals, and some may choose to not use any GPIO but disable write protect by connecting it directly to logic 0 or 1, so that there is no "protection."
[MJ] Understood, Thanks.
Would 'amiflash@Win32' or other flash routings have the same problem?
amiflash knows how to control this write protection, other flash routines may or may not. uniflash for example can call flash operations in the existing BIOS which know how to control the protection.
[MJ] Thanks, I am a new guy in x86/BIOS field. I choose flashrom because it is based on linux, while uniflash seems only have a win32 release.
PS: the original BIOS chip for this board is ASD AE29F2008-12, It also can't be readed by flashrom(and the model was not listed in flashrom README file).
Ok, if it is not very different from the other supported flash chips it should not be very difficult to add.
[MJ] because I have no more BIOS EEPROM chips in hand, I just tested W49F002U, after programming by a BIOS programmer, it also works on my board, :)
Can you guide me in a better direction? I will try my best on this test.
In order to find out about the GPIO you can either:
- Use a multimeter to check if any GPIO pin on the southbridge is
connected to the flash chip write protect
- Save all GPIO registers from booting with factory BIOS
Compare with GPIO registers from booting with coreboot Set one GPIO register bit at a time and test if flashrom can identify the flash chip automatically. (That requires write to work correctly.)
[MJ] I suppose that there has no WP# pin on W49F002U, so there should not have any GPIO pin connected between South bridge and BIOS.
Thank you for your excellecent help.
Best regards
//Peter
-- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On 03.03.2008 07:10, Jun Ma wrote:
[MJ] for my poor board SIS5595/W49F002U, there seems no WP# function, you can get DS from: http://www.winbond-usa.com/products/winbond_products/pdfs/Memory/w49f002u.pd...
There is a write protection function in the W49F002U: #WE, but the signal is inverted.
Can you guide me in a better direction? I will try my best on this test.
In order to find out about the GPIO you can either:
- Use a multimeter to check if any GPIO pin on the southbridge is
connected to the flash chip write protect
- Save all GPIO registers from booting with factory BIOS
Compare with GPIO registers from booting with coreboot Set one GPIO register bit at a time and test if flashrom can identify the flash chip automatically. (That requires write to work correctly.)
[MJ] I suppose that there has no WP# pin on W49F002U, so there should not have any GPIO pin connected between South bridge and BIOS.
See above.
Regards, Carl-Daniel
-
Carl-Daniel Hailfinger -
Jun Ma -
Peter Stuge -
ron minnich