On 07.11.2016 20:20, Charlotte Plusplus wrote:
On 11/6/16, Patrick Rudolph siro@das-labor.org wrote:
Am 06.11.2016 um 09:33 schrieb Charlotte Plusplus:
I am new to coreboot. I could try to add the missing power management states. But can I please ask for pointers and suggestions? What is missing? Is there any documentation?
Power management is done through ACPI. You'd need to figure out which ACPI functions are used by your operating system and implement/fix them.
I am using Linux, Arch or Ubuntu. I don't really understand what you mean there. I thought ACPI functions for power management were quite standard. After reading my dmesg, I thought the linux kernel PSTATE and CPUFREQ drivers were working fine. I need to do more tests with powertop.
CPU power management should be complete within coreboot and is usually not board specific (TDP limits may be but community driven coreboot ports often ignore that).
ACPI C-states are configured in the devicetree for Sandy/Ivy Bridge. P-states should be configured to the defaults for a given processor.
Is the power management state complete enough from coreboot standpoint to work with the current linux kernel??
Sure.
If not, could you point me to an Ivy Bridge board that has the most complete implementation of power management, so I can use it as an example?
If there is really something missing, it would be very board (or maybe ThinkPad) specific, I suppose. So nothing standard, hard to find an example. Sometimes there's something that can be configured at the OS level if the firmware haven't done so yet. Sometimes you need to disable a single device/chip when the system goes into a sleep state. Looking at the "tunables" in the powertop tool might be a good idea.
I see some boards have cstates support, like src/mainboard/lenovo/x200/cstates.c and after googling I found that libreboot had "Higher battery life on GM45 (X200, T400, T500, R400) due to higher cstates now being supported (thanks Arthur Heymans). C4 power states also supported. Higher battery life on i945 (X60, T60, MacBook2,1) due to better CPU C-state settings. (Deep C4, Dynamicl L2 shrinking, C2E).
Patch is in: https://notabug.org/vimuser/libreboot/commit/89819c5ce3cd5c9a38e9e7e817573dc...
However, I could not need documentation or explainations for the numbers used (which differ in coreboot and libreboot)
Some of the numbers are hints to the OS how much power would be saved by a given state / how long the latency is to get out of it. This is defined in the ACPI specification [1, p.381..]. The last 0x30 in that patch gives the number of the C-state, IIRC. coreboot actually uses C4, too, it's just using a weird register to tell the hardware to use C4 when C3 is requested (see 2a1847e lenovo/x200,t400: enable C4 cpu low power state). The 0x30 is an operand to the MWAIT instruction [2]. But again, this all should work fine for Ivy Bridge.
I have found http://www.intel.com/content/www/us/en/support/processors/000006619.html but that is not super helpful.
Well, most of Intel's public documentation is about how you make use of their technology from an OS perspective. There isn't much public docu- mentation about how the firmware configures things.
I would be happy to write proper power management support, but I would really appreciate some links to the documentation or some examples.
A related question: how do I write a ACPI method to receive a call from userland and do something on coreboot side, like write a register? I would like to add a way to turn the NVidia GPU on and off from userland, for bumblebee or KVM with IOMMU GPU passthrugh.
I'm not sure if there is an interface in Linux to call something in ACPI from userspace. Usually ACPI methods are called on standardized events from the kernel. So you might have to write a kernel driver to call your method (just noticed there exists `acpi_call` in the bumblebee project).
Writing a register isn't very straight forward (nothing seems to be in ACPI). Generally you have to define a `OperationRegion` that represents a part of memory or i/o space, and define a `Field` of registers over that. `southbridge/intel/bd82x6x/acpi/smbus.asl` might be a good example. The second `OperationRegion` there works on i/o ports, I guess you need something similar to change GPIO settings.
Hope that helps, Nico
[1] Advanced Configuration and Power Interface Specification Chapter 8 Processor Configuration and Control http://www.acpi.info/DOWNLOADS/ACPI_5_Errata%20A.pdf
[2] Intel® 64 and IA-32 Architectures Software Developer’s Manuals Vol.2
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32...
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Nico Huber