On 11/19/08, Peter Stuge peter@stuge.se wrote:
The page_size member is considered an eraseblock size by the code.
On Wed, Nov 19, 2008 at 8:36 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Yes. We should have one eraseblock_size member and one write_size member.
In the flashchips array, the value of page_size is page size if the chip has page-write as the only write command. At other times, it is just a parameter of the memory geometry - maybe erase block size, maybe not.
I have made some investigation to figure out the above result. I am attaching it below for convenience of further discussion.
Vendor Model Type Visibleness ----------------------------------------------------------------------- S P L F Wr Wp Px Ar Ap Po 1p Zp ?r ?p
S = SPI
P = Parallel (did not seperate parallel into sub-types when investigating those flash chips)
Px = Parallel, using JEDEC Single-Supply EEPROM like Command Set (command preceded by addresses and data containing alternated 1 and 0 bits, i.e., 55, 555, 5555, AA, AAA, 2AA, 2AAA, etc.)
Po = Parallel, without preceded cycles
L = LPC
F = FWH
N = There is no page concept or page is not visible to host.
Wr = Page read can start at any address within a page and will wrap back at page boundary in one page read instruction
Wp = Page program can start at any address within a page and will wrap back at page boundary in one page program instruction
Ar = Automatically page boundary alignment for page read
Ap = Automatically page boundary alignment for page program
1p = Every byte in a page has to be specified in one page program instruction
Zp = Page address is determined by the address of the last data to be programmed.
?r = Host should guarantee page address consistency when reading. How the flash chip behaves when inconsistency happens is unknown.
?p = Host should guarantee page address consistency when page programming. How the flash chip behaves when inconsistency happens is unknown.
Vendor Model Type Visibleness ----------------------------------------------------------------------- AMD Am29F002 - Px - - - - Am29F016D - Px - - - -
ATMEL AT25DF021 S - - - - Wp AT25F512B S - - - - Wp AT25FS010 S - - - - Wp AT26DF041 S - - - - Wp AT26F004 S - - - - - AT29C020 - - - - - 1p AT45CS1282 S - - - Wr Wp AT45DB011D S - - - Wr Wp AT49F002(N)(T) - P - - - -
AMIC A25L40P S - - - - Wp A29002(1) - P - - - - A29040B - P - - - - A49LF040A - - L - - -
EMST F49B002UA - P - - - -
EON EN29F002(N) - P - - - -
Fujitsu MBM29F004BC/TC - P - - - - MBM29F400BC/TC - P - - - -
Intel 82802AB/AC - - - F - -
Macronix MX25L512 S - - - - Wp MX25L1005 S - - - - Wp MX29F002(N)T/B - P - - - - MX29LV040C - P - - - -
Numonyx M25PE10/20 S - - - - Wp
PMC Pm25LV512A S - - - - Wp Pm25LV010A S - - - - Wp Pm25LV020 S - - - - Wp Pm25LV040 S - - - - Wp Pm25LV080B/016B S - - - - Wp Pm49FL002/004 - - L F - -
Sharp LHF00L04 - - - F ?r -
Spansion S25FL016A S - - - - ?p
SST SST25VF040B S - - - - - SST25VF080B S - - - - - SST25VF016B S - - - - - SST25VF032B S - - - - - SST28SF040A - - - - - - SST29EE010 - P - - - Zp SST29LE010 - P - - - Zp SST29VE010 - P - - - Zp SST29EE020A - P - - - Zp SST29LE020A - P - - - Zp SST29VE020A - P - - - Zp SST39SF010A - P - - - - SST39SF020A - P - - - - SST39SF040 - P - - - - SST39VF512 - P - - - - SST39VF010 - P - - - - SST39VF020 - P - - - - SST39VF040 - P - - - - SST49LF002A - P - F - - SST49LF003A - P - F - - SST49LF004A - P - F - - SST49LF008A - P - F - - SST49LF002B - P L F - - SST49LF003B - P L F - - SST49LF004B - P L F - - SST49LF004C - - - F - Ap SST49LF008C - - - F - Ap SST49LF016C - - - F - Ap SST49LF020A - P L - - - SST49LF040 - P L - - - SST49LF040B - P L - - - SST49LF080A - P L - - - SST49LF160C - - L - - Ap
ST M25P05-A S - - - - Wp M25P10-A S - - - - Wp M25P20 S - - - - Wp M25P40 S - - - - Wp M25P80 S - - - - Wp M25P16 S - - - - Wp M25P32 S - - - - Wp M25P64 S - - - - Wp M25P128 S - - - - Wp M29F002T/NT/B - Px - - - - M29F040B - Px - - - - M29F400BT - Px - - - - M29W010B - Px - - - - M29W040B - Px - - - - M50FLW040A/B - - L F Ar - M50FLW080A/B - - L F Ar - M50FW002 - Po - F - - M50FW040 - Po - F - - M50FW080 - Po - F - - M50LPW116 - Po L - - -
SyncMOS S29C31004T - Px - - - - S29C51001T - Px - - - - S29C51002T - Px - - - - S29C51004T - Px - - - -
Winbond W25x10 S - - - - Wp W25x20 S - - - - Wp W25x40 S - - - - Wp W25x80 S - - - - Wp W29C011A - Px - - - ?p W29C020C - Px - - - ?p W29C040 - Px - - - ?p W29EE011 - Px - - - ?p W39V040A - Px L - - - W39V040B - Px L - - - W39V040C - Px L - - - W39V040FA - Px - F - - W39V080A - Px L - - - W49F002U - Px - - - - W49V002A - Px L - - - W49V002FA - Px - F - - W39V080FA - Px - F - -
On 04.01.2009 10:20, FENG Yu Ning wrote:
On 11/19/08, Peter Stuge peter@stuge.se wrote:
The page_size member is considered an eraseblock size by the code.
On Wed, Nov 19, 2008 at 8:36 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Yes. We should have one eraseblock_size member and one write_size member.
In the flashchips array, the value of page_size is page size if the chip has page-write as the only write command. At other times, it is just a parameter of the memory geometry - maybe erase block size, maybe not.
I have made some investigation to figure out the above result. I am attaching it below for convenience of further discussion.
Vendor Model Type Visibleness
S P L F Wr Wp Px Ar Ap Po 1p Zp ?r ?pS = SPI
P = Parallel (did not seperate parallel into sub-types when investigating those flash chips)
L = LPC
F = FWH
Wr = Page read can start at any address within a page and will wrap back at page boundary in one page read instruction
Almost all SPI chips wrap at chip boundary for reads, not page boundary. Some LPF/FWH chips do the same.
Wp = Page program can start at any address within a page and will wrap back at page boundary in one page program instruction
Program wraparound (chip/page) not only depends on the chip, but also on the programming mode. Once we introduce drivers for external flashers, this becomes important.
We need multiple tuples of erase function <-> erase block size <-> access mode write function <-> write block size <-> access mode read function <-> read block size <-> access mode
For a chip supporting multiple erase functions, this means we need multiple erase function <-> erase block size pairs.
And each function also needs to be annotated with the access method (LPC/FWH/SPI/special AAI/...) so that flashrom can decide on whether a given flash function is usable with the available hardware. For example, an external flasher may be able to use AAI mode, whereas this is generally not possible (exceptions may apply) for in-circuit flashing (which is used by flashrom right now).
Regards, Carl-Daniel
-
Carl-Daniel Hailfinger -
FENG Yu Ning