SMI handler for fsp_broadwell_de

[Watzlavick, Robert L]

I want to experiment with an SMI handler on the Camelback Mountain CRB (Xeon D-1500) but it appears that the fsp_broadwell_de changes removed SMM support.  I'm browsing the coreboot-4.4 release.  Was there a reason it was removed?  It shows up in the soc/intel/Broadwell area so I suppose I could port over the original code.  I didn't see that the D_LCK bit was set anywhere so does that mean I can potentially let SeaBIOS install an SMI handler?  Or is it set in the FSP?  I also noticed the mainline has some new code under coreboot/src/soc/intel/sch but I'm not sure which processors that is for.

Thanks,
-Bob

[Yang, York]

Fsp_broadwell_de do not implement the SMI support, but you may refer to soc/Broadwell as both are Intel architecture chipset.  The SMI support can be done purely in coreboot, but need to touch FSP.

/ YoRK

From: coreboot [mailto:[e-mail]] On Behalf Of Watzlavick, Robert L
Sent: Thursday, September 22, 2016 4:28 PM
To: [e-mail]
Subject: [coreboot] SMI handler for fsp_broadwell_de

I want to experiment with an SMI handler on the Camelback Mountain CRB (Xeon D-1500) but it appears that the fsp_broadwell_de changes removed SMM support.  I'm browsing the coreboot-4.4 release.  Was there a reason it was removed?  It shows up in the soc/intel/Broadwell area so I suppose I could port over the original code.  I didn't see that the D_LCK bit was set anywhere so does that mean I can potentially let SeaBIOS install an SMI handler?  Or is it set in the FSP?  I also noticed the mainline has some new code under coreboot/src/soc/intel/sch but I'm not sure which processors that is for.

Thanks,
-Bob

[Zoran Stojsavljevic]

> I didn’t see that the D_LCK bit was set anywhere so does that mean I can

potentially let SeaBIOS install an SMI handler?

Isn't it that D_LCK belongs to the following PCIe root hub configuration
space register: 0:0.0 0x9c (32bit)? Where the following is the lowest byte
structure:
bit 7 -> Reserved
bit 6 -> D_OPEN
bit 5 -> D_CLS
bit 4 -> D_LCK
bit 3 -> Enable
[bits (0..2) are reserved (0s)]

When I do the following on my HSW i5-4300: setpci -s 0:0.0 0x9c.l =>
0xFFFFFFFF ???

Any explanation? York?

Thank you,
Zoran

On Fri, Sep 23, 2016 at 1:27 AM, Watzlavick, Robert L <
[e-mail]> wrote:
> I want to experiment with an SMI handler on the Camelback Mountain CRB
> (Xeon D-1500) but it appears that the fsp_broadwell_de changes removed SMM
> support.  I’m browsing the coreboot-4.4 release.  Was there a reason it was
> removed?  It shows up in the soc/intel/Broadwell area so I suppose I could
> port over the original code.  I didn’t see that the D_LCK bit was set
> anywhere so does that mean I can potentially let SeaBIOS install an SMI
> handler?  Or is it set in the FSP?  I also noticed the mainline has some
> new code under coreboot/src/soc/intel/sch but I’m not sure which processors
> that is for.
>
> Thanks,
>
> -Bob