It is awhile... Opportunity just did struck (suddenly/plotzlich), so I am
While lurking around in Coreboot, trying to solve some "Mystery of digital
Orga.ni.sms", I ran into very interesting file:
Coreboot tree I am using: [zoran@localhost coreboot-09.06.2016]$ git
Maybe, it is worth looking into it. You tell us?
On Tue, May 3, 2016 at 10:28 AM, Alexander Böcken <
again, thanks for your clues to this problem. I don't think post code 0x52
is about memory configuration. The post code appears when I call
TempRamInit which is supposed to enable Cache-as-RAM. Real memory is
initialized at a later call to FspMemoryInit. coreboot supplies the
location of the microcode and a cachable region to TempRamInit.
Additionally, there are some settings that can be applied to the FSP image
with Intel's Binary Configuration Tool. I don't know if these are used
during TempRamInit, but I'll try and fiddle around with them.
I agree, it would be helpful to have a list of post codes that can be
output by FSP. Otherwise it's all speculation as what is wrong.