[LinuxBIOS] Posted memory write enable...incorrect? - coreboot

20 May 2005


      Hi,
In looking over the Intel 82801ER (ICH-5) southbridge code, I noticed
some statements that modify LPC PCI config register 0x46 to enable PCI
posted memory writes (src/southbridge/intel/i82801er/i82801er_lpc.c):
static void lpc_init(struct device *dev)
    {
        ...
/* posted memory write enable */
       byte = pci_read_config8(dev, 0x46);
       pci_write_config8(dev, 0x46, byte | (1<<0));
...
    }
The ICH-5 datasheet does not mention such a configuration register.
Neither do the datasheets for the ICH-4 (82801DBM) or the AMD 8111,
which have similar code.
Is it possible that these were inherited (incorrectly) from code for the
AMD 766 southbridge? That *does* support this functionality.
Steve Magnani
Digital Design Corporation
www.digidescorp.com