[PATCH] (resend) fix the flashrom problem on m57sli boards with SPI flash

[Florentin Demetrescu]

This patch fixes the decoding of the IO address range 0x0800->0x085f into the
LPC device of the MCP55 southbridge, enabling flashrom access to the SPI
interface of the IT8716 SIO chip.

Signed-off-by: Florentin Demetrescu

Patch file attached.

Thanks,
  Florentin

[Peter Stuge]

On Thu, Jan 17, 2008 at 01:40:07PM +0100, Florentin Demetrescu wrote:
> /* FIXME : really dirty! It seems that the IO addr range for the SPI IF.
> HAS to be set into the 0xb0 or 0xb4 reg which conflicts strongly with
> mcp55_lpc_enable_childrens_resources() */
> pci_write_config32(dev, conf->spi_sio_pcireg, conf->spi_sio_iorange);

Can you expand on this comment? What would be the clean way and what
is the conflict in the mcp55 code?

//Peter

[Florentin Demetrescu]

Quoting Peter Stuge :
> On Thu, Jan 17, 2008 at 01:40:07PM +0100, Florentin Demetrescu wrote:
> > /* FIXME : really dirty! It seems that the IO addr range for the SPI IF.
> > HAS to be set into the 0xb0 or 0xb4 reg which conflicts strongly with
> > mcp55_lpc_enable_childrens_resources() */
> > pci_write_config32(dev, conf->spi_sio_pcireg, conf->spi_sio_iorange);
>
> Can you expand on this comment? What would be the clean way and what
> is the conflict in the mcp55 code?

yes.

In the procedure "mcp55_lpc_enable_childrens_resources()" at line 335 in
mcp55_lpc.c one founds this loop :

for(i=0;i<var_num;i++) {
    	pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
    }

Given that "var_num" can be btw 0 and 3, when i=2 one gets 0xa8 + i*4 = 0xb0,
so this procedure thrashes the value set by the patched procedure "lpc_init()"
(when conf->spi_sio_pcireg=0xb0)

The clean way to fix this? Unfortunately I see no one, unless we have access to
some NDAed documentation, as I have no idea why the 0x0800->0x085f IO range must
be set into the 0xb0 or 0xb4 pci registers.. Maybe Yinghai could give some
advice..

And a last remark : in some previous posts concerning this topic, people speak
about gpio configuration.. IMHO, this isn't related in any way with the gpio
configuration issue (nor in SB, not even in SIO), but only to the IO address
decoding (and "routing") inside the southbridge.

Regards,
  Florentin

[PATCH] (resend) fix the flashrom problem on m57sli boards with SPI flash

[Carl-Daniel Hailfinger]

On 17.01.2008 15:33, Florentin Demetrescu wrote:
> Quoting Peter Stuge :
> > On Thu, Jan 17, 2008 at 01:40:07PM +0100, Florentin Demetrescu wrote:
> > > /* FIXME : really dirty! It seems that the IO addr range for the SPI IF.
> > > HAS to be set into the 0xb0 or 0xb4 reg which conflicts strongly with
> > > mcp55_lpc_enable_childrens_resources() */
> > > pci_write_config32(dev, conf->spi_sio_pcireg, conf->spi_sio_iorange);
> >
> > Can you expand on this comment? What would be the clean way and what
> > is the conflict in the mcp55 code?
>
> yes.
>
> In the procedure "mcp55_lpc_enable_childrens_resources()" at line 335 in
> mcp55_lpc.c one founds this loop :
>
> for(i=0;i<var_num;i++) {
>    	pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
>    }
>
> Given that "var_num" can be btw 0 and 3, when i=2 one gets 0xa8 + i*4 = 0xb0,
> so this procedure thrashes the value set by the patched procedure "lpc_init()"
> (when conf->spi_sio_pcireg=0xb0)
>
> The clean way to fix this? Unfortunately I see no one, unless we have access to
> some NDAed documentation, as I have no idea why the 0x0800->0x085f IO range must
> be set into the 0xb0 or 0xb4 pci registers.. Maybe Yinghai could give some
> advice..

If 0x0800 appears as a child IO resource, everything should work just
fine. Can you try that?
> And a last remark : in some previous posts concerning this topic, people speak
> about gpio configuration.. IMHO, this isn't related in any way with the gpio
> configuration issue (nor in SB, not even in SIO), but only to the IO address
> decoding (and "routing") inside the southbridge.

Yes.

Regards,
Carl-Daniel