Hello, Was anyone aware we are doing the do_ram_command() wrong on the i8xx nothbridges? We are sending the ram commands to all memory and doing our dummy reads at the end. I just found an Intel doc that says we are supposed to do all the ram commands to each row of memory.
Quoting from doc:
1. Steps for JEDEC initilization for SDRAM devices during boot up: a. NOP command b. Pre-charge all banks (at least 200 us after NOP) c. 8 CBR refreshes (Auto Refresh) d. MRS command e. Set GMCH-M Mode Select bits back to NORMAL operation mode f. Perform a dummy memory read cycle 2. Repeat this sequence for all memory rows for all SO-DIMMs 3. Test all memory rows after JEDEC initialization sequence is done on all memory rows
I will work on a patch for the i830, we should probibly fix this on the other Intle northbridges.
On 02.06.2009 17:13 Uhr, Joseph Smith wrote:
Hello, Was anyone aware we are doing the do_ram_command() wrong on the i8xx nothbridges? We are sending the ram commands to all memory and doing our dummy reads at the end. I just found an Intel doc that says we are supposed to do all the ram commands to each row of memory.
...
I will work on a patch for the i830, we should probibly fix this on the other Intle northbridges.
Check the i945 code for an example on how to do it... older chipsets might/might not be different...
On Tue, 02 Jun 2009 18:00:53 +0200, Stefan Reinauer stepan@coresystems.de wrote:
On 02.06.2009 17:13 Uhr, Joseph Smith wrote:
Hello, Was anyone aware we are doing the do_ram_command() wrong on the i8xx nothbridges? We are sending the ram commands to all memory and doing our dummy reads
at
the end. I just found an Intel doc that says we are supposed to do all the ram commands to each row of memory.
...
I will work on a patch for the i830, we should probibly fix this on the other Intle northbridges.
Check the i945 code for an example on how to do it... older chipsets might/might not be different...
Would it be different for SDRAM vs DDR ?
On Tue, 02 Jun 2009 18:00:53 +0200, Stefan Reinauer stepan@coresystems.de wrote:
On 02.06.2009 17:13 Uhr, Joseph Smith wrote:
Hello, Was anyone aware we are doing the do_ram_command() wrong on the i8xx nothbridges? We are sending the ram commands to all memory and doing our dummy reads
at
the end. I just found an Intel doc that says we are supposed to do all the ram commands to each row of memory.
...
I will work on a patch for the i830, we should probibly fix this on the other Intle northbridges.
Check the i945 code for an example on how to do it... older chipsets might/might not be different...
Would it be different for SDRAM vs DDR ?
You need a couple more steps (different MRS commands etc) for DDR, but the loop itself is basically the same.
On Tue, 02 Jun 2009 18:11:42 +0200, Stefan Reinauer stepan@coresystems.de wrote:
On Tue, 02 Jun 2009 18:00:53 +0200, Stefan Reinauer
wrote:
On 02.06.2009 17:13 Uhr, Joseph Smith wrote:
Hello, Was anyone aware we are doing the do_ram_command() wrong on the i8xx nothbridges? We are sending the ram commands to all memory and doing our dummy
reads
at
the end. I just found an Intel doc that says we are supposed to do all the ram commands to each row of memory.
...
I will work on a patch for the i830, we should probibly fix this on
the
other Intle northbridges.
Check the i945 code for an example on how to do it... older chipsets might/might not be different...
Would it be different for SDRAM vs DDR ?
You need a couple more steps (different MRS commands etc) for DDR, but the loop itself is basically the same.
Ok, I hope you don't mind but I have a few questions about how the i945 sdram_jedec_enable() does it?
Just to clarify, jedec seems to call it "banks" and Intel calls it "rows" correct?
I don't really understand how you are calculating the bank address (BA or bankaddr) which determines the row of memory to initialize, can you logically explain it or do you have a good source you can point me too?
According to your for loop, it looks like you are running the set of initialize commands 8 times? If the i945 has a max of 2 memory sockets which means max of 4 rows, shouldn't this only run 4 times?
Also it doesn't look like there is a control structure in place to skip the rows where no memory is found? Is that correct?
Sorry if these questions are silly, I am just trying to understand it.
On Tue, 02 Jun 2009 11:13:30 -0400, Joseph Smith joe@settoplinux.org wrote:
Hello, Was anyone aware we are doing the do_ram_command() wrong on the i8xx nothbridges? We are sending the ram commands to all memory and doing our dummy reads
at
the end. I just found an Intel doc that says we are supposed to do all the ram commands to each row of memory.
Quoting from doc:
- Steps for JEDEC initilization for SDRAM devices during boot up:
a. NOP command b. Pre-charge all banks (at least 200 us after NOP) c. 8 CBR refreshes (Auto Refresh) d. MRS command e. Set GMCH-M Mode Select bits back to NORMAL operation mode f. Perform a dummy memory read cycle 2. Repeat this sequence for all memory rows for all SO-DIMMs 3. Test all memory rows after JEDEC initialization sequence is done on
all
memory rows
I will work on a patch for the i830, we should probibly fix this on the other Intle northbridges.
Good news :-) I have the above method working on the i830. I just want to do a little more testing before I submit a patch.
-
Joseph Smith -
Stefan Reinauer