Author: rminnich Date: 2008-10-05 06:56:29 +0200 (Sun, 05 Oct 2008) New Revision: 889
Modified: coreboot-v3/superio/fintek/f71805f/superio.c coreboot-v3/superio/ite/it8712f/superio.c coreboot-v3/superio/ite/it8716f/superio.c coreboot-v3/superio/winbond/w83627hf/superio.c Log: Minor typos that need to be fixed. The oddest thing is that an earlier version, with these typos, compiled.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/superio/fintek/f71805f/superio.c =================================================================== --- coreboot-v3/superio/fintek/f71805f/superio.c 2008-10-05 04:46:32 UTC (rev 888) +++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-10-05 04:56:29 UTC (rev 889) @@ -95,6 +95,8 @@ } }
+static void phase2_setup_scan_bus(struct device *dev); + struct device_operations f71805f_ops = { .phase2_setup_scan_bus = phase2_setup_scan_bus, .phase4_read_resources = pnp_read_resources, @@ -105,8 +107,8 @@ };
static struct pnp_info pnp_dev_info[] = { - { &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &f71805f_ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &f71805f_ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, /* TODO: Everything else */ };
Modified: coreboot-v3/superio/ite/it8712f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8712f/superio.c 2008-10-05 04:46:32 UTC (rev 888) +++ coreboot-v3/superio/ite/it8712f/superio.c 2008-10-05 04:56:29 UTC (rev 889) @@ -114,7 +114,7 @@ pnp_set_enable(dev, dev->enabled); pnp_exit_ext_func_mode(dev); } - +static void it8712f_setup_scan_bus(struct device *dev); struct device_operations it8712f_ops = { .phase2_setup_scan_bus = it8712f_setup_scan_bus, .phase4_read_resources = pnp_read_resources, @@ -126,13 +126,13 @@
/* TODO: FDC, MIDI, GAME, IR. */ static struct pnp_info pnp_dev_info[] = { - {&ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0}, }, - {&ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x7f8, 0}, }, - {&ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},}, - {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4}, }, - {&ops, IT8712F_KBCM, PNP_IRQ0, }, - {&ops, IT8712F_GPIO, }, + {&it8712f_ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0}, }, + {&it8712f_ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x7f8, 0}, }, + {&it8712f_ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&it8712f_ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},}, + {&it8712f_ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4}, }, + {&it8712f_ops, IT8712F_KBCM, PNP_IRQ0, }, + {&it8712f_ops, IT8712F_GPIO, }, };
static void it8712f_setup_scan_bus(struct device *dev)
Modified: coreboot-v3/superio/ite/it8716f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8716f/superio.c 2008-10-05 04:46:32 UTC (rev 888) +++ coreboot-v3/superio/ite/it8716f/superio.c 2008-10-05 04:56:29 UTC (rev 889) @@ -143,6 +143,7 @@ } }
+static void it8716f_setup_scan_bus(struct device *dev); struct device_operations it8716f_ops = { .phase2_setup_scan_bus = it8716f_setup_scan_bus, .phase4_read_resources = pnp_read_resources, @@ -153,19 +154,19 @@ };
static struct pnp_info pnp_dev_info[] = { - {&ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, + {&it8716f_ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&it8716f_ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&it8716f_ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},}, - {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, + {&it8716f_ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, {0x7ff, 0x4},}, - {&ops, IT8716F_KBCM, PNP_IRQ0,}, - {&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},}, - {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, - {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, - {&ops, IT8716F_IR,}, + {&it8716f_ops, IT8716F_KBCM, PNP_IRQ0,}, + {&it8716f_ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, + {&it8716f_ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, + {&it8716f_ops, IT8716F_IR,}, };
static void it8716f_setup_scan_bus(struct device *dev)
Modified: coreboot-v3/superio/winbond/w83627hf/superio.c =================================================================== --- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-05 04:46:32 UTC (rev 888) +++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-05 04:56:29 UTC (rev 889) @@ -189,7 +189,7 @@ pnp_exit_ext_func_mode(dev); } } - +static void phase2_setup_scan_bus(struct device *dev); struct device_operations w83627hf_ops = { .phase2_setup_scan_bus = phase2_setup_scan_bus, .phase4_read_resources = pnp_read_resources, @@ -200,18 +200,18 @@ };
static struct pnp_info pnp_dev_info[] = { - { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, // No 4 { 0,}, - { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, - { &ops, W83627HF_GPIO2, }, - { &ops, W83627HF_GPIO3, }, - { &ops, W83627HF_ACPI, }, - { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, + { &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &w83627hf_ops, W83627HF_GPIO2, }, + { &w83627hf_ops, W83627HF_GPIO3, }, + { &w83627hf_ops, W83627HF_ACPI, }, + { &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, };
-
svn＠coreboot.org