r808 - in coreboot-v3: . device include/device mainboard/amd mainboard/amd/serengeti northbridge/amd/k8 southbridge/amd/amd8111
Author: rminnich Date: 2008-08-24 04:59:05 +0200 (Sun, 24 Aug 2008) New Revision: 808
Modified: coreboot-v3/Kconfig coreboot-v3/device/hypertransport.c coreboot-v3/include/device/hypertransport.h coreboot-v3/mainboard/amd/Kconfig coreboot-v3/mainboard/amd/serengeti/dts coreboot-v3/northbridge/amd/k8/Makefile coreboot-v3/northbridge/amd/k8/domain.c coreboot-v3/northbridge/amd/k8/pci.c coreboot-v3/southbridge/amd/amd8111/Makefile coreboot-v3/southbridge/amd/amd8111/ac97.c coreboot-v3/southbridge/amd/amd8111/acpi.c coreboot-v3/southbridge/amd/amd8111/amd8111.c coreboot-v3/southbridge/amd/amd8111/ide.c coreboot-v3/southbridge/amd/amd8111/lpc.c coreboot-v3/southbridge/amd/amd8111/nic.c coreboot-v3/southbridge/amd/amd8111/nic.dts coreboot-v3/southbridge/amd/amd8111/smbus.c coreboot-v3/southbridge/amd/amd8111/usb.c coreboot-v3/southbridge/amd/amd8111/usb2.c Log: This now compiles (with many warnings but ...) and tries to build a rom image, and fails: LAR build/coreboot.rom Bootblock coreboot.bootblock does not appear to be a bootblock. Error adding the bootblock to the LAR. make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 1
Next step is to get rid of all warnings that are not #warning.
Then it is on to simnow.
Anyone who wants to work on the warnings is most welcome to.
DBE62 still builds with no problems.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/Kconfig 2008-08-24 02:59:05 UTC (rev 808) @@ -84,6 +84,8 @@ boolean config SOUTHBRIDGE_NVIDIA_MCP55 boolean +config SOUTHBRIDGE_AMD_AMD8111 + boolean
# Super I/Os: config SUPERIO_WINBOND_W83627HF
Modified: coreboot-v3/device/hypertransport.c =================================================================== --- coreboot-v3/device/hypertransport.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/device/hypertransport.c 2008-08-24 02:59:05 UTC (rev 808) @@ -23,22 +23,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <bitops.h> #include <console.h> -#include <device/device.h> -#include <device/path.h> +#include <lib.h> +#include <string.h> +#include <mtrr.h> +#include <macros.h> +#include <spd.h> +#include <cpu.h> +#include <msr.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> #include <device/pci.h> -#include <device/pci_ids.h> +#include <device/hypertransport_def.h> #include <device/hypertransport.h> -#include <part/hard_reset.h> -#include <part/fallback_boot.h> +#include <mc146818rtc.h> +#include <lib.h> +#include <lapic.h> +#include <mainboard.h>
#define OPT_HT_LINK 0
-#if OPT_HT_LINK == 1 -#include <cpu/amd/model_fxx_rev.h> -#endif - static struct device *ht_scan_get_devs(struct device **old_devices) { struct device *first, *last; @@ -322,7 +326,7 @@ } while ((ctrl & (1 << 5)) == 0);
/* Actually, only for one HT device HT chain, and unitid is 0. */ -#if HT_CHAIN_UNITID_BASE == 0 +#if CONFIG_HT_CHAIN_UNITID_BASE == 0 if (offset_unitid) { return; } @@ -332,8 +336,8 @@ if ((!offset_unitid) || (offset_unitid && - (!((HT_CHAIN_END_UNITID_BASE == 0) - && (HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE))))) { + (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) + && (CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE))))) { struct device dummy; u32 id; dummy.bus = bus; @@ -361,8 +365,9 @@ (id == 0x0000ffff) || (id == 0xffff0000)) { continue; } - dummy.vendor = id & 0xffff; - dummy.device = (id >> 16) & 0xffff; + dummy.id.type = DEVICE_ID_PCI; + dummy.id.pci.vendor = id & 0xffff; + dummy.id.pci.device = (id >> 16) & 0xffff; dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE); pos = ht_lookup_slave_capability(&dummy); if (!pos) { @@ -374,7 +379,7 @@ flags &= ~0x1f; pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags); printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", - dev_path(&dummy), dummy.vendor, dummy.device); + dev_path(&dummy), dummy.id.pci.vendor, dummy.id.pci.device); } }
@@ -384,20 +389,20 @@ unsigned int *ht_unitid_base, unsigned int offset_unitid) { - /* Even HT_CHAIN_UNITID_BASE == 0, we still can go through this + /* Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this * function, because of end_of_chain check, also we need it to * optimize link. */ unsigned int next_unitid, last_unitid; struct device *old_devices, *dev, *func; - unsigned int min_unitid = (offset_unitid) ? HT_CHAIN_UNITID_BASE : 1; + unsigned int min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1; struct ht_link prev; struct device *last_func = 0; int ht_dev_num = 0;
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE /* Let's record the device of last HT device, so we can set the - * unitid to HT_CHAIN_END_UNITID_BASE. + * unitid to CONFIG_HT_CHAIN_END_UNITID_BASE. */ unsigned int real_last_unitid; u8 real_last_pos; @@ -509,7 +514,7 @@ /* Update the unitid of the next device. */ ht_unitid_base[ht_dev_num] = next_unitid; ht_dev_num++; -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE if (offset_unitid) { real_last_unitid = next_unitid; real_last_pos = pos; @@ -523,7 +528,7 @@
printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", dev_path(dev), - dev->vendor, dev->device, + dev->id.pci.vendor, dev->id.pci.device, (dev->enabled ? "enabled" : "disabled"), next_unitid);
@@ -538,7 +543,7 @@ } #endif
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE if (offset_unitid && (ht_dev_num > 0)) { u16 flags; int i; @@ -546,19 +551,19 @@ flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
for (func = real_last_dev; func; func = func->sibling) { func->path.pci.devfn -= ((real_last_unitid - - HT_CHAIN_END_UNITID_BASE) << 3); + CONFIG_HT_CHAIN_END_UNITID_BASE) << 3); last_func = func; }
/* Update last one. */ - ht_unitid_base[ht_dev_num - 1] = HT_CHAIN_END_UNITID_BASE; + ht_unitid_base[ht_dev_num - 1] = CONFIG_HT_CHAIN_END_UNITID_BASE;
next_unitid = real_last_unitid; } @@ -629,12 +634,11 @@ };
const struct device_operations default_ht_ops_bus = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = ht_scan_bridge, - .enable = 0, + .phase3_scan = ht_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = 0, .reset_bus = pci_bus_reset, .ops_pci = &ht_bus_ops_pci, };
Modified: coreboot-v3/include/device/hypertransport.h =================================================================== --- coreboot-v3/include/device/hypertransport.h 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/include/device/hypertransport.h 2008-08-24 02:59:05 UTC (rev 808) @@ -24,7 +24,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); unsigned int ht_scan_bridge(struct device *dev, unsigned int max); -extern struct device_operations default_ht_ops_bus; +extern const struct device_operations default_ht_ops_bus;
#define HT_IO_HOST_ALIGN 4096 #define HT_MEM_HOST_ALIGN (1024*1024)
Modified: coreboot-v3/mainboard/amd/Kconfig =================================================================== --- coreboot-v3/mainboard/amd/Kconfig 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/mainboard/amd/Kconfig 2008-08-24 02:59:05 UTC (rev 808) @@ -52,6 +52,7 @@ select OPTION_TABLE select CPU_AMD_K8 select NORTHBRIDGE_AMD_K8 + select SOUTHBRIDGE_AMD_AMD8111 select IOAPIC help AMD Serengeti
Modified: coreboot-v3/mainboard/amd/serengeti/dts =================================================================== --- coreboot-v3/mainboard/amd/serengeti/dts 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/mainboard/amd/serengeti/dts 2008-08-24 02:59:05 UTC (rev 808) @@ -17,25 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*00:00.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a1) -00:01.0 ISA bridge: nVidia Corporation MCP55 LPC Bridge (rev a2) -00:01.1 SMBus: nVidia Corporation MCP55 SMBus (rev a2) -00:02.0 USB Controller: nVidia Corporation MCP55 USB Controller (rev a1) -00:02.1 USB Controller: nVidia Corporation MCP55 USB Controller (rev a2) -00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) -00:05.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) -00:05.1 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) -00:06.0 PCI bridge: nVidia Corporation MCP55 PCI bridge (rev a2) -00:06.1 Audio device: nVidia Corporation MCP55 High Definition Audio (rev a2) -00:08.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a2) -00:0f.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) -00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration -00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map -00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller -00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control -01:0a.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) -02:00.0 VGA compatible controller: nVidia Corporation G72 [GeForce 7300 LE] (rev a1) -*/
/{ mainboard_vendor = "AMD"; @@ -46,11 +27,18 @@ domain@0 { pci@1,0{ }; + /* guesses; we need a real lspci */ pci@18,0 { /config/("northbridge/amd/k8/pci"); pci@0,0 { /config/("southbridge/amd/amd8111/amd8111.dts"); }; + pci@4,0 { + /config/("southbridge/amd/amd8111/ide.dts"); + }; + pci@5,0 { + /config/("southbridge/amd/amd8111/nic.dts"); + }; }; }; };
Modified: coreboot-v3/northbridge/amd/k8/Makefile =================================================================== --- coreboot-v3/northbridge/amd/k8/Makefile 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/northbridge/amd/k8/Makefile 2008-08-24 02:59:05 UTC (rev 808) @@ -26,6 +26,7 @@ $(src)/northbridge/amd/k8/common.c \ $(src)/northbridge/amd/k8/cpu.c \ $(src)/northbridge/amd/k8/domain.c \ - $(src)/northbridge/amd/k8/pci.c + $(src)/northbridge/amd/k8/pci.c \ + $(src)/device/hypertransport.c
endif
Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-08-24 02:59:05 UTC (rev 808) @@ -360,7 +360,7 @@ k8_ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; } - assign_resources(&dev->link[0]); + phase4_assign_resources(&dev->link[0]); }
static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max)
Modified: coreboot-v3/northbridge/amd/k8/pci.c =================================================================== --- coreboot-v3/northbridge/amd/k8/pci.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/northbridge/amd/k8/pci.c 2008-08-24 02:59:05 UTC (rev 808) @@ -546,7 +546,7 @@ struct bus *bus; bus = &dev->link[link]; if (bus->children) { - assign_resources(bus); + phase4_assign_resources(bus); } } }
Modified: coreboot-v3/southbridge/amd/amd8111/Makefile =================================================================== --- coreboot-v3/southbridge/amd/amd8111/Makefile 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/Makefile 2008-08-24 02:59:05 UTC (rev 808) @@ -34,7 +34,7 @@ $(src)/southbridge/amd/amd8111/usb.c \ $(src)/southbridge/amd/amd8111/usb2.c -STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/amd8111/stage1.c +STAGE0_CHIPSET_SRC +=
endif
Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-08-24 02:59:05 UTC (rev 808) @@ -17,11 +17,15 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <device/device.h> +#include <types.h> +#include <lib.h> +#include <console.h> #include <device/pci.h> +#include <msr.h> +#include <legacy.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> +#include <statictree.h> +#include <config.h> #include "amd8111.h"
static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-08-24 02:59:05 UTC (rev 808) @@ -17,7 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <console.h> #include <device/device.h> #include <types.h> #include <lib.h> @@ -27,7 +27,10 @@ #include <legacy.h> #include <device/pci_ids.h> #include <statictree.h> -#include <config.h>#include "amd8111.h" +#include <config.h> +#include <device/smbus.h> +#include <mc146818rtc.h> +#include "amd8111.h" #include "amd8111_smbus.h"
#define PREVIOUS_POWER_STATE 0x43 @@ -43,6 +46,7 @@
static int lsmbus_recv_byte(struct device * dev) { + int do_smbus_recv_byte(u16 smbus_io_base, u16 device); unsigned device; struct resource *res;
@@ -54,6 +58,7 @@
static int lsmbus_send_byte(struct device * dev, u8 val) { + int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val); unsigned device; struct resource *res;
@@ -66,6 +71,7 @@
static int lsmbus_read_byte(struct device * dev, u8 address) { + int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address); unsigned device; struct resource *res;
@@ -77,6 +83,7 @@
static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { + int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val); unsigned device; struct resource *res;
@@ -140,7 +147,7 @@ byte |= 0x40; } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
/* switch serial irq logic from quiet mode to continuous * mode for Winbond W83627HF Rev. 17 @@ -218,11 +225,7 @@ .set_subsystem = lpci_set_subsystem, };
-static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -struct device_operations ac97audio = { +struct device_operations acpi = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_ACPI}}},
Modified: coreboot-v3/southbridge/amd/amd8111/amd8111.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-08-24 02:59:05 UTC (rev 808) @@ -41,27 +41,27 @@
/* See if we are behind the amd8111 pci bridge */ bus_dev = dev->bus->dev; - if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && - (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) + if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_AMD) && + (bus_dev->id.pci.device == PCI_DEVICE_ID_AMD_8111_PCI)) { unsigned devfn; devfn = bus_dev->path.pci.devfn + (1 << 3); lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn); - index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8; - if (dev->path.u.pci.devfn == 2) { /* EHCI */ + index = ((dev->path.pci.devfn & ~7) >> 3) + 8; + if (dev->path.pci.devfn == 2) { /* EHCI */ index = 16; } } else { unsigned devfn; - devfn = (dev->path.u.pci.devfn) & ~7; + devfn = (dev->path.pci.devfn) & ~7; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); - index = dev->path.u.pci.devfn & 7; + index = dev->path.pci.devfn & 7; } if ((!lpc_dev) || (index >= 17)) { return; } - if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) || - (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) + if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_AMD) || + (lpc_dev->id.pci.device != PCI_DEVICE_ID_AMD_8111_ISA)) { u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
Modified: coreboot-v3/southbridge/amd/amd8111/ide.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ide.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-08-24 02:59:05 UTC (rev 808) @@ -26,7 +26,7 @@ #include <device/pci_ids.h> #include <statictree.h> #include <config.h> -#nclude "amd8111.h" +#include "amd8111.h"
static void ide_init(struct device *dev) { @@ -34,7 +34,7 @@ /* Enable ide devices so the linux ide driver will work */ u16 word; u8 byte; - conf = dev->chip_info; + conf = dev->device_configuration;
word = pci_read_config16(dev, 0x40); /* Ensure prefetch is disabled */ @@ -72,7 +72,7 @@ .set_subsystem = lpci_set_subsystem, };
-struct device_operations mcp55_ide = { +struct device_operations amd8111_ide = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_IDE}}},
Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-24 02:59:05 UTC (rev 808) @@ -27,6 +27,8 @@ #include <device/pci_ids.h> #include <statictree.h> #include <config.h> +#include <lapic.h> +#include <mc146818rtc.h> #include "amd8111.h"
#define NMI_OFF 0 @@ -103,7 +105,7 @@ l[4] = a->value_high; value_high = l[4]; if ((i==0) && (value_low == 0xffffffff)) { - printk_warning("IO APIC not responding.\n"); + printk(BIOS_WARNING, "IO APIC not responding.\n"); return; } printk(BIOS_SPEW, "for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
Modified: coreboot-v3/southbridge/amd/amd8111/nic.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/nic.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/nic.c 2008-08-24 02:59:05 UTC (rev 808) @@ -71,6 +71,7 @@
/* Hard Reset PHY */ printk(BIOS_DEBUG, "Reseting PHY... "); +/* if (conf->phy_lowreset) { writel(VAL0 | PHY_RST_POL | RESET_PHY , (void *)(mmio + CMD3)); } else { @@ -78,6 +79,7 @@ } mdelay(15); writel(RESET_PHY, (void *)(mmio + CMD3)); +*/ printk(BIOS_DEBUG, "Done\n"); }
Modified: coreboot-v3/southbridge/amd/amd8111/nic.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/nic.dts 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/nic.dts 2008-08-24 02:59:05 UTC (rev 808) @@ -20,4 +20,5 @@
{ device_operations = "amd8111_nic"; + phy_lowreset = "0"; };
Modified: coreboot-v3/southbridge/amd/amd8111/smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-08-24 02:59:05 UTC (rev 808) @@ -26,13 +26,12 @@ #include <device/pci_ids.h> #include <statictree.h> #include <config.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus.h> -#include <arch/io.h> +#include <io.h> #include "amd8111.h"
static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) @@ -59,6 +58,6 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, - .ops_pci = &lops_pci + .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, };
Modified: coreboot-v3/southbridge/amd/amd8111/usb.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-08-24 02:59:05 UTC (rev 808) @@ -26,13 +26,11 @@ #include <device/pci_ids.h> #include <statictree.h> #include <config.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus.h> -#include <arch/io.h> +#include <io.h> #include "amd8111.h"
Modified: coreboot-v3/southbridge/amd/amd8111/usb2.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-08-23 16:51:00 UTC (rev 807) +++ coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-08-24 02:59:05 UTC (rev 808) @@ -27,13 +27,12 @@ #include <device/pci_ids.h> #include <statictree.h> #include <config.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus.h> -#include <arch/io.h> +#include <io.h> #include "amd8111.h"
static void amd8111_usb2_enable(struct device *dev)
-
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