Note: for install this patch, you must download the last coreboot SVN, and install first the patch posted by Corey Osgood, that includes CN700/C7 and jetway mainboard. The filo patch is for correct a problem with FILO when tries to find the IDE disk, if more that one IDE interface is on, and no all IDE's are in native Mode. The count of compatibility interfaces are wrong, and not finds the interface that is marked as a IDE 0x0101 or SATA 0x0180 and not all are native, the search of the io base and control, are wrong. If this is not correct sorry :))) If in VT8237R have SATA as an 0101 and the IDE too 0101 class, with this patch, works, because counts corectly the unique non native interface IDE, as the first. NOTE1: in the epia-cn/Config.lb the IDE and SATA are enabled. NOTE2: in epia-cn/auto.c the values of PCI_DEV(0,0x11,0) 0x50 and 0x51 are different, for have IDE and SATA enableds at function enable_mainboard_devices NOTE3: Here is a file base.c that haves a udelay with use of rtdsc NOTE4: another function via_cn_fixup, fixes the use of PCI devices access to the memory. Must be improved, and not use a fixed value. NOTE5: have a change in cn700/raminit.c for configure in CN the memory. NOTE6: vt8237r configures the SATA device as an IDE class 0x0101 must be 0x0180????? Urbez Santana.
On Feb 6, 2008 7:03 PM, Urbez Santana Roma <urbez@linuxupc.upc.edu> wrote:
Note: for install this patch, you must download the last coreboot SVN, and install first the patch posted by Corey Osgood, that includes CN700/C7 and jetway mainboard.
The filo patch is for correct a problem with FILO when tries to find the IDE disk, if more that one IDE interface is on, and no all IDE's are in native Mode. The count of compatibility interfaces are wrong, and not finds the interface that is marked as a IDE 0x0101 or SATA 0x0180 and not all are native, the search of the io base and control, are wrong.
If this is not correct sorry :)))
If in VT8237R have SATA as an 0101 and the IDE too 0101 class, with this patch, works, because counts corectly the unique non native interface IDE, as the first.
Ok, so maybe this is why FILO beefs for me. It seems to find the IDE controller at hde, but dumps a message about a floating bus. I've already built filo and coreboot with the patch, but I'm holding off til tomorrow to test, at the moment I need sleep. Everything else IDE-wise looks to be the same. NOTE1: in the epia-cn/Config.lb the IDE and SATA are enabled.
NOTE2: in epia-cn/auto.c the values of PCI_DEV(0,0x11,0) 0x50 and 0x51 are different, for have IDE and SATA enableds at function
And they look like they aren't right? IDE cannot be disabled in the same way the rest of the devs there can. Also 0x51's lower bits control keyboard, mouse, and RTC function.
enable_mainboard_devices NOTE3: Here is a file base.c that haves a udelay with use of rtdsc NOTE4: another function via_cn_fixup, fixes the use of PCI devices access to the memory. Must be improved, and not use a fixed value.
The bus ones are set later during vt8237r lpc_init, so I'm not sure they're needed here (I've been testing with and without them, not seeing a difference), I'll investigate further. The memory bit is set correct during ram init in my lastest iterations. NOTE5: have a change in cn700/raminit.c for configure in CN the memory. I've confirmed these values to work with my Corsair and A-data memory too.
NOTE6: vt8237r configures the SATA device as an IDE class 0x0101 must be 0x0180?????
Clearing bit 7 of the SATA's Rx45 allows the sub-class code to be changed. The vt8237r datasheet is floating around the interwebs, it was released by via. There may even be a link to it in the vt8237r code somewhere. Comment on this: + dev = pci_locate_device(PCI_ID(0x1106, 0x3149), 0); + if(dev == PCI_DEV_INVALID) { + print_debug("SATA Controller not found!\n\rUsing 00.f.0 PCI device\r\n"); + dev=PCI_DEV(0,0xf,0); + } If we can't find SATA, it means that for some reason it's probably already disabled, and setting the device statically might hit the IDE controller (since this function's entire purpose is to move the ide controller to where the sata controller is now). And we don't want to be messing up bits on an already flaky IDE controller ;) And lastly: does vga work, and do you use the bochs bios or have you made changes to the emulator so the vga bios will run? -Corey
Do you have any updated patches for the CN10K board? When following your steps for patching for the C7 + CN700 and the Jetway we get undeclared identifier errors in vga.c when building. -Bari Urbez Santana Roma wrote:
Note: for install this patch, you must download the last coreboot SVN, and install first the patch posted by Corey Osgood, that includes CN700/C7 and jetway mainboard.
The filo patch is for correct a problem with FILO when tries to find the IDE disk, if more that one IDE interface is on, and no all IDE's are in native Mode. The count of compatibility interfaces are wrong, and not finds the interface that is marked as a IDE 0x0101 or SATA 0x0180 and not all are native, the search of the io base and control, are wrong.
If this is not correct sorry :)))
If in VT8237R have SATA as an 0101 and the IDE too 0101 class, with this patch, works, because counts corectly the unique non native interface IDE, as the first.
NOTE1: in the epia-cn/Config.lb the IDE and SATA are enabled. NOTE2: in epia-cn/auto.c the values of PCI_DEV(0,0x11,0) 0x50 and 0x51 are different, for have IDE and SATA enableds at function enable_mainboard_devices NOTE3: Here is a file base.c that haves a udelay with use of rtdsc NOTE4: another function via_cn_fixup, fixes the use of PCI devices access to the memory. Must be improved, and not use a fixed value. NOTE5: have a change in cn700/raminit.c for configure in CN the memory. NOTE6: vt8237r configures the SATA device as an IDE class 0x0101 must be 0x0180?????
Urbez Santana.
participants (3)
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bari -
Corey Osgood -
Urbez Santana Roma