diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/acpi_tables.c b/coreboot-v2/src/mainboard/via/epia-cn/acpi_tables.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/acpi_tables.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/acpi_tables.c	2008-02-04 22:58:45.000000000 +0100
@@ -0,0 +1,87 @@
+/*
+ * CoreBOOT ACPI Table support
+ * written by Stefan Reinauer <stepan@openbios.org>
+ * ACPI FADT, FACS, and DSDT table support added by 
+ * Nick Barker <nick.barker9@btinternet.com>, and those portions
+ * (C) Copyright 2004 Nick Barker
+ * (C) Copyright 2005 Stefan Reinauer
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+
+extern unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Nothing to do */
+	return current;
+}
+
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Nothing to do */
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	
+	/* Align ACPI tables to 16byte */
+	start   = ( start + 0x0f ) & -0x10;
+	current = start;
+	
+	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+	
+	acpi_write_rsdp(rsdp, rsdt);
+	acpi_write_rsdt(rsdt);
+	
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk_debug("ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *)current;
+	current += ((acpi_header_t *)AmlCode)->length;
+	memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length);
+	dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
+	dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
+	printk_debug("ACPI:     * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+	printk_debug("ACPI:     * FADT\n");
+
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt,facs,dsdt);
+	acpi_add_table(rsdt,fadt);
+
+	printk_info("ACPI: done.\n");
+	return current;
+}
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/auto.c b/coreboot-v2/src/mainboard/via/epia-cn/auto.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/auto.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/auto.c	2008-02-06 23:55:01.000000000 +0100
@@ -0,0 +1,294 @@
+/*
+ * This file is part of the CoreBOOT project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ * Modified a bit: Urbez Santana.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define CN_RAM_INIT
+#define DEBUG_RAM_SETUP
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#if 0
+#include <cpu/x86/lapic.h>
+#endif
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "northbridge/via/cn700/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "base.c"
+//#include "lib/delay.c"
+//#include "pc80/mc146818rtc_early.c"
+//#include "pc80/udelay_io.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "debug.c"
+
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+
+#include "serial.c"
+//#include "southbridge/via/vt8237/vt8237_ide.c"
+
+#define spd_read_byte(addr, dev) smbus_read_byte(addr, dev)
+#define CN_RAM_INIT
+#include "northbridge/via/cn700/raminit.c"
+
+#include "epiacn.h"
+
+#if 1
+#define LAPIC_BASE_MSR 0x1B
+#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
+#define LAPIC_BASE_MSR_ENABLE (1 << 11)
+#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
+
+#define LAPIC_DEFAULT_BASE 0xfee00000
+
+
+void enable_lapic(void)
+{
+ 
+        msr_t msr;
+        print_debug("ENABLE LAPIC\r\n");
+        msr=rdmsr(LAPIC_BASE_MSR);
+        msr.hi &= 0xffffff00;
+        msr.lo &= 0x000007ff;
+        msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
+        wrmsr(LAPIC_BASE_MSR, msr);
+}
+#endif
+
+/* This function will completely disable the onboard serial ata (SATA) device
+ * and move the IDE (PATA) device from Device 15 function 1 to D15F0 */
+static void disable_sata(device_t lpc_dev)
+{
+	print_debug("Disabling Via SATA, moving IDE to D10F0\r\n");
+	device_t dev;
+	uint8_t enables;
+	dev = pci_locate_device(PCI_ID(0x1106, 0x3149), 0);
+	if(dev == PCI_DEV_INVALID) {
+		print_debug("SATA Controller not found!\n\rUsing 00.f.0 PCI device\r\n");
+        dev=PCI_DEV(0,0xf,0);
+	}
+
+	enables = pci_read_config8(dev, 0xd1);
+	enables |= (1 << 3);
+	pci_write_config8(dev, 0xd1, enables);
+
+	enables = pci_read_config8(dev, 0x49);
+	enables |= (1 << 7);
+	pci_write_config8(dev, 0x49, enables);
+
+	enables = pci_read_config8(lpc_dev, 0x50);
+	enables |= (1 << 3);
+	pci_write_config8(lpc_dev, 0x50, enables);
+}
+
+static void enable_mainboard_devices(device_t lpc_dev) 
+{
+	device_t dev;
+
+
+	// Disable GP2/GP3, to keep mainboard from rebooting automatically
+	pci_write_config8(lpc_dev, 0x98, 0x00);
+
+	pci_write_config8(lpc_dev, 0x50, 0x80);//Devices normally enabled
+	pci_write_config8(lpc_dev, 0x51, 0x91);//Sata enabled. IDE enabled: if not not detected here.
+	pci_write_config8(lpc_dev, 0x58, 0x02);
+	pci_write_config8(lpc_dev, 0x59, 0x80);
+	pci_write_config8(lpc_dev, 0x5b, 0x09);
+
+	dev = pci_locate_device(PCI_ID(0x1106, 0x0571), 0);
+	if(dev == PCI_DEV_INVALID) {
+		print_debug("IDE Controller not found!\n\rUsing 00.f.1 PCI device\r\n");
+        dev=PCI_DEV(0,0xf,1);
+	}
+
+	print_debug("Found IDE controller\r\n");
+	// Make it respond to IO space
+	pci_write_config8(dev, 0x04, 0x07);
+
+	// Compatibility mode addresses
+	pci_write_config32(dev, 0x10, 0);
+	pci_write_config32(dev, 0x14, 0);
+	pci_write_config32(dev, 0x18, 0);
+	pci_write_config32(dev, 0x1c, 0);//mmm, was 0x1b
+
+#define BUS_MASTER_ADDR 0xfe00
+	// Native mode base address
+	pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
+	
+	pci_write_config8(dev, 0x40, 0x4b);//was 0x3
+	pci_write_config8(dev, 0x41, 0xf2);
+	pci_write_config8(dev, 0x42, 0x09);
+	
+	pci_write_config8(dev, 0x50, 0x80);
+	pci_write_config8(dev, 0x51, 0x9b);
+
+	// Force IDE interrput line and pin for compatibility mode.
+	pci_write_config8(dev, 0x3c, 0xff);//was 0x0e
+	pci_write_config8(dev, 0x3d, 0x00);//was 0x00
+	
+}
+
+static void enable_shadow_ram(const struct mem_controller *ctrl) 
+{
+	uint8_t shadowreg;
+	
+	print_debug("Enabling shadow ram\r\n");
+	/* Enable shadow ram as normal dram */
+	/* 0xc0000-0xcffff */
+	pci_write_config8(ctrl->d0f3, 0x80, 0xff);
+	pci_write_config8(ctrl->d0f7, 0x61, 0xff);
+	/* 0xd0000-0xdffff */
+	pci_write_config8(ctrl->d0f3, 0x81, 0xff);
+	pci_write_config8(ctrl->d0f7, 0x62, 0xff);
+	/* 0xe0000-0xeffff */
+	pci_write_config8(ctrl->d0f3, 0x82, 0xff);
+	pci_write_config8(ctrl->d0f7, 0x64, 0xff);
+
+	/* 0xf0000-0xfffff */
+	shadowreg = pci_read_config8(ctrl->d0f3, 0x83);
+	shadowreg |= 0x30;
+	pci_write_config8(ctrl->d0f3, 0x83, 0x30);
+
+	/* Do it again for the vlink controller */
+	shadowreg = pci_read_config8(ctrl->d0f7, 0x63);
+	shadowreg |= 0x30;
+	pci_write_config8(ctrl->d0f7, 0x63, 0x30);
+}
+
+static void print_debug_decimal(int dec)
+{
+    int base;
+    base=1000000000;
+    while(base && dec<base) base/=10;
+    if (!base) {uart_tx_byte('0');return;}
+    while(base)
+    {
+        uart_tx_byte((dec/base)+'0');
+        dec%=10;
+        base/=10;
+    }
+}
+
+#define MSR_IA32_PERF_STATUS            0x00000198
+#define MSR_IA32_PERF_CTL          		0x00000199
+#define MSR_IA32_MISC_ENABLE 			0x000001a0
+
+static void set_c7_speed(void)
+{
+    msr_t msr;
+	print_debug("Enabling C7 Max Speed\n");
+	msr=rdmsr(MSR_IA32_MISC_ENABLE);
+	if (!(msr.lo & 0x10000)) {msr.lo|=0x10000;wrmsr(MSR_IA32_MISC_ENABLE,msr);}
+	msr=rdmsr(MSR_IA32_PERF_STATUS);
+	print_debug("Voltage: ");print_debug_decimal((int)(msr.lo&0xff) * 16 + 700);print_debug(" mV\r\n");
+	print_debug("CPU mult:");print_debug_decimal((int)((msr.lo >> 8) & 0xff));print_debug("\r\n");
+	print_debug("Max Voltage:");print_debug_decimal((int)(msr.hi &0xff) * 16 + 700);print_debug(" mV\r\n");
+	print_debug("Max CPU mult:");print_debug_decimal((int)((msr.hi >> 8) & 0xff));print_debug("\r\n");
+	print_debug("Min Voltage:");print_debug_decimal((int)((msr.hi >> 16) & 0xff) * 16 + 700);print_debug(" mV\r\n");
+	print_debug("Min CPU mult: ");print_debug_decimal((int)((msr.hi >> 24) & 0xff));print_debug("\r\n");
+	//TODO: wait CPU not busy bit 16 & 17 off (STATUS)
+    msr.hi=0;msr.lo=(msr.hi&0xff00)| ((msr.hi>>16)&0x00ff);//Max mult, Min voltage
+    wrmsr(MSR_IA32_PERF_CTL, msr);
+	//TODO: wait CPU transition bit 16 & 17 off (STATUS)
+    udelay(10);
+	msr=rdmsr(MSR_IA32_PERF_STATUS);
+	print_debug("NEW Voltage:"); print_debug_decimal((int)(msr.lo&0xff) * 16 + 700);print_debug(" mV\r\n");
+	print_debug("NEW CPU mult:"); print_debug_decimal((int)((msr.lo >> 8) & 0xff));print_debug("\r\n");
+
+}
+
+static void via_cn_fixup(void)
+{
+    pci_write_config8(PCI_DEV(0,1,0),0x19,0x1);//enable PCI-BRIGDE SECONDARY BUS
+    pci_write_config8(PCI_DEV(0,1,0),0x1a,0x1);//if not, FILO confuses and hangs.
+    //This makes DMA and access to RAM for PCI devices working.
+    //Need revision, i not known what is exactly.
+	pci_write_config8(PCI_DEV(0,0,7), 0x57, 0x20);//was 0x01
+
+}
+
+static void main(unsigned long bist)
+{
+	device_t lpc_dev;
+
+	static const struct mem_controller cn700[] = {
+		{
+			.d0f0 = PCI_DEV(0, 0, 0),
+			.d0f2 = PCI_DEV(0, 0, 2),
+			.d0f3 = PCI_DEV(0, 0, 3),
+			.d0f4 = PCI_DEV(0, 0, 4),
+			.d0f7 = PCI_DEV(0, 0, 7),
+			.d1f0 = PCI_DEV(0, 1, 0),
+			.channel0 = {0x50},
+		},
+	};
+
+	bip(2000,200);
+	bip(5000,200);
+
+	if (bist == 0) {
+		early_mtrr_init();
+		enable_lapic(); 
+	}
+	
+		
+	/* Allows access to all northbridge devices */
+	pci_write_config8(cn700->d0f0, 0x4f, 0x01);
+
+	enable_viacn_serial();
+	uart_init();
+	console_init();
+    print_debug("Init of CN10000\r\n");
+
+	
+	lpc_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+	if (lpc_dev == PCI_DEV_INVALID)
+		die("Southbridge not found!!!\r\n");
+
+	enable_mainboard_devices(lpc_dev);
+//	disable_sata(lpc_dev);
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	/* The purpose of smbus_fixup() is to make sure the smbus is ready for 
+	 * transactions. Always call it just before doing ram init, to make sure
+	 * the ram setup functions recieve good spd data. */
+	enable_smbus();
+	smbus_fixup(cn700);
+
+	enable_shadow_ram(cn700);
+	print_debug("Init RAM\r\n");
+	c7_cpu_setup(cn700->d0f2);
+	sdram_set_registers(cn700);
+	sdram_set_spd_registers(cn700);
+	sdram_enable(cn700->d0f3);
+    via_cn_fixup();
+    set_c7_speed();
+}
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/base.c b/coreboot-v2/src/mainboard/via/epia-cn/base.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/base.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/base.c	2008-02-06 23:04:14.000000000 +0100
@@ -0,0 +1,107 @@
+#define CN_CPU_MHZ 1000
+
+//Im not sure that the delay of the delay.c works at the correctly speed. (beeps)
+void udelay(unsigned usecs)
+{
+	long cycles;
+	cycles=CN_CPU_MHZ*usecs;
+	asm volatile(
+		"rdtsc\n"
+		"addl %%eax,%%ecx\n"
+		"rdtsc\n"
+		"subl %%ecx,%%eax\n"
+		"jl .-6\n"
+		:
+		:"c" (cycles)
+        :"eax","edx"
+		);
+}
+
+
+
+//added for debugging...
+static inline void bip(int periode,int msecs)
+{
+	int i;
+	outb(inb(0x61)|3,0x61);
+	outb(0xb6,0x43);
+	outb(periode&0xff,0x42);
+        outb(periode>>8,0x42);
+	msecs/=2;
+        for (i=0;i<msecs;i++) udelay(10);
+        outb(inb(0x61)&0xfc,0x61);
+        for (i=0;i<msecs;i++) udelay(10);
+}
+
+
+#define PCICFG_ADDR(bus,dev,fn,reg)\
+	(0x80000000 | (bus << 16) | (dev<<11 ) | (fn << 8) | (reg & ~3))
+
+
+#define PCIDEV(bus,dev,fn)\
+        ((bus<<8) | (dev<<3) |fn)
+#define CF8	1
+#define CF16	2
+#define CF32	4
+
+
+static uint32_t pci_read_config(int pcidev,int reg,int len)
+{
+        int bus;
+        int dev;
+        int fn;
+        bus=pcidev>>8;dev=(pcidev>>3)&0x1f;fn=pcidev&0x7;
+	outl(PCICFG_ADDR(bus,dev,fn,reg), 0xCF8);
+	udelay(1);
+        switch(len)
+        {
+          case CF8:return inb(0xCFC + (reg&3));
+          case CF16:return inw(0xCFC + (reg&2));
+          case CF32:return inl(0xCFC);
+        }
+	return inl(0xCFC);
+}
+
+static void pci_write_config(int pcidev,int reg, uint32_t val,int len)
+{
+        int bus;
+        int dev;
+        int fn;
+        bus=pcidev>>8;dev=(pcidev>>3)&0x1f;fn=pcidev&0x7;
+	outl(PCICFG_ADDR(bus,dev,fn,reg), 0xCF8);
+	udelay(1);
+        switch(len)
+        {
+          case CF8:outb(val,0xCFC + (reg&3));break;
+          case CF16:outw(val,0xCFC + (reg&2));break;
+          case CF32:outl(val,0xCFC);break;
+        }
+}
+
+
+static int pci_search_device(unsigned int devid)
+{
+        int bus;
+        int dev;
+        int fn;
+	for (bus=0;bus<10;(bus)++)
+	for (dev=0;dev<32;(dev)++)
+	for (fn=0;fn<8;(fn)++)	
+        {
+                unsigned int id;
+                id = pci_read_config(PCIDEV(bus,dev,fn),0,CF32);
+                if (devid==id) 
+                {
+                  print_debug("Found PCI device:");print_debug_hex32(devid);
+                  print_debug(" at:");
+                  print_debug_hex8(bus);print_debug("-");
+                  print_debug_hex8(dev);print_debug("-");
+                  print_debug_hex8(fn);print_debug("\r\n");
+                  return PCIDEV(bus,dev,fn);
+                }
+        }
+        print_debug("PCI device not found:");print_debug_hex32(devid);
+        return -1;
+}
+
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/chip.h b/coreboot-v2/src/mainboard/via/epia-cn/chip.h
--- a/coreboot-v2/src/mainboard/via/epia-cn/chip.h	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/chip.h	2007-05-23 00:46:43.000000000 +0200
@@ -0,0 +1,5 @@
+extern struct chip_operations mainboard_via_epia_cn_ops;
+
+struct mainboard_via_epia_cn_config {
+	int nothing;
+};
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout b/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout
--- a/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/cmos.layout	2004-04-23 00:31:49.000000000 +0200
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/Config.lb b/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
--- a/coreboot-v2/src/mainboard/via/epia-cn/Config.lb	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/Config.lb	2008-02-06 18:31:05.000000000 +0100
@@ -0,0 +1,208 @@
+##
+## Compute the location and size of where this firmware image
+## (coreBOOT plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The coreBOOT bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of coreBOOT will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreBOOT,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+object vgabios.o
+
+if HAVE_ACPI_TABLES
+	object fadt.o
+	object dsdt.o
+	object acpi_tables.o
+end
+
+##
+## Romcc output
+##
+makerule ./failover.E
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E 
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc 
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit coreBOOT entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where coreBOOT is entered)
+##
+if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of coreBOOT startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds 
+	mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files 
+##
+dir /pc80
+config chip.h
+
+chip northbridge/via/cn700
+
+	device apic_cluster 0 on
+		chip cpu/via/model_centaur
+			device apic 0 on  end 
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 0.0 on end # AGP Bridge
+		device pci 0.1 on end # Error Reporting
+		device pci 0.2 on end # Host Bus Control
+		device pci 0.3 on end # Memory Controller
+		device pci 0.4 on end # Power Management
+		device pci 0.7 on end # V-Link Controller
+		device pci 1.0 on # PCI Bridge
+			#chip drivers/pci/onboard
+				device pci 0.0 on end
+			#	register "rom_address" = "0xfff80000" #512k image
+			#end # Onboard Video
+		end # PCI Bridge
+		chip southbridge/via/vt8237r
+
+		            #both IDE channels
+	        	    register "ide0_enable" = "1"
+	        	    register "ide1_enable" = "1"
+        	    #both cables are 80pin   
+	            register "ide0_80pin_cable" = "1"
+        	    register "ide1_80pin_cable" = "1"   
+	            #enables the functions of SB
+	            register "fn_ctrl_lo" = "0x80"
+	            register "fn_ctrl_hi" = "0x91"
+
+
+			device pci 0f.0 on  end # RAID VT6420
+			device pci 0f.1 on  end # IDE
+
+			device pci 10.0 on end # USB 1.1
+			device pci 10.1 on end # USB 1.1
+			device pci 10.2 on end # USB 1.1
+			device pci 10.3 on end # USB 1.1
+			device pci 10.4 on end # USB 2
+
+			device pci 11.0 on      # Southbridge
+				chip superio/via/vt1211
+					device pnp 2e.0 on	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 on	# Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 3
+					end
+					device pnp 2e.2 on	# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on	# COM2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.b on	# HWM
+						io 0x60 = 0xec00
+					end
+
+				end
+			end
+			
+			device pci 11.5 on  end # AC97 Audio
+			device pci 12.0 on  end # Ethernet
+		end
+	end
+end
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/debug.c b/coreboot-v2/src/mainboard/via/epia-cn/debug.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/debug.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/debug.c	2008-01-19 01:20:18.000000000 +0100
@@ -0,0 +1,89 @@
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		print_debug_pci_dev(dev);
+		print_debug("\r\n");
+	}
+}
+
+static void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\r\n");
+	
+	for(i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		dump_pci_device(dev);
+	}
+}
+
+
+static void dump_io_resources(unsigned port) 
+{
+
+	int i;
+        udelay(2000);
+        print_debug_hex16(port);
+        print_debug(":\r\n");
+        for(i = 0; i < 256; i++) {
+                uint8_t val;
+                if ((i & 0x0f) == 0) {
+                        print_debug_hex8(i);
+                        print_debug_char(':');
+                }
+                val = inb(port);
+                print_debug_char(' ');
+                print_debug_hex8(val);
+                if ((i & 0x0f) == 0x0f) {
+                        print_debug("\r\n");
+                }
+		port++;
+        }
+}
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/dsdt.asl b/coreboot-v2/src/mainboard/via/epia-cn/dsdt.asl
--- a/coreboot-v2/src/mainboard/via/epia-cn/dsdt.asl	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/dsdt.asl	2008-01-27 21:19:10.000000000 +0100
@@ -0,0 +1,257 @@
+/*
+ * Minimalist ACPI DSDT table for EPIA-M / MII
+ * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ *
+ * 
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+	/*  
+	 * Define the main processor
+	 */
+	Scope (\_PR)
+	{
+		Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
+	}
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 * any others would involve declaring the wake up methods
+	 */
+	Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
+
+	/* Root of the bus hierarchy */
+	Scope (\_SB)
+    	{
+		/* Define how interrupt Link A is plumbed in */ 
+		Device (LNKA)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x01)
+			/* Status - always return ready */
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0B)
+ 			}
+			/* Current Resources - return irq set up in BIOS */  
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+				{
+					IRQ (Level, ActiveLow, Shared) {5}
+				})
+				Return (BUFF)
+                	}
+			/* Possible Resources - return the range of irqs
+ 			 * we are using for PCI - only here to keep Linux ACPI
+			 * happy 
+			 */
+			Method (_PRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+                    		{
+					IRQ (Level, ActiveLow, Shared) {5,9,10}
+                    		})
+                    		Return (BUFF)
+                	}
+			/* Set Resources - dummy function to keep Linux ACPI happy
+                         * Linux is more than happy not to tinker with irq
+			 * assignments as long as the CRS and STA functions 
+			 * return good values
+			 */
+			Method (_SRS, 1, NotSerialized ) {}
+			/* Disable - dummy function to keep Linux ACPI happy */
+			Method (_DIS, 0, NotSerialized ) {}
+ 
+		} // End of LNKA 
+
+		/* Define how interrupt Link B is plumbed in */ 
+		Device (LNKB)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x02)
+			/* Status - always return ready */
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0B)
+ 			}
+			/* Current Resources - return irq set up in BIOS */  
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+				{
+					IRQ (Level, ActiveLow, Shared) {9}
+				})
+				Return (BUFF)
+                	}
+			/* Possible Resources - return the range of irqs
+			 * we are using for PCI - only here to keep Linux ACPI
+			 * happy 
+			 */
+			Method (_PRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+                    		{
+					IRQ (Level, ActiveLow, Shared) {5,9,10}
+                    		})
+                    		Return (BUFF)
+                	}
+			/* Set Resources - dummy function to keep Linux ACPI happy
+                         * Linux is more than happy not to tinker with irq
+			 * assignments as long as the CRS and STA functions 
+			 * return good values
+			 */
+			Method (_SRS, 1, NotSerialized ) {}
+			/* Disable - dummy function to keep Linux ACPI happy */
+			Method (_DIS, 0, NotSerialized ) {}
+ 
+		} // End of LNKB
+
+		/* Define how interrupt Link C is plumbed in */ 
+		Device (LNKC)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x03)
+			/* Status - always return ready */
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0B)
+ 			}
+			/* Current Resources - return irq set up in BIOS */  
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+				{
+					IRQ (Level, ActiveLow, Shared) {9}
+				})
+				Return (BUFF)
+                	}
+			/* Possible Resources - return the range of irqs
+			 * we are using for PCI - only here to keep Linux ACPI
+			 * happy 
+			 */
+			Method (_PRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+                    		{
+					IRQ (Level, ActiveLow, Shared) {5,9,10}
+                    		})
+                    		Return (BUFF)
+                	}
+			/* Set Resources - dummy function to keep Linux ACPI happy
+                         * Linux is more than happy not to tinker with irq
+			 * assignments as long as the CRS and STA functions 
+			 * return good values
+			 */
+			Method (_SRS, 1, NotSerialized ) {}
+			/* Disable - dummy function to keep Linux ACPI happy */
+			Method (_DIS, 0, NotSerialized ) {}
+ 
+		} // End of LNKC
+
+		/* Define how interrupt Link D is plumbed in */ 
+		Device (LNKD)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x04)
+			/* Status - always return ready */
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0B)
+ 			}
+			/* Current Resources - return irq set up in BIOS */  
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+				{
+					IRQ (Level, ActiveLow, Shared) {5}
+				})
+				Return (BUFF)
+                	}
+			/* Possible Resources - return the range of irqs
+			 * we are using for PCI - only here to keep Linux ACPI
+			 * happy 
+			 */
+			Method (_PRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+                    		{
+					IRQ (Level, ActiveLow, Shared) {5,9,10}
+                    		})
+                    		Return (BUFF)
+                	}
+			/* Set Resources - dummy function to keep Linux ACPI happy
+                         * Linux is more than happy not to tinker with irq
+			 * assignments as long as the CRS and STA functions 
+			 * return good values
+			 */
+			Method (_SRS, 1, NotSerialized ) {}
+			/* Disable - dummy function to keep Linux ACPI happy */
+			Method (_DIS, 0, NotSerialized ) {}
+ 
+		} // End of LNKD 
+
+ 
+		/* top PCI device */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x00)
+
+			/* PCI Routing Table */
+			Name (_PRT, Package () {
+				/* Epia-MII 6000e cardbus: */
+				Package () {0x000AFFFF, 0x00, LNKA, 0x00}, // Cardbus Link A
+				Package () {0x000AFFFF, 0x01, LNKB, 0x00}, // Cardbus Link B
+				Package () {0x000AFFFF, 0x02, LNKC, 0x00}, // Cardbus Link C
+				Package () {0x000AFFFF, 0x03, LNKD, 0x00}, // Cardbus Link D
+
+				Package () {0x000DFFFF, 0x00, LNKB, 0x00}, // Firewire Link B
+				Package () {0x000DFFFF, 0x01, LNKC, 0x00}, // Firewire Link C
+				Package () {0x000DFFFF, 0x02, LNKD, 0x00}, // Firewire Linc D
+				Package () {0x000DFFFF, 0x03, LNKA, 0x00}, // Firewire Link A
+
+				Package () {0x0010FFFF, 0x00, LNKA, 0x00}, // USB Link A
+				Package () {0x0010FFFF, 0x01, LNKB, 0x00}, // USB Link B
+				Package () {0x0010FFFF, 0x02, LNKC, 0x00}, // USB Link C
+				Package () {0x0010FFFF, 0x03, LNKD, 0x00}, // USB Link D
+
+				Package () {0x0011FFFF, 0x00, LNKA, 0x00}, // vtCN700 Link A
+				Package () {0x0011FFFF, 0x01, LNKB, 0x00}, // vtCN700 Link B
+				Package () {0x0011FFFF, 0x02, LNKC, 0x00}, // vtCN700 Link C
+				Package () {0x0011FFFF, 0x03, LNKD, 0x00}, // vtCN700 Link D
+
+				Package () {0x0012FFFF, 0x00, LNKA, 0x00}, // LAN Link A 
+				Package () {0x0012FFFF, 0x01, LNKB, 0x00}, // LAN Link B
+				Package () {0x0012FFFF, 0x02, LNKC, 0x00}, // LAN Link C
+				Package () {0x0012FFFF, 0x03, LNKD, 0x00}, // LAN Link D
+
+				Package () {0x0013FFFF, 0x00, LNKA, 0x00}, // Riser slot LinkA 
+				Package () {0x0013FFFF, 0x01, LNKB, 0x00}, // Riser slot LinkB
+				Package () {0x0013FFFF, 0x02, LNKC, 0x00}, // Riser slot LinkC
+				Package () {0x0013FFFF, 0x03, LNKD, 0x00}, // Riser slot LinkD
+
+				Package () {0x0014FFFF, 0x00, LNKB, 0x00}, // Slot 1, Link B
+				Package () {0x0014FFFF, 0x01, LNKC, 0x00}, // Slot 1, Link C
+				Package () {0x0014FFFF, 0x02, LNKD, 0x00}, // Slot 1, Link D
+				Package () {0x0014FFFF, 0x03, LNKA, 0x00}, // Slot 1, Link A
+                
+				Package () {0x0001FFFF, 0x00, LNKA, 0x00}, // VGA Link A
+				Package () {0x0001FFFF, 0x01, LNKB, 0x00}, // VGA Link B
+				Package () {0x0001FFFF, 0x02, LNKC, 0x00}, // VGA Link C
+				Package () {0x0001FFFF, 0x03, LNKD, 0x00} // VGA Link D
+
+            		})
+
+
+		} // End of PCI0
+
+	} // End of _SB
+
+} // End of Definition Block
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/dsdt.c b/coreboot-v2/src/mainboard/via/epia-cn/dsdt.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/dsdt.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/dsdt.c	2008-01-27 22:59:30.000000000 +0100
@@ -0,0 +1,7 @@
+//Intel ACPI Component Architecture
+//File generated by gendsdt
+unsigned char AmlCode[] =
+{
+#error You must use gendsdt for generate this file.
+};
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/epiacn.h b/coreboot-v2/src/mainboard/via/epia-cn/epiacn.h
--- a/coreboot-v2/src/mainboard/via/epia-cn/epiacn.h	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/epiacn.h	2008-01-19 01:21:33.000000000 +0100
@@ -0,0 +1,53 @@
+/* A series of defines, to tell the code where all devices are. This should eliminate
+ * any searching, but leave searching as an option */
+ 
+/* There must be a better way to impliment this, or something like it */
+
+/* When using these, use device_t x = DxFx, for now */
+#ifdef USE_STATIC_DEVICE_LOCATIONS == 1
+/* Northbridge */
+#define D0F0	PCI_DEV(0,0,0)
+#define D0F1	PCI_DEV(0,0,1)
+#define D0F2	PCI_DEV(0,0,2)
+#define D0F3	PCI_DEV(0,0,3)
+#define D0F4	PCI_DEV(0,0,4)
+#define D0F7	PCI_DEV(0,0,7)
+#define D1F0	PCI_DEV(0,1,0)		/* PCI Bridge */
+#define DAF0	PCI_DEV(0,0xA,0)	/* Firewire */
+/* Southbridge */
+#define DFF0	PCI_DEV(0,0xF,0)	/* SATA Controller, IDE if SATA disabled */
+#define DFF1	PCI_DEV(0,0xF,1)	/* IDE Controller */
+#define D10F0	PCI_DEV(0,0x10,0)	/* USB 1.1 Controllers */
+#define D10F1	PCI_DEV(0,0x10,1)
+#define D10F2	PCI_DEV(0,0x10,2)
+#define D10F3	PCI_DEV(0,0x10,3)
+#define D10F4	PCI_DEV(0,0x10,4)	/* USB 2.0 Controller */
+#define D10F5	PCI_DEV(0,0x10,5)	/* USB 2.0 Communications (?) */
+#define D11F0	PCI_DEV(0,0x11,0)	/* Bus control/Power Management */
+#define D11F5	PCI_DEV(0,0x11,5)	/* AC'97 Codec Controller */
+#define D11F6	PCI_DEV(0,0x11,6)	/* MC'97 Codec Controller */
+#define D12F0	PCI_DEV(0,0x12,0)	/* Via Rhine NIC */
+
+#else
+
+#define D0F0	pci_locate_device(PCI_ID(0x1106, 0x0314)
+#define D0F1	pci_locate_device(PCI_ID(0x1106, 0x1314)
+#define D0F2	pci_locate_device(PCI_ID(0x1106, 0x2314)
+#define D0F3	pci_locate_device(PCI_ID(0x1106, 0x3208)
+#define D0F4	pci_locate_device(PCI_ID(0x1106, 0x4314)
+#define D0F7	pci_locate_device(PCI_ID(0x1106, 0x7314)
+#define D1F0	pci_locate_device(PCI_ID(0x1106, 0xb198)
+
+#define DAF0	pci_locate_device(PCI_ID(0x1106, 0x3044)
+#define DFF0	pci_locate_device(PCI_ID(0x1106, 0x3149)
+#define DFF1	pci_locate_device(PCI_ID(0x1106, 0x0571)
+#define D10F0	pci_locate_device(PCI_ID(0x1106, 0x3038)
+#define D10F1	(D10F0 + PCI_DEV(0,0,1))	/* SlightlyHackish :p */
+#define D10F2	(D10F0 + PCI_DEV(0,0,2))
+#define D10F3	(D10F0 + PCI_DEV(0,0,3))
+#define D10F4	pci_locate_device(PCI_ID(0x1106, 0x3104)
+#define D11F0	pci_locate_device(PCI_ID(0x1106, 0xD104)
+#define D11F5	pci_locate_device(PCI_ID(0x1106, 0x3227)
+#define D11F6	pci_locate_device(PCI_ID(0x1106, 0x3059)
+#define D12F0	pci_locate_device(PCI_ID(0x1106, 0x3065)
+#endif
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/fadt.c b/coreboot-v2/src/mainboard/via/epia-cn/fadt.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/fadt.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/fadt.c	2008-01-28 00:12:47.000000000 +0100
@@ -0,0 +1,11 @@
+//Intel ACPI Component Architecture
+//File generated by genfadt
+#include <string.h>
+#include <arch/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
+    acpi_header_t *header=&(fadt->header);
+
+#error You must use genfadt to generate this file
+}
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/failover.c b/coreboot-v2/src/mainboard/via/epia-cn/failover.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/failover.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/failover.c	2005-11-22 01:07:02.000000000 +0100
@@ -0,0 +1,34 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+
+static unsigned long main(unsigned long bist)
+{
+#if 0
+	/* This is the primary cpu how should I boot? */
+	if (do_normal_boot()) {
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
+	}
+ normal_image:
+	asm volatile ("jmp __normal_image" 
+		: /* outputs */ 
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
+ cpu_reset:
+	asm volatile ("jmp __cpu_reset"
+		: /* outputs */ 
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+ fallback_image:
+#endif
+	return bist;
+}
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c b/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c	2007-05-24 18:38:29.000000000 +0200
@@ -0,0 +1,44 @@
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#ifdef GETPIR
+#include "pirq_routing.h"
+#else
+#include <arch/pirq_routing.h>
+#endif
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*9,	 /* there can be total 9 devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x11<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0xc20,		 /* IRQs devoted exclusively to PCI usage */
+	0x1106,		 /* Vendor */
+	0x596,		 /* Device */
+	0,		 /* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x66,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
+		{0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
+		{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0},
+		{0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+        return copy_pirq_routing_table(addr);
+}
+         
\ No hay ningún carácter de nueva línea al final del fichero
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c b/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/mainboard.c	2008-01-27 21:23:26.000000000 +0100
@@ -0,0 +1,46 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "chip.h"
+
+void vga_enable_console();
+
+
+static void vga_fixup(void) {
+        // we do this right here because:
+        // - all the hardware is working, and some VGA bioses seem to need
+        //   that
+        // - we need page 0 below for linuxbios tables.
+
+        printk_debug("INSTALL REAL-MODE IDT\n");
+        setup_realmode_idt();
+        printk_debug("DO THE VGA BIOS\n");
+        do_vgabios();
+        post_code(0x93);
+	vga_enable_console();
+
+
+}
+ 
+ /*
+void write_protect_vgabios(void)
+{
+ 	device_t dev;
+ 
+ 	printk_info("write_protect_vgabios\n");
+	// UniChrome Pro IGP. 
+ 	dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3344, 0);
+ 	if(dev)
+ 		pci_write_config8(dev, 0x61, 0xaa);
+
+}
+*/
+
+
+struct chip_operations mainboard_via_epia_cn_ops = {
+	CHIP_NAME("VIA EPIA-CN Mainboard")
+};
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/Options.lb b/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
--- a/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2008-02-04 16:58:53.000000000 +0100
@@ -0,0 +1,139 @@
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+uses HAVE_ACPI_TABLES
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_UDELAY_TSC
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_MAX_PCI_BUSES 
+uses TTYS0_BAUD
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE  = 256*1024
+
+###
+### Build options
+###
+default CONFIG_PCI_ROM_RUN=0
+default CONFIG_CONSOLE_VGA=0
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## no MP table
+##
+default HAVE_MP_TABLE=0
+
+##
+## Use TSC for udelay.
+##
+default CONFIG_UDELAY_TSC=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=5
+
+
+##
+## Build code to load acpi tables
+##
+default HAVE_ACPI_TABLES=1
+
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+default FALLBACK_SIZE = 131072
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+
+default _RAMBASE = 0x00004000
+
+default CONFIG_ROM_PAYLOAD     = 1
+
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Set this to the max PCI bus number you 
+## would ever use for PCI config IO.
+## Setting this number very high will make 
+## pci_locate_device take a long time when
+## it can't find a device.
+##
+default CONFIG_MAX_PCI_BUSES = 5	 
+end
+
+default CONFIG_VIDEO_MB = 32
+default AGP_APERTURE_SIZE = 32
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/reset.c b/coreboot-v2/src/mainboard/via/epia-cn/reset.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/reset.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/reset.c	2004-04-17 04:36:47.000000000 +0200
@@ -0,0 +1,43 @@
+#if 0
+//#include "arch/romcc_io.h"
+#include <arch/io.h>
+
+typedef unsigned device_t;
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFF) << 16) | \
+	(((DEV) & 0x1f) << 11) | \
+	(((FN)  & 0x7) << 8))
+
+static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+{
+        unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+	unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+	unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
+}
+#endif
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/serial.c b/coreboot-v2/src/mainboard/via/epia-cn/serial.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/serial.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/serial.c	2008-02-04 22:50:30.000000000 +0100
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the CoreBOOT project.
+ *
+ * Comes from another VIA serial initialization.
+ * Adapted by Urbez Santana i Roma <urbez@linuxupc.upc.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+// Base Address are 0x3F8
+
+static void pnp_on(void)
+{
+	outb(0x87, 0x2e);
+	outb(0x87, 0xeb);//Micro delay
+	outb(0x87, 0x2e);
+	outb(0x87, 0xeb);//Micro delay
+}
+
+static void pnp_off(void)
+{
+	outb(0xaa, 0x2e);
+	outb(0xaa, 0xeb);//Micro delay
+}
+
+static void write_pnp(uint8_t addr,uint8_t val) 
+{
+	outb(addr, 0x2e);
+	outb(addr, 0xeb);//Micro delay
+	outb(val, 0x2f);
+	outb(val, 0xeb);//Micro delay
+}
+
+static void enable_viacn_serial(void) 
+{
+	pnp_on();
+	write_pnp(0x7, 0x2);// set address	
+	write_pnp(0x30, 0x1);// enable output
+	write_pnp(0x60,0xfe);// COM1 base address (FEh)
+	
+	write_pnp(0x70,0x4);// COM1 IRQ=0x04, must disable interrupt for BIOS	
+	write_pnp(0xf0,0x2);//COM1 Control
+	pnp_off();
+	// set up reg to set baud rate.
+	outb(0x80,0x3fb);
+	// Set 115 kb
+	outw(1,0x3f8);
+	//no parity, one stop, 8 bits
+	outb(3,0x3fb);
+	// now turn on RTS, DRT
+	outb(3,0x3fc);
+}
+
+
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/vgabios.c b/coreboot-v2/src/mainboard/via/epia-cn/vgabios.c
--- a/coreboot-v2/src/mainboard/via/epia-cn/vgabios.c	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/vgabios.c	2008-02-04 16:57:41.000000000 +0100
@@ -0,0 +1,839 @@
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#undef __KERNEL__
+#include <arch/io.h>
+//#include <printk.h>
+#include <string.h>
+#include "vgachip.h"
+
+/* vgabios.c. Derived from: */
+
+/*------------------------------------------------------------ -*- C -*-
+ *  2 Kernel Monte a.k.a. Linux loading Linux on x86
+ *
+ *  Erik Arjan Hendriks <hendriks@lanl.gov>
+ *
+ *  This version is a derivative of the original two kernel monte
+ *  which is (C) 2000 Scyld.
+ *
+ *  Copyright (C) 2000 Scyld Computing Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Portions related to the alpha architecture are:
+ *
+ *  Copyright(C) 2001 University of California.  LA-CC Number 01-67.
+ *  This software has been authored by an employee or employees of the
+ *  University of California, operator of the Los Alamos National
+ *  Laboratory under Contract No.  W-7405-ENG-36 with the U.S.
+ *  Department of Energy.  The U.S. Government has rights to use,
+ *  reproduce, and distribute this software. If the software is
+ *  modified to produce derivative works, such modified software should
+ *  be clearly marked, so as not to confuse it with the version
+ *  available from LANL.
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License, incorporated herein by
+ *  reference to http://www.gnu.org/licenses/gpl.html.
+ *
+ *  This software is provided by the author(s) "as is" and any express
+ *  or implied warranties, including, but not limited to, the implied
+ *  warranties of merchantability and fitness for a particular purpose
+ *  are disclaimed.  In no event shall the author(s) be liable for any
+ *  direct, indirect, incidental, special, exemplary, or consequential
+ *  damages (including, but not limited to, procurement of substitute
+ *  goods or services; loss of use, data, or profits; or business
+ *  interruption) however caused and on any theory of liability,
+ *  whether in contract, strict liability, or tort (including
+ *  negligence or otherwise) arising in any way out of the use of this
+ *  software, even if advised of the possibility of such damage.
+ *
+ *  $Id: vgabios.c,v 1.5 2004/10/06 17:33:52 rminnich Exp $
+ *--------------------------------------------------------------------*/
+
+/* Modified to be a self sufficient plug in so that it can be used 
+   without reliance on other parts of core Coreboot 
+   (C) 2005 Nick.Barker9@btinternet.com
+
+  Used initially for epia-m where there are problems getting the bios
+  emulator to successfully run this bios.
+*/
+
+/* Declare a temporary global descriptor table - necessary because the
+   Core part of the bios no longer sets up any 16 bit segments */
+__asm__ (
+	/* pointer to original gdt */
+	"gdtarg:			\n"
+	"	.word	gdt_limit	\n"
+	"	.long	gdt	       	\n"		
+
+	/* compute the table limit */
+	"__mygdt_limit = __mygdt_end - __mygdt - 1	\n"
+
+	"__mygdtaddr:			\n"
+	"	.word	__mygdt_limit  	\n"
+	"	.long	__mygdt	       	\n"
+
+	"__mygdt: 		       	\n"
+	/* selgdt 0, unused */
+	"	.word	0x0000, 0x0000	\n"
+	"	.byte	0x00, 0x00, 0x00, 0x00	\n"
+
+	/* selgdt 8, unused */
+	"	.word	0x0000, 0x0000	       	\n"
+	"	.byte	0x00, 0x00, 0x00, 0x00	\n"
+
+	/* selgdt 0x10, flat code segment */
+	"	.word	0xffff, 0x0000	       	\n"
+	"	.byte	0x00, 0x9b, 0xcf, 0x00	\n"	
+
+	/* selgdt 0x18, flat data segment */
+	"	.word	0xffff, 0x0000	       	\n"
+	"	.byte	0x00, 0x93, 0xcf, 0x00	\n"
+
+	/* selgdt 0x20, unused */
+	"	.word	0x0000, 0x0000	       	\n"
+	"	.byte	0x00, 0x00, 0x00, 0x00	\n"
+
+        /* selgdt 0x28 16-bit 64k code at 0x00000000 */
+	"	.word	0xffff, 0x0000	       	\n"
+	"	.byte	0, 0x9a, 0, 0	       	\n"
+
+	/* selgdt 0x30 16-bit 64k data at 0x00000000 */
+	"	.word	0xffff, 0x0000	       	\n"
+	"	.byte	0, 0x92, 0, 0	       	\n"
+
+	"__mygdt_end:				\n"
+);
+
+/* Declare a pointer to where our idt is going to be i.e. at mem zero */
+__asm__ ("__myidt:		\n"
+	 /* 16-bit limit */
+	 "	.word 1023	\n"
+	 /* 24-bit base */
+	 "	.long 0		\n"
+	 "	.word 0		\n"
+);
+
+/* The address arguments to this function are PHYSICAL ADDRESSES */ 
+static void real_mode_switch_call_vga(unsigned long devfn)
+{
+	__asm__ __volatile__ (
+		// paranoia -- does ecx get saved? not sure. This is 
+		// the easiest safe thing to do.
+		"	pushal			\n"
+		/* save the stack */
+		"	mov 	%esp, __stack	\n"
+		"	jmp 	1f		\n"
+		"__stack: .long 0		\n"
+		"1:\n"
+		/* get devfn into %ecx */
+		"	movl    %esp, %ebp	\n"
+		"	movl    8(%ebp), %ecx	\n"
+		/* load 'our' gdt */
+		"	lgdt	%cs:__mygdtaddr	\n"
+
+		/*  This configures CS properly for real mode. */
+		"	ljmp	$0x28, $__rms_16bit\n"
+		"__rms_16bit:		  	\n"
+		"	.code16			\n"
+		/* 16 bit code from here on... */
+
+		/* Load the segment registers w/ properly configured segment
+		 * descriptors.  They will retain these configurations (limits,
+		 * writability, etc.) once protected mode is turned off. */
+		"	mov	$0x30, %ax	\n"
+		"	mov	%ax, %ds       	\n"
+		"	mov	%ax, %es       	\n"
+		"	mov	%ax, %fs       	\n"
+		"	mov	%ax, %gs       	\n"
+		"	mov	%ax, %ss       	\n"
+
+		/* Turn off protection (bit 0 in CR0) */
+		"	movl	%cr0, %eax	\n"
+		"	andl	$0xFFFFFFFE, %eax \n"
+		"	movl	%eax, %cr0	\n"
+
+		/* Now really going into real mode */
+		"	ljmp	$0,  $__rms_real\n"
+		"__rms_real:			\n"
+
+		/* put the stack at the end of page zero. 
+		 * that way we can easily share it between real and protected, 
+		 * since the 16-bit ESP at segment 0 will work for any case. 
+		/* Setup a stack */
+		"	mov	$0x0, %ax	\n"
+		"	mov	%ax, %ss	\n"
+		"	movl	$0x1000, %eax	\n"
+		"	movl	%eax, %esp	\n"
+
+		/* Load our 16 it idt */
+		"	xor	%ax, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	lidt	__myidt		\n"
+
+		/* Dump zeros in the other segregs */
+		"	mov	%ax, %es       	\n"
+		"	mov	%ax, %fs       	\n"
+		"	mov	%ax, %gs       	\n"
+		"	mov	$0x40, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	mov	%cx, %ax	\n"
+
+		/* run VGA BIOS at 0xc000:0003 */
+		"	lcall	$0xc000, $0x0003\n"
+
+		/* if we got here, just about done. 
+		 * Need to get back to protected mode */
+		"	movl	%cr0, %eax	\n"
+		"	orl	$0x0000001, %eax\n" /* PE = 1 */
+		"	movl	%eax, %cr0	\n"
+
+		/* Now that we are in protected mode jump to a 32 bit code segment. */
+		"	data32	ljmp	$0x10, $vgarestart\n"
+		"vgarestart:\n"
+		"	.code32\n"
+		"	movw	$0x18, %ax     	\n"
+		"	mov	%ax, %ds       	\n"
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+		"	mov	%ax, %ss	\n"
+
+		/* restore proper gdt and idt */
+		"	lgdt	%cs:gdtarg	\n"
+		"	lidt	idtarg		\n"
+
+		".globl vga_exit		\n"
+		"vga_exit:			\n"
+		"	mov	__stack, %esp	\n"
+		"	popal			\n"
+		);
+}
+
+__asm__ (".text\n""real_mode_switch_end:\n");
+extern char real_mode_switch_end[];
+
+/* call vga bios int 10 function 0x4f14 to enable main console 
+   epia-m does not always autosence the main console so forcing it on is good !! */ 
+void vga_enable_console()
+{
+	__asm__ __volatile__ (
+		/* paranoia -- does ecx get saved? not sure. This is 
+		 * the easiest safe thing to do. */
+		"	pushal			\n"
+		/* save the stack */
+		"	mov	%esp, __stack	\n"
+
+		/* load 'our' gdt */
+		"	lgdt 	%cs:__mygdtaddr	\n"
+
+		/*  This configures CS properly for real mode. */
+		"	ljmp 	$0x28, $__vga_ec_16bit\n"
+		"__vga_ec_16bit:		\n"
+		"	.code16			\n"
+		/* 16 bit code from here on... */
+
+		/* Load the segment registers w/ properly configured segment
+		 * descriptors.  They will retain these configurations (limits,
+		 * writability, etc.) once protected mode is turned off. */
+		"	mov	$0x30, %ax     	\n"
+		"	mov	%ax, %ds       	\n"
+		"	mov	%ax, %es       	\n"
+		"	mov	%ax, %fs       	\n"
+		"	mov	%ax, %gs       	\n"
+		"	mov	%ax, %ss       	\n"
+
+		/* Turn off protection (bit 0 in CR0) */
+		"	movl	%cr0, %eax     	\n"
+		"	andl	$0xFFFFFFFE, %eax\n"
+		"	movl	%eax, %cr0     	\n"
+
+		/* Now really going into real mode */
+		"	ljmp	$0, $__vga_ec_real \n"
+		"__vga_ec_real:                  \n"
+
+		/* put the stack at the end of page zero. 
+		 * that way we can easily share it between real and protected, 
+		 * since the 16-bit ESP at segment 0 will work for any case. 
+		/* Setup a stack */
+		"	mov	$0x0, %ax	\n"
+		"	mov	%ax, %ss	\n"
+		"	movl	$0x1000, %eax	\n"
+		"	movl	%eax, %esp	\n"
+
+		/* debugging for RGM */
+		"	mov	$0x11, %al	\n"
+		"	outb	%al, $0x80	\n"
+
+		/* Load our 16 it idt */
+		"	xor	%ax, %ax       	\n"
+		"	mov	%ax, %ds	\n"
+		"	lidt	__myidt		\n"
+
+		/* Dump zeros in the other segregs */
+		"	mov	%ax, %ds	\n"
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+
+		/* ask bios to enable main console */
+		/* set up for int 10 call - values found from X server
+		 * bios call routines */
+		"	movw	$0x4f14,%ax	\n"
+		"	movw	$0x8003,%bx	\n"
+		"	movw	$1, %cx		\n"
+		"	movw	$0, %dx		\n"
+		"	movw	$0, %di		\n"
+		"	int	$0x10		\n"
+
+		"	movb	$0x55, %al	\n"
+		"	outb	%al, $0x80	\n"
+
+		/* if we got here, just about done. 
+		 * Need to get back to protected mode */
+		"	movl	%cr0, %eax	\n"
+		"	orl	$0x0000001, %eax\n" /* PE = 1 */
+		"	movl	%eax, %cr0	\n"
+
+		/* Now that we are in protected mode jump to a 32 bit code segment. */
+		"	data32	ljmp	$0x10, $vga_ec_restart\n"
+		"vga_ec_restart:\n"
+		"	.code32\n"
+		"	movw	$0x18, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+		"	mov	%ax, %ss	\n"
+
+		/* restore proper gdt and idt */
+		"	lgdt	%cs:gdtarg 	\n"
+		"	lidt	idtarg		\n"
+		"	.globl	vga__ec_exit	\n"
+		"vga_ec_exit:\n"
+		"	mov	__stack, %esp	\n"
+		"	popal\n"
+		);
+}
+
+void do_vgabios(void)
+{
+	device_t dev;
+	unsigned long busdevfn;
+	unsigned int rom = 0;
+	unsigned char *buf;
+	unsigned int size = 64*1024;
+	int i;
+	
+	/* clear vga bios data area */
+	for (i = 0x400; i < 0x500; i++) {
+		*(unsigned char *) i = 0;
+	}
+
+	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0);
+
+	if (!dev) {
+		printk_debug("NO VGA FOUND\n");
+		return;
+	}
+	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+
+	/* declare rom address here - keep any config data out of the way
+	 * of core LXB stuff */
+
+	rom = 0xfff80000;
+	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
+	printk_debug("rom base, size: %x\n", rom);
+
+	buf = (unsigned char *) rom;
+	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
+		memcpy((void *) 0xc0000, buf, size);
+
+//		write_protect_vgabios();  // in northbridge
+
+	  	// check signature again
+		buf = (unsigned char *) 0xc0000;
+		if (buf[0]==0x55 && buf[1]==0xAA) {
+			busdevfn = (dev->bus->secondary << 8) | dev->path.u.pci.devfn;
+			printk_debug("bus/devfn = %#x\n", busdevfn);
+
+		    	real_mode_switch_call_vga(busdevfn);
+		} else
+			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+	} else 
+		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+
+	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
+}
+
+
+// we had hoped to avoid this. 
+// this is a stub IDT only. It's main purpose is to ignore calls 
+// to the BIOS. 
+// no longer. Dammit. We have to respond to these.
+struct realidt {
+	unsigned short offset, cs;
+}; 
+
+// from a handy writeup that andrey found.
+
+// handler. 
+// There are some assumptions we can make here. 
+// First, the Top Of Stack (TOS) is located on the top of page zero. 
+// we can share this stack between real and protected mode. 
+// that simplifies a lot of things ...
+// we'll just push all the registers on the stack as longwords, 
+// and pop to protected mode. 
+// second, since this only ever runs as part of coreboot, 
+// we know all the segment register values -- so we don't save any.
+// keep the handler that calls things small. It can do a call to 
+// more complex code in coreboot itself. This helps a lot as we don't
+// have to do address fixup in this little stub, and calls are absolute
+// so the handler is relocatable.
+void handler(void)
+{
+	__asm__ __volatile__ ( 
+		"	.code16		\n"
+		"idthandle:		\n"
+		"	pushal		\n"
+		"	movb 	$0, %al	\n"
+		"	ljmp 	$0, $callbiosint16\n"
+		"end_idthandle:		\n"
+		"	.code32		\n"
+		);
+}
+
+void debughandler(void)
+{
+	__asm__ __volatile__ ( 
+		"	.code16		\n"
+		"debughandle:		\n"
+		"	pushw	%cx	\n"
+		"	movw	$250, %cx \n"
+		"dbh1:			\n"
+		"	loop	dbh1	\n"
+		"	popw	%cx	\n"
+		"	iret		\n"
+		"end_debughandle:	\n"
+		".code32		\n"
+		);
+}
+
+// Calling conventions. The first C function is called with this stuff
+// on the stack. They look like value parameters, but note that if you
+// modify them they will go back to the INTx function modified. 
+// the C function will call the biosint function with these as
+// REFERENCE parameters. In this way, we can easily get 
+// returns back to the INTx caller (i.e. vgabios)
+void callbiosint(void)
+{
+	__asm__ __volatile__ (
+		"	.code16		\n"
+		"callbiosint16:		\n"
+		"	push	%ds	\n"
+		"	push	%es	\n"
+		"	push	%fs	\n"
+		"	push	%gs	\n"
+		// clean up the int #. To save space we put it in the lower
+		// byte. But the top 24 bits are junk. 
+		"	andl	$0xff, %eax\n"
+		// this push does two things:
+		// - put the INT # on the stack as a parameter
+		// - provides us with a temp for the %cr0 mods.
+		"	pushl	%eax	\n"
+		"	movl    %cr0, %eax\n"
+		"	orl	$0x00000001, %eax\n" /* PE = 1 */
+		"	movl	%eax, %cr0\n"
+		/* Now that we are in protected mode jump to a 32 bit code segment. */
+		"	data32  ljmp    $0x10, $biosprotect\n"
+		"biosprotect:		\n"
+		"	.code32		\n"
+		"	movw	$0x18, %ax          \n"
+		"	mov	%ax, %ds          \n"
+		"	mov	%ax, %es          \n"
+		"	mov	%ax, %fs          \n"
+		"	mov	%ax, %gs          \n"
+		"	mov	%ax, %ss          \n"
+		"	lidt	idtarg         \n"
+		"	call	biosint	\n"
+		// back to real mode ...
+		"	ljmp	$0x28, $__rms_16bit2\n"
+		"__rms_16bit2:			\n"
+		"	.code16			\n"
+		/* 16 bit code from here on... */
+		/* Load the segment registers w/ properly configured segment
+		 * descriptors.  They will retain these configurations (limits,
+		 * writability, etc.) once protected mode is turned off. */
+		"	mov	$0x30, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+		"	mov	%ax, %ss	\n"
+		
+		/* Turn off protection (bit 0 in CR0) */
+		"	movl	%cr0, %eax		\n"
+		"	andl	$0xFFFFFFFE, %eax	\n"
+		"	movl	%eax, %cr0		\n"
+
+		/* Now really going into real mode */
+		"	ljmp $0,  $__rms_real2	\n"
+		"__rms_real2:			\n"
+
+		/* Setup a stack
+		 * FixME: where is esp? */
+		"	mov	$0x0, %ax       \n"
+		"	mov	%ax, %ss	\n"
+
+		/* ebugging for RGM */
+		"	mov	$0x11, %al	\n"
+		"	outb	%al, $0x80	\n"
+
+		/* Load our 16 it idt */
+		"	xor	%ax, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	lidt	__myidt		\n"
+
+		/* Dump zeros in the other segregs */
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+		"	mov	$0x40, %ax	\n"
+		"	mov	%ax, %ds	\n"
+
+		/* pop the INT # that you pushed earlier */
+		"	popl	%eax		\n"
+		"	pop	%gs		\n"
+		"	pop	%fs		\n"
+		"	pop	%es		\n"
+		"	pop	%ds		\n"
+		"	popal			\n"
+		"	iret			\n"
+		"	.code32			\n"
+		);
+}
+
+enum {
+	PCIBIOS = 0x1a, 
+	MEMSIZE = 0x12
+};
+
+int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+	    unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+	    unsigned long *pecx, unsigned long *peax, unsigned long *pflags);
+
+int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+		unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+		unsigned long *pecx, unsigned long *peax, unsigned long *pflags
+        );
+
+extern void vga_exit(void);
+
+int biosint(unsigned long intnumber,
+	    unsigned long gsfs, unsigned long dses,
+	    unsigned long edi, unsigned long esi,
+	    unsigned long ebp, unsigned long esp, 
+	    unsigned long ebx, unsigned long edx, 
+	    unsigned long ecx, unsigned long eax, 
+	    unsigned long cs_ip, unsigned short stackflags)
+{
+	unsigned long ip; 
+	unsigned long cs; 
+	unsigned long flags;
+	int ret = -1;
+	
+	ip = cs_ip & 0xffff;
+	cs = cs_ip >> 16;
+	flags = stackflags;
+	
+	printk_debug("biosint: INT# 0x%lx\n", intnumber);
+	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
+		      eax, ebx, ecx, edx);
+	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+		     ebp, esp, edi, esi);
+	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+		     ip, cs, flags);
+
+	// cases in a good compiler are just as good as your own tables. 
+	switch (intnumber) {
+	case 0 ... 15:
+		// These are not BIOS service, but the CPU-generated exceptions
+		printk_info("biosint: Oops, exception %u\n", intnumber);
+		if (esp < 0x1000) {
+			printk_debug("Stack contents: ");
+			while (esp < 0x1000) {
+				printk_debug("0x%04x ", *(unsigned short *) esp);
+				esp += 2;
+			}
+			printk_debug("\n");
+		}
+		printk_debug("biosint: Bailing out\n");
+		// "longjmp"
+		vga_exit();
+		break;
+		
+	case PCIBIOS:
+		ret = pcibios( &edi, &esi, &ebp, &esp, 
+			       &ebx, &edx, &ecx, &eax, &flags);
+		break;
+	case MEMSIZE: 
+		// who cares. 
+		eax = 64 * 1024;
+		ret = 0;
+		break;
+	case 0x15:
+		ret=handleint21( &edi, &esi, &ebp, &esp, 
+				&ebx, &edx, &ecx, &eax, &flags);
+		break;
+	default:
+		printk_info("BIOSINT: Unsupport int #0x%x\n", 
+			    intnumber);
+		break;
+	}
+	if (ret)
+		flags |= 1; // carry flags
+	else
+		flags &= ~1;
+	stackflags = flags;
+	return ret;
+} 
+
+
+void setup_realmode_idt(void) 
+{
+	extern unsigned char idthandle, end_idthandle;
+	extern unsigned char debughandle, end_debughandle;
+
+	int i;
+	struct realidt *idts = (struct realidt *) 0;
+	int codesize = &end_idthandle - &idthandle;
+	unsigned char *intbyte, *codeptr;
+	
+	// for each int, we create a customized little handler
+	// that just pushes %ax, puts the int # in %al, 
+	// then calls the common interrupt handler. 
+	// this necessitated because intel didn't know much about 
+	// architecture when they did the 8086 (it shows)
+	// (hmm do they know anymore even now :-)
+	// obviously you can see I don't really care about memory 
+	// efficiency. If I did I would probe back through the stack
+	// and get it that way. But that's really disgusting.
+	for (i = 0; i < 256; i++) {
+		idts[i].cs = 0;
+		codeptr = (char*) 4096 + i * codesize;
+		idts[i].offset = (unsigned) codeptr;
+		memcpy(codeptr, &idthandle, codesize);
+		intbyte = codeptr + 3;
+		*intbyte = i;
+	}
+	
+	// fixed entry points
+	
+	// VGA BIOSes tend to hardcode f000:f065 as the previous handler of
+	// int10. 
+	// calling convention here is the same as INTs, we can reuse
+	// the int entry code.
+	codeptr = (char*) 0xff065;
+	memcpy(codeptr, &idthandle, codesize);
+	intbyte = codeptr + 3;
+	*intbyte = 0x42; /* int42 is the relocated int10 */
+
+	/* debug handler - useful to set a programmable delay between instructions if the
+	   TF bit is set upon call to real mode */
+	idts[1].cs = 0;
+	idts[1].offset = 16384;
+	memcpy(16384, &debughandle, &end_debughandle - &debughandle);
+
+	
+}
+
+
+
+enum {
+	CHECK = 0xb001,
+	FINDDEV = 0xb102,
+	READCONFBYTE = 0xb108,
+	READCONFWORD = 0xb109,
+	READCONFDWORD = 0xb10a,
+	WRITECONFBYTE = 0xb10b,
+	WRITECONFWORD = 0xb10c,
+	WRITECONFDWORD = 0xb10d
+};
+
+// errors go in AH. Just set these up so that word assigns
+// will work. KISS. 
+enum {
+	PCIBIOS_NODEV = 0x8600,
+	PCIBIOS_BADREG = 0x8700
+};
+
+int
+pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, 
+	unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, 
+	unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
+{
+	unsigned long edi = *pedi;
+	unsigned long esi = *pesi;
+	unsigned long ebp = *pebp;
+	unsigned long esp = *pesp;
+	unsigned long ebx = *pebx;
+	unsigned long edx = *pedx;
+	unsigned long ecx = *pecx;
+	unsigned long eax = *peax;
+	unsigned long flags = *pflags;
+	unsigned short func = (unsigned short) eax;
+	int retval = 0;
+	unsigned short devid, vendorid, devfn;
+	short devindex; /* Use short to get rid of garbage in upper half of 32-bit register */
+	unsigned char bus;
+	device_t dev;
+	
+	switch(func) {
+	case  CHECK:
+		*pedx = 0x4350;
+		*pecx = 0x2049;
+		retval = 0;
+		break;
+	case FINDDEV:
+	{
+		devid = *pecx;
+		vendorid = *pedx;
+		devindex = *pesi;
+		dev = 0;
+		while ((dev = dev_find_device(vendorid, devid, dev))) {
+			if (devindex <= 0)
+				break;
+			devindex--;
+		}
+		if (dev) {
+			unsigned short busdevfn;
+			*peax = 0;
+			// busnum is an unsigned char;
+			// devfn is an int, so we mask it off. 
+			busdevfn = (dev->bus->secondary << 8)
+				| (dev->path.u.pci.devfn & 0xff);
+			printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+			*pebx = busdevfn;
+			retval = 0;
+		} else {
+			*peax = PCIBIOS_NODEV;
+			retval = -1;
+		}
+	}
+	break;
+	case READCONFDWORD:
+	case READCONFWORD:
+	case READCONFBYTE:
+	case WRITECONFDWORD:
+	case WRITECONFWORD:
+	case WRITECONFBYTE:
+	{
+		unsigned long dword;
+		unsigned short word;
+		unsigned char byte;
+		unsigned char reg;
+		
+		devfn = *pebx & 0xff;
+		bus = *pebx >> 8;
+		reg = *pedi;
+		dev = dev_find_slot(bus, devfn);
+		if (! dev) {
+			printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
+			*peax = PCIBIOS_BADREG;
+			retval = -1;
+		}
+		switch(func) {
+		case READCONFBYTE:
+			byte = pci_read_config8(dev, reg);
+			*pecx = byte;
+			break;
+		case READCONFWORD:
+			word = pci_read_config16(dev, reg);
+			*pecx = word;
+			break;
+		case READCONFDWORD:
+			dword = pci_read_config32(dev, reg);
+			*pecx = dword;
+			break;
+		case WRITECONFBYTE:
+			byte = *pecx;
+			pci_write_config8(dev, reg, byte);
+			break;
+		case WRITECONFWORD:
+			word = *pecx;
+			pci_write_config16(dev, reg, word);
+			break;
+		case WRITECONFDWORD:
+			dword = *pecx;
+			pci_write_config32(dev, reg, dword);
+			break;
+		}
+		
+		if (retval) 
+			retval = PCIBIOS_BADREG;
+		printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+			     func, bus, devfn, reg, *pecx);
+		*peax = 0;
+		retval = 0;
+	}
+	break;
+	default:
+		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		break;
+	}
+	
+	return retval;
+} 
+
+int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
+		unsigned long *esp, unsigned long *ebx, unsigned long *edx,
+		unsigned long *ecx, unsigned long *eax, unsigned long *flags)
+{
+	int res=-1;
+	switch(*eax&0xffff)
+	{
+	case 0x5f19:
+		break;
+	case 0x5f18:
+		*eax=0x5f;
+		*ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
+		*ecx=0x060;
+		res=0;
+		break;
+	case 0x5f00:
+		*eax = 0x8600;
+		break;
+	case 0x5f01:
+		*eax = 0x5f;
+		*ecx = (*ecx & 0xffffff00 ) | 2; // panel type =  2 = 1024 * 768
+		res = 0;
+		break;
+	case 0x5f02:
+		*eax=0x5f;
+		*ebx= (*ebx & 0xffff0000) | 2;
+		*ecx= (*ecx & 0xffff0000) | 0x401;  // PAL + crt only 
+		*edx= (*edx & 0xffff0000) | 0;  // TV Layout - default
+		res=0;
+		break;
+	case 0x5f0f:
+		*eax=0x860f;
+		break;
+	}
+	return res;
+}
diff -urN a/coreboot-v2/src/mainboard/via/epia-cn/vgachip.h b/coreboot-v2/src/mainboard/via/epia-cn/vgachip.h
--- a/coreboot-v2/src/mainboard/via/epia-cn/vgachip.h	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/src/mainboard/via/epia-cn/vgachip.h	2005-11-22 01:07:02.000000000 +0100
@@ -0,0 +1,10 @@
+#ifndef _PC80_VGABIOS
+#define _PC80_VGABIOS
+
+extern struct chip_control pc80_vgabios_control;
+
+struct pc80_vgabios_config {
+	int nothing;
+};
+
+#endif /* _PC80_VGABIOS */
diff -urN a/coreboot-v2/src/northbridge/via/cn700/raminit.c b/coreboot-v2/src/northbridge/via/cn700/raminit.c
--- a/coreboot-v2/src/northbridge/via/cn700/raminit.c	2008-02-07 00:13:04.000000000 +0100
+++ b/coreboot-v2/src/northbridge/via/cn700/raminit.c	2008-02-06 22:34:27.000000000 +0100
@@ -352,13 +352,22 @@
 	/* (E)MRS values are from the BPG. No direct explanation is given, but 
 	 * they should somehow conform to the JEDEC DDR2 SDRAM Specification
 	 * (JESD79-2C). */
-	do_ram_command(dev, RAM_COMMAND_MRS, 0x0022d8);
-	
+#ifdef CN_RAM_INIT	
+    //with CN10K needs the 20 bit to be active.
+	do_ram_command(dev, RAM_COMMAND_MRS, 0x1022d8);
+
+	/* 7. Mode register set. */
+	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+	do_ram_command(dev, RAM_COMMAND_MRS, 0x121c20);//default OCD calibration
+	do_ram_command(dev, RAM_COMMAND_MRS, 0x120020);//exit calibration mode
+#else
+	do_ram_command(dev, RAM_COMMAND_MRS, 0x22d8);
+
 	/* 7. Mode register set. */
 	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
 	do_ram_command(dev, RAM_COMMAND_MRS, 0x21c20);//default OCD calibration
 	do_ram_command(dev, RAM_COMMAND_MRS, 0x20020);//exit calibration mode
-	
+#endif	
 	/* 8. Normal operation */
 	PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
 	do_ram_command(dev, RAM_COMMAND_NORMAL, 0);
diff -urN a/coreboot-v2/targets/via/epia-cn/Config.lb b/coreboot-v2/targets/via/epia-cn/Config.lb
--- a/coreboot-v2/targets/via/epia-cn/Config.lb	1970-01-01 01:00:00.000000000 +0100
+++ b/coreboot-v2/targets/via/epia-cn/Config.lb	2008-02-06 23:10:40.000000000 +0100
@@ -0,0 +1,45 @@
+# abuild config file for EPIA-CN
+
+target via_epia-cn
+mainboard via/epia-cn
+
+option  MAXIMUM_CONSOLE_LOGLEVEL=9
+option  DEFAULT_CONSOLE_LOGLEVEL=9
+option  CONFIG_CONSOLE_SERIAL8250=1
+
+option ROM_SIZE=0x80000 # 4 mbit
+
+
+
+option HAVE_OPTION_TABLE=1
+option CONFIG_ROM_PAYLOAD=1
+option HAVE_FALLBACK_BOOT=1
+#option CONFIG_COMPRESSED_PAYLOAD_NRV2B=1
+option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
+
+
+###
+### Compute the location and size of where this firmware image
+### (coreBOOT plus bootloader) will live in the boot rom chip.
+###
+option FALLBACK_SIZE=0x80000
+
+## LinuxBIOS C code runs at this location in RAM
+#probemos activado... la posición de ram...
+option _RAMBASE=0x00004000
+
+#
+# Via EPIA CN
+#
+
+romimage "fallback" 
+	option USE_FALLBACK_IMAGE=1
+#	option ROM_IMAGE_SIZE=0x18000
+#	option ROM_IMAGE_SIZE=0x10000
+#	option ROM_SECTION_OFFSET=0x10000
+#	option ROM_SECTION_SIZE=0x30000
+#	option COREBOOT_EXTRA_VERSION=".0-Fallback"
+	payload $(HOME)/filo-0.5/filo.elf
+end
+
+buildrom ./coreboot.rom ROM_SIZE "fallback"
+

