[PATCH] Remove various .c #includes from Intel 440BX/82371EB boards

[Uwe Hermann]

See patch.

This works fine (tested in abuild) for all 440BX boards, but it seems to
break the build of the QEMU target.

I tried to fix it but I don't really know how it can be done. The
problem is (I guess) that the QEMU target is still using ROMCC and
all other 82371EB boards don't (?) Any ideas?

CC         southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o
    GEN        romstage/ldscript.ld
    LINK       coreboot.romstage
build/southbridge/intel/i82371eb/i82371eb_early_pm.romstage.o: In function `enable_pm':
/home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_pm.c:42: undefined reference to `die'
build/southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o: In function `enable_smbus':
/home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c:47: undefined reference to `die'
collect2: ld returned 1 exit status
make: *** [build/coreboot.romstage] Error 1

Uwe.

[PATCH] Remove various .c #includes from Intel 440BX/82371EB boards

[Corey Osgood]

On Thu, Oct 7, 2010 at 5:50 PM, Uwe Hermann  wrote:
> See patch.
>
> This works fine (tested in abuild) for all 440BX boards, but it seems to
> break the build of the QEMU target.
>
> I tried to fix it but I don't really know how it can be done. The
> problem is (I guess) that the QEMU target is still using ROMCC and
> all other 82371EB boards don't (?) Any ideas?
>
> CC         southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o
>    GEN        romstage/ldscript.ld
>    LINK       coreboot.romstage
> build/southbridge/intel/i82371eb/i82371eb_early_pm.romstage.o: In function `enable_pm':
> /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_pm.c:42: undefined reference to `die'
> build/southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o: In function `enable_smbus':
> /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c:47: undefined reference to `die'
> collect2: ld returned 1 exit status
> make: *** [build/coreboot.romstage] Error 1

I think I've found the problem, include/console/console.h:

62 #ifndef __ROMCC__
63 void console_init(void);
64 void post_code(u8 value);
65 void __attribute__ ((noreturn)) die(const char *msg);

Maybe move that definition a few lines up, and see what happens? Or
else converting the QEMU target to CAR seems like the other option.

-Corey
> Uwe.
>
> http://hermann-uwe.de     | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org

[PATCH] Remove various .c #includes from Intel 440BX/82371EB boards

[Warren Turkal]

Any reason not to convert QEMU to car?

Thanks,
wt

On Thu, Oct 7, 2010 at 11:41 PM, Corey Osgood  wrote:
> On Thu, Oct 7, 2010 at 5:50 PM, Uwe Hermann  wrote:
> > See patch.
> >
> > This works fine (tested in abuild) for all 440BX boards, but it seems to
> > break the build of the QEMU target.
> >
> > I tried to fix it but I don't really know how it can be done. The
> > problem is (I guess) that the QEMU target is still using ROMCC and
> > all other 82371EB boards don't (?) Any ideas?
> >
> > CC         southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o
> >    GEN        romstage/ldscript.ld
> >    LINK       coreboot.romstage
> > build/southbridge/intel/i82371eb/i82371eb_early_pm.romstage.o: In function `enable_pm':
> > /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_pm.c:42: undefined reference to `die'
> > build/southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o: In function `enable_smbus':
> > /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c:47: undefined reference to `die'
> > collect2: ld returned 1 exit status
> > make: *** [build/coreboot.romstage] Error 1
>
> I think I've found the problem, include/console/console.h:
>
> 62 #ifndef __ROMCC__
> 63 void console_init(void);
> 64 void post_code(u8 value);
> 65 void __attribute__ ((noreturn)) die(const char *msg);
>
> Maybe move that definition a few lines up, and see what happens? Or
> else converting the QEMU target to CAR seems like the other option.
>
> -Corey
> > Uwe.
> >
> > http://hermann-uwe.de     | http://sigrok.org
> > http://randomprojects.org | http://unmaintained-free-software.org

[PATCH] Remove various .c #includes from Intel 440BX/82371EB boards

[Uwe Hermann]

On Fri, Oct 08, 2010 at 02:41:40AM -0400, Corey Osgood wrote:
> I think I've found the problem, include/console/console.h:
>
> 62 #ifndef __ROMCC__
> 63 void console_init(void);
> 64 void post_code(u8 value);
> 65 void __attribute__ ((noreturn)) die(const char *msg);
>
> Maybe move that definition a few lines up, and see what happens? Or

So far I couldn't find a combination which works, but it's not needed at
the moment, I can dodge the problem by removing the die() calls
alltogether, that was on my TODO list anyways. Those checks in the code
are not really useful, the PCI device is always there, and we don't do
such checks elsewhere in the code either.

Updated patch attached, now survives abuild.
> else converting the QEMU target to CAR seems like the other option.

That won't work as far as I've heard (QEMU limitations).

Uwe.

[PATCH] Remove various .c #includes from Intel 440BX/82371EB boards

[Idwer Vollering]

2010/10/9 Uwe Hermann
> On Fri, Oct 08, 2010 at 02:41:40AM -0400, Corey Osgood wrote:
> > I think I've found the problem, include/console/console.h:
> >
> > 62 #ifndef __ROMCC__
> > 63 void console_init(void);
> > 64 void post_code(u8 value);
> > 65 void __attribute__ ((noreturn)) die(const char *msg);
> >
> > Maybe move that definition a few lines up, and see what happens? Or
>
> So far I couldn't find a combination which works, but it's not needed at
> the moment, I can dodge the problem by removing the die() calls
> alltogether, that was on my TODO list anyways. Those checks in the code
> are not really useful, the PCI device is always there, and we don't do
> such checks elsewhere in the code either.
>
> Updated patch attached, now survives abuild.

Note that compilation breaks when using CONFIG_DEBUG_RAM_SETUP=y.

Apart from that:

Signed-off-by: Uwe Hermann

Acking the second patch (v4_remove_c_includes_i82371eb_2.patch):
Acked-by: Idwer Vollering
> > else converting the QEMU target to CAR seems like the other option.
>
> That won't work as far as I've heard (QEMU limitations).
> Uwe.
>
> http://hermann-uwe.de     | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org

[PATCH] Remove various .c #includes from Intel 440BX/82371EB boards

[Uwe Hermann]

On Sat, Oct 09, 2010 at 06:41:39PM +0200, Idwer Vollering wrote:
> > Updated patch attached, now survives abuild.
>
> Note that compilation breaks when using CONFIG_DEBUG_RAM_SETUP=y.

Yep, though that was broken on a number of boards already before my
patch, I will fix them all in a follow-up patch.
> Acked-by: Idwer Vollering

Thanks, r5929.

Uwe.

[Stefan Reinauer]

On 09.10.2010, at 03:04, Uwe Hermann  wrote:
> On Fri, Oct 08, 2010 at 02:41:40AM -0400, Corey Osgood wrote:
> > I think I've found the problem, include/console/console.h:
> >
> > 62 #ifndef __ROMCC__
> > 63 void console_init(void);
> > 64 void post_code(u8 value);
> > 65 void __attribute__ ((noreturn)) die(const char *msg);
> >
> > Maybe move that definition a few lines up, and see what happens? Or
>
> So far I couldn't find a combination which works, but it's not needed at
> the moment, I can dodge the problem by removing the die() calls
> alltogether, that was on my TODO list anyways. Those checks in the code
> are not really useful, the PCI device is always there, and we don't do
> such checks elsewhere in the code either.

Is that also true for newer qemus which emulate the q35 chipset? We should make sure coreboot runs nicely on those too.
> Updated patch attached, now survives abuild.
> > else converting the QEMU target to CAR seems like the other option.
>
> That won't work as far as I've heard (QEMU limitations).
> Uwe.
>
> http://hermann-uwe.de     | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org
> <v4_remove_c_includes_i82371eb_2.patch>
>
> coreboot mailing list: [e-mail]
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