HT reset hang on 690G/SB600 board Asus M2A-VM

[Carl-Daniel Hailfinger]

Hi!

I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
SuperIO.

My codebase is a slightly modified amd/dbm690t target. I only changed
the CPU socket to AM2.

coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
bsp_apicid=0x0
core0 started:
SBLink=00
NC node|link=00
rs690_early_setup()
get_cpu_rev EAX=0x50ff2.
CPU Rev is K8_G0.
NB Revision is A12.
rs690_ht_init k8_ht_freq=0.
k8_optimization()
rs690_por_init
sb600_early_setup()
sb600_devices_por_init()
sb600_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is 0x13
sb600_devices_por_init(): IDE Device, BDF:0-20-1
sb600_devices_por_init(): LPC Device, BDF:0-20-3
sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
sb600_devices_por_init(): SATA Device, BDF:0-18-0
sb600_pmio_por_init()
begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
Current fid_cur: 0x2, fid_max: 0xa
Requested fid_new: 0xa
FidVid table step fidvid: 0xa
end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
needs_reset=0x1
ht reset -

It hangs after that soft reset. No POST code, nothing else.

Any insights are appreciated.

Processor info follows:
hilbert:~ # cat /proc/cpuinfo
processor       : 0
vendor_id       : AuthenticAMD
cpu family      : 15
model           : 95
model name      : AMD Athlon(tm) 64 Processor 3000+
stepping        : 2
cpu MHz         : 1800.000
cache size      : 512 KB
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt
rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm svm extapic cr8_legacy
bogomips        : 3602.72
TLB size        : 1024 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp tm stc

Regards,
Carl-Daniel

[Carl-Daniel Hailfinger]

On 11.12.2008 03:03, Carl-Daniel Hailfinger wrote:
> Hi!
>
> I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
> similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
> SuperIO.
>
> My codebase is a slightly modified amd/dbm690t target. I only changed
> the CPU socket to AM2.
>
> coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
> bsp_apicid=0x0
> core0 started:
> SBLink=00
> NC node|link=00
> rs690_early_setup()
> get_cpu_rev EAX=0x50ff2.
> CPU Rev is K8_G0.
> NB Revision is A12.
> rs690_ht_init k8_ht_freq=0.
> k8_optimization()
> rs690_por_init
> sb600_early_setup()
> sb600_devices_por_init()
> sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> SMBus controller enabled, sb revision is 0x13
> sb600_devices_por_init(): IDE Device, BDF:0-20-1
> sb600_devices_por_init(): LPC Device, BDF:0-20-3
> sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> sb600_devices_por_init(): SATA Device, BDF:0-18-0
> sb600_pmio_por_init()
> begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> Current fid_cur: 0x2, fid_max: 0xa
> Requested fid_new: 0xa
> FidVid table step fidvid: 0xa
> end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> needs_reset=0x1
> ht reset -
>
> It hangs after that soft reset. No POST code, nothing else.
>
> Any insights are appreciated.
>
> Processor info follows:
> hilbert:~ # cat /proc/cpuinfo
> processor       : 0
> vendor_id       : AuthenticAMD
> cpu family      : 15
> model           : 95
> model name      : AMD Athlon(tm) 64 Processor 3000+
> stepping        : 2
> cpu MHz         : 1800.000
> cache size      : 512 KB
> fpu             : yes
> fpu_exception   : yes
> cpuid level     : 1
> wp              : yes
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm svm extapic cr8_legacy
> bogomips        : 3602.72
> TLB size        : 1024 4K pages
> clflush size    : 64
> cache_alignment : 64
> address sizes   : 40 bits physical, 48 bits virtual
> power management: ts fid vid ttp tm stc

Attached is a lspci for the proprietary BIOS on my machine.

Regards,
Carl-Daniel

[Bao, Zheng]

Hi,
I doubt if the fid/vid code causes this problem. You can try to remove
the 
Fid/vid code and see if the problem still exists.

--- cache_as_ram_auto.c (revision 3789)
+++ cache_as_ram_auto.c (working copy)
@@ -197,17 +197,7 @@
    rs690_early_setup(); 
    sb600_early_setup();

-	msr=rdmsr(0xc0010042); 
-	printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi,
msr.lo); 
-  
-	enable_fid_change(); 
-	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); 
-	init_fidvid_bsp(bsp_apicid);

-	/* show final fid and vid */ 
-	msr=rdmsr(0xc0010042); 
-	printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi,
msr.lo);

needs_reset = optimize_link_coherent_ht(); 
    needs_reset |= optimize_link_incoherent_ht(sysinfo); 
    printk_debug("needs_reset=0x%x\n", needs_reset);

Joe
-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Carl-Daniel
Hailfinger
Sent: Thursday, December 11, 2008 10:04 AM
To: Coreboot
Subject: [coreboot] HT reset hang on 690G/SB600 board Asus M2A-VM

Hi!

I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
SuperIO.

My codebase is a slightly modified amd/dbm690t target. I only changed
the CPU socket to AM2.

coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
bsp_apicid=0x0
core0 started:
SBLink=00
NC node|link=00
rs690_early_setup()
get_cpu_rev EAX=0x50ff2.
CPU Rev is K8_G0.
NB Revision is A12.
rs690_ht_init k8_ht_freq=0.
k8_optimization()
rs690_por_init
sb600_early_setup()
sb600_devices_por_init()
sb600_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is 0x13
sb600_devices_por_init(): IDE Device, BDF:0-20-1
sb600_devices_por_init(): LPC Device, BDF:0-20-3
sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
sb600_devices_por_init(): SATA Device, BDF:0-18-0
sb600_pmio_por_init()
begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
Current fid_cur: 0x2, fid_max: 0xa
Requested fid_new: 0xa
FidVid table step fidvid: 0xa
end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
needs_reset=0x1
ht reset -

It hangs after that soft reset. No POST code, nothing else.

Any insights are appreciated.

Processor info follows:
hilbert:~ # cat /proc/cpuinfo
processor       : 0
vendor_id       : AuthenticAMD
cpu family      : 15
model           : 95
model name      : AMD Athlon(tm) 64 Processor 3000+
stepping        : 2
cpu MHz         : 1800.000
cache size      : 512 KB
fpu             : yes
fpu_exception   : yes
cpuid level     : 1
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt
rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm svm extapic
cr8_legacy
bogomips        : 3602.72
TLB size        : 1024 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp tm stc

Regards,
Carl-Daniel

[Carl-Daniel Hailfinger]

Hi Joe,

thanks for your patch. I have tried it, but the machine still hangs
after HT reset.

Regards,
Carl-Daniel

On 11.12.2008 03:42, Bao, Zheng wrote:
> Hi,
> I doubt if the fid/vid code causes this problem. You can try to remove
> the 
> Fid/vid code and see if the problem still exists.
>
> --- cache_as_ram_auto.c (revision 3789)
> +++ cache_as_ram_auto.c (working copy)
> @@ -197,17 +197,7 @@
>    rs690_early_setup(); 
>    sb600_early_setup();
> msr=rdmsr(0xc0010042);
> printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi,
>
> msr.lo);
>
> enable_fid_change();
>
> enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
>
> init_fidvid_bsp(bsp_apicid);
>
> /* show final fid and vid */
>
> msr=rdmsr(0xc0010042);
>
> printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi,
>
> msr.lo);
>
> needs_reset = optimize_link_coherent_ht(); 
>    needs_reset |= optimize_link_incoherent_ht(sysinfo); 
>    printk_debug("needs_reset=0x%x\n", needs_reset);
>
> Joe
> -----Original Message-----
> From: [e-mail]
> [mailto:[e-mail]] On Behalf Of Carl-Daniel
> Hailfinger
> Sent: Thursday, December 11, 2008 10:04 AM
> To: Coreboot
> Subject: [coreboot] HT reset hang on 690G/SB600 board Asus M2A-VM
>
> Hi!
>
> I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
> similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
> SuperIO.
>
> My codebase is a slightly modified amd/dbm690t target. I only changed
> the CPU socket to AM2.
>
> coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
> bsp_apicid=0x0
> core0 started:
> SBLink=00
> NC node|link=00
> rs690_early_setup()
> get_cpu_rev EAX=0x50ff2.
> CPU Rev is K8_G0.
> NB Revision is A12.
> rs690_ht_init k8_ht_freq=0.
> k8_optimization()
> rs690_por_init
> sb600_early_setup()
> sb600_devices_por_init()
> sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> SMBus controller enabled, sb revision is 0x13
> sb600_devices_por_init(): IDE Device, BDF:0-20-1
> sb600_devices_por_init(): LPC Device, BDF:0-20-3
> sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> sb600_devices_por_init(): SATA Device, BDF:0-18-0
> sb600_pmio_por_init()
> begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> Current fid_cur: 0x2, fid_max: 0xa
> Requested fid_new: 0xa
> FidVid table step fidvid: 0xa
> end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> needs_reset=0x1
> ht reset -
>
> It hangs after that soft reset. No POST code, nothing else.
>
> Any insights are appreciated.
>
> Processor info follows:
> hilbert:~ # cat /proc/cpuinfo
> processor       : 0
> vendor_id       : AuthenticAMD
> cpu family      : 15
> model           : 95
> model name      : AMD Athlon(tm) 64 Processor 3000+
> stepping        : 2
> cpu MHz         : 1800.000
> cache size      : 512 KB
> fpu             : yes
> fpu_exception   : yes
> cpuid level     : 1
> wp              : yes
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm svm extapic
> cr8_legacy
> bogomips        : 3602.72
> TLB size        : 1024 4K pages
> clflush size    : 64
> cache_alignment : 64
> address sizes   : 40 bits physical, 48 bits virtual
> power management: ts fid vid ttp tm stc
>
> Regards,
> Carl-Daniel

Hi,

Change soft_reset to hard_reset.

Rudolf

----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.

[Myles Watson]

On Thu, Dec 11, 2008 at 2:27 AM,  wrote:
> Hi,
>
> Change soft_reset to hard_reset.
>
> Rudolf

You could also comment out the reset at that point to see how much farther
you get.  It sounds like the reset isn't happening.  Can you tell from the
factory BIOS how the resets are implemented?  Can you find that information
from Linux ACPI handling?  Maybe it uses different IO lines than the
supported board.

Since that reset is to optimize the HT links, it will be a lot slower
without the reset.

Thanks,
Myles

[Carl-Daniel Hailfinger]

Hi,

On 11.12.2008 15:27, Myles Watson wrote:
> On Thu, Dec 11, 2008 at 2:27 AM,  wrote:
> > Change soft_reset to hard_reset.

Sorry, with that change, the machine just keeps resetting.
> You could also comment out the reset at that point to see how much farther
> you get.  It sounds like the reset isn't happening.  Can you tell from the
> factory BIOS how the resets are implemented?  Can you find that information
> from Linux ACPI handling?  Maybe it uses different IO lines than the
> supported board.
>
> Since that reset is to optimize the HT links, it will be a lot slower
> without the reset.

I added code to skip the reset and now it boots further. Boot log is
attached.
My RAM configuration was two DIMMs with 2 GB each (4 GB total), but
coreboot only sees 2 GB total, so I removed one of the DIMMS. The boot
log is with that one DIMM only.

This is my diff against dbm690t:
Index: src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- src/mainboard/amd/dbm690t/Config.lb	(Revision 3808)
+++ src/mainboard/amd/dbm690t/Config.lb	(Arbeitskopie)
@@ -198,7 +198,7 @@
 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 chip northbridge/amd/amdk8/root_complex
    device apic_cluster 0 on
-		chip cpu/amd/socket_S1G1
+		chip cpu/amd/socket_AM2
    	device apic 0 on end
    	end
    end
@@ -214,8 +214,8 @@
    					end
    				end
    				device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x1914
+					#device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x7914
    				device pci 5.0 on end # PCIE P2P bridge 0x7915
    				device pci 6.0 on end # PCIE P2P bridge 0x7916
    				device pci 7.0 on end # PCIE P2P bridge 0x7917
Index: src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- src/mainboard/amd/dbm690t/Options.lb	(Revision 3808)
+++ src/mainboard/amd/dbm690t/Options.lb	(Arbeitskopie)
@@ -289,9 +289,9 @@
 ## SPEW       9   Way too many details

## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  DEFAULT_CONSOLE_LOGLEVEL=9
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  MAXIMUM_CONSOLE_LOGLEVEL=9

##
 ## Select power on after power fail setting
Index: src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- src/mainboard/amd/dbm690t/cache_as_ram_auto.c	(Revision 3808)
+++ src/mainboard/amd/dbm690t/cache_as_ram_auto.c	(Arbeitskopie)
@@ -213,10 +213,12 @@
    printk_debug("needs_reset=0x%x\n", needs_reset);

-	if (needs_reset) {
+	if (0 && needs_reset) {
    	print_info("ht reset -\r\n");
    	soft_reset();
    }
+	print_info("FIXME: Skipping ht reset -\r\n");
+	post_code(0xcc);

allow_all_aps_stop(bsp_apicid);

Regards,
Carl-Daniel

[Stefan Reinauer]

Carl-Daniel Hailfinger wrote:
> Hi!
>
> I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
> similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
> SuperIO.
>
> My codebase is a slightly modified amd/dbm690t target. I only changed
> the CPU socket to AM2.
>
> coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
> bsp_apicid=0x0
> core0 started:
> SBLink=00
> NC node|link=00
> rs690_early_setup()
> get_cpu_rev EAX=0x50ff2.
> CPU Rev is K8_G0.
> NB Revision is A12.
> rs690_ht_init k8_ht_freq=0.
> k8_optimization()
> rs690_por_init
> sb600_early_setup()
> sb600_devices_por_init()
> sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> SMBus controller enabled, sb revision is 0x13
> sb600_devices_por_init(): IDE Device, BDF:0-20-1
> sb600_devices_por_init(): LPC Device, BDF:0-20-3
> sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> sb600_devices_por_init(): SATA Device, BDF:0-18-0
> sb600_pmio_por_init()
> begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> Current fid_cur: 0x2, fid_max: 0xa
> Requested fid_new: 0xa
> FidVid table step fidvid: 0xa
> end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> needs_reset=0x1
> ht reset -
>
> It hangs after that soft reset. No POST code, nothing else.

Comment out the FidVid stuff and try again. If that does not help,
disable link speed changes and try again.

[Carl-Daniel Hailfinger]

On 11.12.2008 17:49, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
> > Hi!
> >
> > I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
> > similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
> > SuperIO.
> >
> > My codebase is a slightly modified amd/dbm690t target. I only changed
> > the CPU socket to AM2.
> >
> > coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
> > bsp_apicid=0x0
> > core0 started:
> > SBLink=00
> > NC node|link=00
> > rs690_early_setup()
> > get_cpu_rev EAX=0x50ff2.
> > CPU Rev is K8_G0.
> > NB Revision is A12.
> > rs690_ht_init k8_ht_freq=0.
> > k8_optimization()
> > rs690_por_init
> > sb600_early_setup()
> > sb600_devices_por_init()
> > sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> > SMBus controller enabled, sb revision is 0x13
> > sb600_devices_por_init(): IDE Device, BDF:0-20-1
> > sb600_devices_por_init(): LPC Device, BDF:0-20-3
> > sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> > sb600_devices_por_init(): SATA Device, BDF:0-18-0
> > sb600_pmio_por_init()
> > begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> > Current fid_cur: 0x2, fid_max: 0xa
> > Requested fid_new: 0xa
> > FidVid table step fidvid: 0xa
> > end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> > needs_reset=0x1
> > ht reset -
> >
> > It hangs after that soft reset. No POST code, nothing else.
>
> Comment out the FidVid stuff and try again. If that does not help,
> disable link speed changes and try again.

Good news.
FidVid is OK.
Coherent HT optimization is OK.
Incoherent HT optimization causes the hang.

I have added incoherent HT debugging.

coreboot-2.0.0.0-failover Do 11. Dez 19:20:08 CET 2008 starting...
bsp_apicid=0x0
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
SBLink=00
NC node|link=00
rs690_early_setup()
get_cpu_rev EAX=0x50ff2.
CPU Rev is K8_G0.
NB Revision is A12.
rs690_ht_init k8_ht_freq=0.
k8_optimization()
rs690_por_init
sb600_early_setup()
sb600_devices_por_init()
sb600_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is 0x13
sb600_devices_por_init(): IDE Device, BDF:0-20-1
sb600_devices_por_init(): LPC Device, BDF:0-20-3
sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
sb600_devices_por_init(): SATA Device, BDF:0-18-0
sb600_pmio_por_init()
begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
Current fid_cur: 0x2, fid_max: 0xa
Requested fid_new: 0xa
FidVid table step fidvid: 0xa
end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0xd2, unfiltered freq_cap=0x65
pos=0xd2, filtered freq_cap=0x65
freq_cap1=0x75, freq_cap2=0x65
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
needs_reset=0x1
ht reset -

and it hangs here again.

I'll try to reduce maximum allowed link frequency and retest.

Regards,
Carl-Daniel

[Myles Watson]

> sysinfo->link_pair_num=0x1
> entering ht_optimize_link
> pos=0x8a, unfiltered freq_cap=0x8075
> pos=0x8a, filtered freq_cap=0x75
> pos=0xd2, unfiltered freq_cap=0x65
> pos=0xd2, filtered freq_cap=0x65
> freq_cap1=0x75, freq_cap2=0x65
> dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
> dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
> width_cap1=0x11, width_cap2=0x11
> dev1 input ln_width1=0x4, ln_width2=0x4
> dev1 input width=0x1
> dev1 output ln_width1=0x4, ln_width2=0x4
> dev1 input|output width=0x11
> old dev1 input|output width=0x11
> dev2 input|output width=0x11
> old dev2 input|output width=0x11
> after ht_optimize_link for link pair 0, reset_needed=0x1
> after optimize_link_read_pointers_chain, reset_needed=0x1
> needs_reset=0x1
> ht reset -
>
> and it hangs here again.
>
> I'll try to reduce maximum allowed link frequency and retest.

Same symptoms of incorrect reset code to me.  If that's the problem, it will
hang as long as there's a reset called.  I think it's unlikely that the
problem is the link width or frequency if the other board works with the
same chips.

Thanks,
Myles

[Carl-Daniel Hailfinger]

On 11.12.2008 19:31, Carl-Daniel Hailfinger wrote:
> On 11.12.2008 17:49, Stefan Reinauer wrote:
> > Carl-Daniel Hailfinger wrote:
> > > Hi!
> > >
> > > I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
> > > similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
> > > SuperIO.
> > >
> > > My codebase is a slightly modified amd/dbm690t target. I only changed
> > > the CPU socket to AM2.
> > >
> > > coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
> > > bsp_apicid=0x0
> > > core0 started:
> > > SBLink=00
> > > NC node|link=00
> > > rs690_early_setup()
> > > get_cpu_rev EAX=0x50ff2.
> > > CPU Rev is K8_G0.
> > > NB Revision is A12.
> > > rs690_ht_init k8_ht_freq=0.
> > > k8_optimization()
> > > rs690_por_init
> > > sb600_early_setup()
> > > sb600_devices_por_init()
> > > sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> > > SMBus controller enabled, sb revision is 0x13
> > > sb600_devices_por_init(): IDE Device, BDF:0-20-1
> > > sb600_devices_por_init(): LPC Device, BDF:0-20-3
> > > sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> > > sb600_devices_por_init(): SATA Device, BDF:0-18-0
> > > sb600_pmio_por_init()
> > > begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> > > Current fid_cur: 0x2, fid_max: 0xa
> > > Requested fid_new: 0xa
> > > FidVid table step fidvid: 0xa
> > > end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> > > needs_reset=0x1
> > > ht reset -
> > >
> > > It hangs after that soft reset. No POST code, nothing else.
> >
> > Comment out the FidVid stuff and try again. If that does not help,
> > disable link speed changes and try again.
>
> Good news.
> FidVid is OK.
> Coherent HT optimization is OK.
> Incoherent HT optimization causes the hang.
>
> I have added incoherent HT debugging.
>
> coreboot-2.0.0.0-failover Do 11. Dez 19:20:08 CET 2008 starting...
> bsp_apicid=0x0
> Enabling routing table for node 00 done.
> Enabling UP settings
> Disabling read/write/fill probes for UP... done.
> coherent_ht_finalize
> done
> core0 started:
> SBLink=00
> NC node|link=00
> rs690_early_setup()
> get_cpu_rev EAX=0x50ff2.
> CPU Rev is K8_G0.
> NB Revision is A12.
> rs690_ht_init k8_ht_freq=0.
> k8_optimization()
> rs690_por_init
> sb600_early_setup()
> sb600_devices_por_init()
> sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> SMBus controller enabled, sb revision is 0x13
> sb600_devices_por_init(): IDE Device, BDF:0-20-1
> sb600_devices_por_init(): LPC Device, BDF:0-20-3
> sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> sb600_devices_por_init(): SATA Device, BDF:0-18-0
> sb600_pmio_por_init()
> begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> Current fid_cur: 0x2, fid_max: 0xa
> Requested fid_new: 0xa
> FidVid table step fidvid: 0xa
> end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> entering optimize_link_incoherent_ht
> sysinfo->link_pair_num=0x1
> entering ht_optimize_link
> pos=0x8a, unfiltered freq_cap=0x8075
> pos=0x8a, filtered freq_cap=0x75
> pos=0xd2, unfiltered freq_cap=0x65
> pos=0xd2, filtered freq_cap=0x65
> freq_cap1=0x75, freq_cap2=0x65
> dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
> dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
> width_cap1=0x11, width_cap2=0x11
> dev1 input ln_width1=0x4, ln_width2=0x4
> dev1 input width=0x1
> dev1 output ln_width1=0x4, ln_width2=0x4
> dev1 input|output width=0x11
> old dev1 input|output width=0x11
> dev2 input|output width=0x11
> old dev2 input|output width=0x11
> after ht_optimize_link for link pair 0, reset_needed=0x1
> after optimize_link_read_pointers_chain, reset_needed=0x1
> needs_reset=0x1
> ht reset -
>
> and it hangs here again.
>
> I'll try to reduce maximum allowed link frequency and retest.

It works with 800,400,200 MHz.
It fails with 1000 MHz.
I didn't test 600 MHz (not supported by RS690G) and 100 MHz.

I think I found a bug in RS690 init.

Regards,
Carl-Daniel

[Carl-Daniel Hailfinger]

On 11.12.2008 20:25, Carl-Daniel Hailfinger wrote:
> On 11.12.2008 19:31, Carl-Daniel Hailfinger wrote:
> > On 11.12.2008 17:49, Stefan Reinauer wrote:
> > > Carl-Daniel Hailfinger wrote:
> > > > Hi!
> > > >
> > > > I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
> > > > similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
> > > > SuperIO.
> > > >
> > > > My codebase is a slightly modified amd/dbm690t target. I only changed
> > > > the CPU socket to AM2.
> > > >
> > > > coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
> > > > bsp_apicid=0x0
> > > > core0 started:
> > > > SBLink=00
> > > > NC node|link=00
> > > > rs690_early_setup()
> > > > get_cpu_rev EAX=0x50ff2.
> > > > CPU Rev is K8_G0.
> > > > NB Revision is A12.
> > > > rs690_ht_init k8_ht_freq=0.
> > > > k8_optimization()
> > > > rs690_por_init
> > > > sb600_early_setup()
> > > > sb600_devices_por_init()
> > > > sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> > > > SMBus controller enabled, sb revision is 0x13
> > > > sb600_devices_por_init(): IDE Device, BDF:0-20-1
> > > > sb600_devices_por_init(): LPC Device, BDF:0-20-3
> > > > sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> > > > sb600_devices_por_init(): SATA Device, BDF:0-18-0
> > > > sb600_pmio_por_init()
> > > > begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> > > > Current fid_cur: 0x2, fid_max: 0xa
> > > > Requested fid_new: 0xa
> > > > FidVid table step fidvid: 0xa
> > > > end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> > > > needs_reset=0x1
> > > > ht reset -
> > > >
> > > > It hangs after that soft reset. No POST code, nothing else.
> > >
> > > Comment out the FidVid stuff and try again. If that does not help,
> > > disable link speed changes and try again.
> >
> > Good news.
> > FidVid is OK.
> > Coherent HT optimization is OK.
> > Incoherent HT optimization causes the hang.
> >
> > I have added incoherent HT debugging.
> >
> > coreboot-2.0.0.0-failover Do 11. Dez 19:20:08 CET 2008 starting...
> > bsp_apicid=0x0
> > Enabling routing table for node 00 done.
> > Enabling UP settings
> > Disabling read/write/fill probes for UP... done.
> > coherent_ht_finalize
> > done
> > core0 started:
> > SBLink=00
> > NC node|link=00
> > rs690_early_setup()
> > get_cpu_rev EAX=0x50ff2.
> > CPU Rev is K8_G0.
> > NB Revision is A12.
> > rs690_ht_init k8_ht_freq=0.
> > k8_optimization()
> > rs690_por_init
> > sb600_early_setup()
> > sb600_devices_por_init()
> > sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> > SMBus controller enabled, sb revision is 0x13
> > sb600_devices_por_init(): IDE Device, BDF:0-20-1
> > sb600_devices_por_init(): LPC Device, BDF:0-20-3
> > sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> > sb600_devices_por_init(): SATA Device, BDF:0-18-0
> > sb600_pmio_por_init()
> > begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> > Current fid_cur: 0x2, fid_max: 0xa
> > Requested fid_new: 0xa
> > FidVid table step fidvid: 0xa
> > end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> > entering optimize_link_incoherent_ht
> > sysinfo->link_pair_num=0x1
> > entering ht_optimize_link
> > pos=0x8a, unfiltered freq_cap=0x8075
> > pos=0x8a, filtered freq_cap=0x75
> > pos=0xd2, unfiltered freq_cap=0x65
> > pos=0xd2, filtered freq_cap=0x65
> > freq_cap1=0x75, freq_cap2=0x65
> > dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
> > dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
> > width_cap1=0x11, width_cap2=0x11
> > dev1 input ln_width1=0x4, ln_width2=0x4
> > dev1 input width=0x1
> > dev1 output ln_width1=0x4, ln_width2=0x4
> > dev1 input|output width=0x11
> > old dev1 input|output width=0x11
> > dev2 input|output width=0x11
> > old dev2 input|output width=0x11
> > after ht_optimize_link for link pair 0, reset_needed=0x1
> > after optimize_link_read_pointers_chain, reset_needed=0x1
> > needs_reset=0x1
> > ht reset -
> >
> > and it hangs here again.
> >
> > I'll try to reduce maximum allowed link frequency and retest.
>
> It works with 800,400,200 MHz.
> It fails with 1000 MHz.
> I didn't test 600 MHz (not supported by RS690G) and 100 MHz.
>
> I think I found a bug in RS690 init.

Fixed!
RS690 needs a workaround to enable 1 GHz ncHyperTransport.
Let me explain:

200/400/800 MHz ncHT link: NB_CFG_Q_F1000_800 bit 0 must NOT be set.
1000 MHz ncHT link: NB_CFG_Q_F1000_800 bit 0 must be set.

RS690 NB_CFG_Q_F1000_800 (nbconfig:0x9C) is a register mentioned in the
AMD RS690 ASIC Family Register Reference Guide.

I'm using the DBM690T target with the attached modifications. Please
note that my RS690 fixup will cause a hang if ncHT is used at 800 MHz or
less.

Boot log until the hang is attached as well.

Regards,
Carl-Daniel

[Myles Watson]

> -----Original Message-----
> From: [e-mail] [mailto:[e-mail]]
> On Behalf Of Carl-Daniel Hailfinger
> Sent: Thursday, December 11, 2008 1:19 PM
> To: Stefan Reinauer
> Cc: Bao, Zheng; Coreboot
> Subject: Re: [coreboot] HT reset hang on 690G/SB600 board Asus M2A-VM
>
> On 11.12.2008 20:25, Carl-Daniel Hailfinger wrote:
> > On 11.12.2008 19:31, Carl-Daniel Hailfinger wrote:
> > > On 11.12.2008 17:49, Stefan Reinauer wrote:
> > > > Carl-Daniel Hailfinger wrote:
> > > > > Hi!
> > > > >
> > > > > I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
> > > > > similar to the AMD DBM690T. It has a 690G/SB600 chipset and an
>
> IT8716F
> > > > > SuperIO.
> > > > >
> > > > > My codebase is a slightly modified amd/dbm690t target. I only changed
> > > > > the CPU socket to AM2.
> > > > >
> > > > > coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
> > > > > bsp_apicid=0x0
> > > > > core0 started:
> > > > > SBLink=00
> > > > > NC node|link=00
> > > > > rs690_early_setup()
> > > > > get_cpu_rev EAX=0x50ff2.
> > > > > CPU Rev is K8_G0.
> > > > > NB Revision is A12.
> > > > > rs690_ht_init k8_ht_freq=0.
> > > > > k8_optimization()
> > > > > rs690_por_init
> > > > > sb600_early_setup()
> > > > > sb600_devices_por_init()
> > > > > sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> > > > > SMBus controller enabled, sb revision is 0x13
> > > > > sb600_devices_por_init(): IDE Device, BDF:0-20-1
> > > > > sb600_devices_por_init(): LPC Device, BDF:0-20-3
> > > > > sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> > > > > sb600_devices_por_init(): SATA Device, BDF:0-18-0
> > > > > sb600_pmio_por_init()
> > > > > begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> > > > > Current fid_cur: 0x2, fid_max: 0xa
> > > > > Requested fid_new: 0xa
> > > > > FidVid table step fidvid: 0xa
> > > > > end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> > > > > needs_reset=0x1
> > > > > ht reset -
> > > > >
> > > > > It hangs after that soft reset. No POST code, nothing else.
> > > >
> > > > Comment out the FidVid stuff and try again. If that does not help,
> > > > disable link speed changes and try again.
> > >
> > > Good news.
> > > FidVid is OK.
> > > Coherent HT optimization is OK.
> > > Incoherent HT optimization causes the hang.
> > >
> > > I have added incoherent HT debugging.
> > >
> > > coreboot-2.0.0.0-failover Do 11. Dez 19:20:08 CET 2008 starting...
> > > bsp_apicid=0x0
> > > Enabling routing table for node 00 done.
> > > Enabling UP settings
> > > Disabling read/write/fill probes for UP... done.
> > > coherent_ht_finalize
> > > done
> > > core0 started:
> > > SBLink=00
> > > NC node|link=00
> > > rs690_early_setup()
> > > get_cpu_rev EAX=0x50ff2.
> > > CPU Rev is K8_G0.
> > > NB Revision is A12.
> > > rs690_ht_init k8_ht_freq=0.
> > > k8_optimization()
> > > rs690_por_init
> > > sb600_early_setup()
> > > sb600_devices_por_init()
> > > sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> > > SMBus controller enabled, sb revision is 0x13
> > > sb600_devices_por_init(): IDE Device, BDF:0-20-1
> > > sb600_devices_por_init(): LPC Device, BDF:0-20-3
> > > sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> > > sb600_devices_por_init(): SATA Device, BDF:0-18-0
> > > sb600_pmio_por_init()
> > > begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> > > Current fid_cur: 0x2, fid_max: 0xa
> > > Requested fid_new: 0xa
> > > FidVid table step fidvid: 0xa
> > > end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> > > entering optimize_link_incoherent_ht
> > > sysinfo->link_pair_num=0x1
> > > entering ht_optimize_link
> > > pos=0x8a, unfiltered freq_cap=0x8075
> > > pos=0x8a, filtered freq_cap=0x75
> > > pos=0xd2, unfiltered freq_cap=0x65
> > > pos=0xd2, filtered freq_cap=0x65
> > > freq_cap1=0x75, freq_cap2=0x65
> > > dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
> > > dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
> > > width_cap1=0x11, width_cap2=0x11
> > > dev1 input ln_width1=0x4, ln_width2=0x4
> > > dev1 input width=0x1
> > > dev1 output ln_width1=0x4, ln_width2=0x4
> > > dev1 input|output width=0x11
> > > old dev1 input|output width=0x11
> > > dev2 input|output width=0x11
> > > old dev2 input|output width=0x11
> > > after ht_optimize_link for link pair 0, reset_needed=0x1
> > > after optimize_link_read_pointers_chain, reset_needed=0x1
> > > needs_reset=0x1
> > > ht reset -
> > >
> > > and it hangs here again.
> > >
> > > I'll try to reduce maximum allowed link frequency and retest.
> >
> > It works with 800,400,200 MHz.
> > It fails with 1000 MHz.
> > I didn't test 600 MHz (not supported by RS690G) and 100 MHz.
> >
> > I think I found a bug in RS690 init.
>
> Fixed!
> RS690 needs a workaround to enable 1 GHz ncHyperTransport.
> Let me explain:
>
> 200/400/800 MHz ncHT link: NB_CFG_Q_F1000_800 bit 0 must NOT be set.
> 1000 MHz ncHT link: NB_CFG_Q_F1000_800 bit 0 must be set.
>
> RS690 NB_CFG_Q_F1000_800 (nbconfig:0x9C) is a register mentioned in the
> AMD RS690 ASIC Family Register Reference Guide.
>
> I'm using the DBM690T target with the attached modifications. Please
> note that my RS690 fixup will cause a hang if ncHT is used at 800 MHz or
> less.
>
> Boot log until the hang is attached as well.

Great debugging!  I'm glad I was wrong.

I think the fix should go in ht_read_freq_cap or a related function there.

Thanks,
Myles