Author: zbao Date: Sun Oct 10 17:18:53 2010 New Revision: 5930 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5930
Log: Trivial. Spelling check.
Signed-off-by: Zheng Bao zheng.bao@amd.com Acked-by: Zheng Bao zheng.bao@amd.com
Modified: trunk/src/southbridge/amd/sb600/sb600_hda.c trunk/src/southbridge/amd/sb600/sb600_sata.c trunk/src/southbridge/amd/sb600/sb600_sm.c trunk/src/southbridge/amd/sb600/sb600_usb.c trunk/src/southbridge/amd/sb700/sb700_early_setup.c trunk/src/southbridge/amd/sb700/sb700_hda.c trunk/src/southbridge/amd/sb700/sb700_lpc.c trunk/src/southbridge/amd/sb700/sb700_sata.c trunk/src/southbridge/amd/sb700/sb700_sm.c trunk/src/southbridge/amd/sb700/sb700_usb.c
Modified: trunk/src/southbridge/amd/sb600/sb600_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_hda.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb600/sb600_hda.c Sun Oct 10 17:18:53 2010 (r5930) @@ -53,7 +53,7 @@ dword &= mask; } while ((dword != val) && --count);
- /* Timeout occured */ + /* Timeout occurred */ if (!count) return -1; return 0; @@ -169,7 +169,7 @@ }
/** - * Wait 50usec for for the codec to indicate it is ready + * Wait 50usec for the codec to indicate it is ready * no response would imply that the codec is non-operative */ static int wait_for_ready(u32 base) @@ -190,7 +190,7 @@ }
/** - * Wait 50usec for for the codec to indicate that it accepted + * Wait 50usec for the codec to indicate that it accepted * the previous command. No response would imply that the code * is non-operative */
Modified: trunk/src/southbridge/amd/sb600/sb600_sata.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_sata.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb600/sb600_sata.c Sun Oct 10 17:18:53 2010 (r5930) @@ -39,7 +39,7 @@ if (byte != (0xA0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the - * second SATA port is poulated. + * second SATA port is populated. */ printk(BIOS_DEBUG, "drive no longer selected after %i ms, " "retrying init\n", i * 10); @@ -83,7 +83,7 @@ byte = 0x6 << 2; pci_write_config8(sm_dev, 0xaf, byte);
- /* get base addresss */ + /* get base address */ sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
Modified: trunk/src/southbridge/amd/sb600/sb600_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_sm.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb600/sb600_sm.c Sun Oct 10 17:18:53 2010 (r5930) @@ -338,7 +338,7 @@
pci_dev_set_resources(dev);
- /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ + /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ byte = pm_ioread(0x52); byte |= 1 << 6; pm_iowrite(0x52, byte);
Modified: trunk/src/southbridge/amd/sb600/sb600_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_usb.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb600/sb600_usb.c Sun Oct 10 17:18:53 2010 (r5930) @@ -96,7 +96,7 @@ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
- /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ + /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */ dword = 0x00020F00; write32(usb2_bar0 + 0xC0, dword);
Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Sun Oct 10 17:18:53 2010 (r5930) @@ -63,7 +63,7 @@ rev = 0x11; /* A11 */ else if (enable_14Mhz == 0x1) { /* This happens, if does, only once. So later if we need to get - * the rivision ID, we don't have to make such a big function. + * the revision ID, we don't have to make such a big function. * We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */ rev = 0x12; byte = pci_read_config8(dev, 0x40); @@ -549,7 +549,7 @@
/* LPC Device, BDF:0-20-3 */ /* The code below is ported from old chipset. It is not - * metioned in RPR. But I keep them. The registers and the + * mentioned in RPR. But I keep them. The registers and the * comments are compatible. */ dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); /* Enabling LPC DMA function. */
Modified: trunk/src/southbridge/amd/sb700/sb700_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_hda.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_hda.c Sun Oct 10 17:18:53 2010 (r5930) @@ -91,7 +91,7 @@ }
/** - * Wait 50usec for for the codec to indicate it is ready + * Wait 50usec for the codec to indicate it is ready * no response would imply that the codec is non-operative */ static int wait_for_ready(u32 base) @@ -112,7 +112,7 @@ }
/** - * Wait 50usec for for the codec to indicate that it accepted + * Wait 50usec for the codec to indicate that it accepted * the previous command. No response would imply that the code * is non-operative */
Modified: trunk/src/southbridge/amd/sb700/sb700_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_lpc.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_lpc.c Sun Oct 10 17:18:53 2010 (r5930) @@ -108,7 +108,7 @@ /** * @brief Enable resources for children devices * - * @param dev the device whos children's resources are to be enabled + * @param dev the device whose children's resources are to be enabled * */ static void sb700_lpc_enable_childrens_resources(device_t dev)
Modified: trunk/src/southbridge/amd/sb700/sb700_sata.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sata.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_sata.c Sun Oct 10 17:18:53 2010 (r5930) @@ -111,7 +111,7 @@ /* get rev_id */ rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
- /* get base addresss */ + /* get base address */ sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
Modified: trunk/src/southbridge/amd/sb700/sb700_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sm.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_sm.c Sun Oct 10 17:18:53 2010 (r5930) @@ -206,7 +206,7 @@ /* 4.14:Enabling Requester ID for upstream traffic. */ abcfg_reg(0x98, 1 << 16, 1 << 16);
- /* 9.2: Enableing IDE Data Bus DD7 Pull Down Resistor */ + /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */ byte = pm2_ioread(0xE5); byte |= 1 << 2; pm2_iowrite(0xE5, byte); @@ -345,7 +345,7 @@
pci_dev_set_resources(dev);
- /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ + /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ byte = pm_ioread(0x52); byte |= 1 << 6; pm_iowrite(0x52, byte);
Modified: trunk/src/southbridge/amd/sb700/sb700_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_usb.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_usb.c Sun Oct 10 17:18:53 2010 (r5930) @@ -83,7 +83,7 @@ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
- /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ + /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */ dword = 0x00020F00; write32(usb2_bar0 + 0xC0, dword);
@@ -105,8 +105,8 @@ pci_write_config32(dev, 0x50, dword); #endif
- /* RPR6.13 Enabling Fix for EHCI Controller Dirver Yellow Sign Issue */ - /* RPR says it is just for A12. CIMM sets it when it is above A11. */ + /* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */ + /* RPR says it is just for A12. CIMx sets it when it is above A11. */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 20); pci_write_config32(dev, 0x50, dword);
-
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